Synthetic test circuit for valve performance test of HVDC

Abstract

Embodiments of a synthetic test circuit for a valve performance test of high-voltage direct current (HVDC) are presented. In some embodiments, the synthetic test circuit comprises a resonance circuit configured to comprise a first test valve to test an operation of an inverter mode and a second test valve to test an operation of a rectifier mode. The synthetic test circuit may comprise a power supply (P/S) configured to provide the resonance circuit with an operating voltage. The synthetic test circuit may comprise a direct current/direct current (DC/DC) converter configured to bypass a DC offset current of the resonance circuit. The first test valve may be an inverter unit, which may have a positive DC current offset. Further, the second test valve may be a rectifier unit, which may have a negative DC current offset.

Claims

1. A synthetic test circuit for a valve performance test of HVDC, comprising: a resonance circuit comprising a first test valve configured to test an operation of an inverter mode and a second test valve configured to test an operation of a rectifier mode; a power supply (P/S) configured to provide the resonance circuit with an operating voltage; and a DC/DC converter configured to bypass a DC offset current of the resonance circuit, wherein each of the first and second test valves comprises a plurality of sub-modules, each sub-module includes a plurality of IGBTs and a capacitor, wherein a current flowing in a sub-module disposed in the first test valve includes a positive DC current offset, and wherein a current flowing in a sub-module disposed in the second test valve includes a negative DC current offset.

2. The synthetic test circuit of claim 1, wherein the resonance circuit comprises a first inductor(L1) and a second inductor(L2) that are serially connected between the first and second test valves, a first auxiliary valve and a second auxiliary valve that are serially connected between the first and second test valves, and a first capacitor(C3) whose one end is connected to a contact between the first inductor(L1) and the second inductor(L2), and whose other end is connected to a contact between the first auxiliary valve and the second auxiliary valve.

3. The synthetic test circuit of claim 2, wherein the first inductor is connected between IGBTs of the first test valve, the second inductor is connected between IGBTs of the second test valve, the first auxiliary valve is connected between the IGBT and the capacitor of the first test valve, and the second auxiliary valve is connected between the IGBT and the capacitor of the second test valve.

4. The synthetic test circuit of claim 2, wherein the sub-modules comprised in the first and second test valves each comprise two serially connected IGBTs, and a capacitor connected to the IGBTs in parallel.

5. The synthetic test circuit of claim 2, wherein the first auxiliary valve comprises a first IGBT, and a second IGBT and a capacitor that are connected to the first IGBT in parallel and are serially connected with each other, and wherein the second auxiliary valve comprises a third IGBT, and a fourth IGBT and a capacitor that are connected to the third IGBT in parallel and are serially connected with each other.

6. The synthetic test circuit of claim 5, wherein the DC/DC converter is connected to both ends of the capacitor comprised in the first auxiliary valve and to both ends of the capacitor comprised in the second auxiliary valve.

7. The synthetic test circuit of claim 5, wherein the power supply is connected to both ends of the capacitor comprised in the second auxiliary valve to charge the test valve and the auxiliary valve.

8. The synthetic test circuit of claim 5, wherein the first and second IGBTs are connected in antiparallel, and the third and fourth IGBTs are connected in antiparallel.

9. The synthetic test circuit of claim 2, wherein the first and second inductors have the same value.

10. The synthetic test circuit of claim 1, wherein the power supply provides the first and second test valves with an operating voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects and features of the present disclosure will become apparent from the following description of embodiments given in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a view illustrating an example of a synthetic test circuit for a valve performance test, according to the prior art.

(3) FIGS. 2 to 4 are views illustrating operations of synthetic test circuits for a valve performance test, according to the prior art.

(4) FIG. 5 is a view illustrating a configuration of a test valve, according to the prior art.

(5) FIG. 6 is a view illustrating an output voltage of a test valve, according to the prior art.

(6) FIG. 7 is a view illustrating an equivalent circuit of a synthetic test circuit, according to the prior art.

(7) FIG. 8 is a view illustrating a voltage of an inductor, according to the prior art.

(8) FIG. 9 is a view illustrating a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure.

(9) FIG. 10 is a view illustrating a circuit diagram of a specimen to be tested with respect to a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure.

(10) FIG. 11 is a view illustrating switch signals and current waveforms of a rectifier unit sub-module of a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure.

(11) FIG. 12 is a view illustrating switch signals and current waveforms of an inverter unit sub-module with respect to a synthetic test circuit of a valve performance test of HVDC in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION

(12) Hereinafter, preferred embodiments of a synthetic test circuit for a valve performance test of HVDC will be described in detail with reference to the accompanying drawings.

(13) FIG. 9 is a view illustrating a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure, FIG. 10 is a view illustrating a circuit diagram of a specimen to be tested with respect to a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure, FIG. 11 is a view illustrating switch signals and current waveforms of a rectifier unit sub-module of a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure, and FIG. 12 is a view illustrating switch signals and current waveforms of an inverter unit sub-module with respect to a synthetic test circuit of a valve performance test of HVDC in accordance with an embodiment of the present disclosure.

(14) A power converter unit of an MMC based power source HVDC is configured of several tens or hundreds of IGBT valves (sub-modules) that are serially connected, which needs to test the performance before manufacturing it.

(15) It is not possible to simultaneously test tens or hundreds of IGBT valves that are connected serially in the performance test, and it is described in the international regulation that five (5) or more IGBTs that are serially connected are to be tested. The essential device for such a test is a synthetic test circuit.

(16) Referring to FIG. 9, in a synthetic test circuit for a valve performance test of HVDC in accordance with an embodiment of the present disclosure, a test valve of a rectifier REC unit in the right side is indicated as two IGBTs (Q.sub.RU-D.sub.RU and Q.sub.RD-D.sub.RD) and a capacitor C.sub.R. In an actual configuration, however, the test valve may be formed of six (6) serially connected IGBT valves (sub-valves) that are same as illustrated in FIG. 10 and it may correspond to a specimen to be tested. Further, a unit indicated as an inverter INV in the left side is also same with the rectifier REC unit and corresponds to a specimen to be tested, too.

(17) Since a characteristic of the IGBT valve configuring the power source HVDC when it operates at a rectifier REC mode is different from that when it operates at an inverter INV mode, the test is needed in each operation mode. However, some embodiments of the present disclosure may provide a structure with which both operation modes can be tested simultaneously.

(18) Referring to FIG. 9, two serially connected inductors L.sub.1 and L.sub.2 that exist between the inverter INV unit and the rectifier REC unit have the same value and get involved in a current flowing. A capacitor C.sub.3 interposed therebetween is connected to a contact between the inductors L.sub.1 and L.sub.2, which serves to treat a current ripple of the inductors L.sub.1 and L.sub.2. Four IGBTs (Q.sub.I1, D.sub.I2, Q.sub.R1 and D.sub.R2) and two capacitors (C.sub.1 and C.sub.2) at the lower stage serve to bypass a DC component of the current flowing through the L.sub.1 and L.sub.2, and this process is performed through the DC/DC converter. An external power applied to perform the operation in FIG. 9 may be supplied by a P/S (Power Supply).

(19) That is, according to some embodiments of the present disclosure, there is included a resonance circuit comprising a first test valve to test an operation of an inverter mode and a second test valve to test an operation of a rectifier mode. Further, the P/S supplies the resonance circuit with an operating power. In detail, the P/S may supply the first and second test valves configuring the resonance circuit with an operating power. The first and second test valves may include a plurality of serially connected sub-modules, and each sub-module may include a plurality of IGBTs and a capacitor. The first test valve may be an inverter INV unit, and the second test valve may be a rectifier REC unit.

(20) The sub-modules included in the first and second test valves each may include two (2) serially connected IGBTs, and a capacitor connected to the IGBTs in parallel.

(21) The first test valve has an end connected to the first inductor L.sub.1 and the other end connected to the first auxiliary valve. The second test valve has an end connected to the second inductor L.sub.2 and the other end connected to the second auxiliary valve.

(22) The first inductor L.sub.1 is connected between IGBTs of the first test valve and the first auxiliary valve is connected between the IGBT and a capacitor of the first test valve. The second inductor L.sub.2 is connected between IGBTs of the second test valve and the second auxiliary valve is connected between the IGBT and a capacitor of the second test valve.

(23) The first auxiliary valve may include two (2) IGBTs (Q.sub.11 and Q.sub.12) and a capacitor C.sub.1, the IGBT (Q.sub.12) and the capacitor C.sub.1 are connected serially, and the IGBT (Q.sub.11) is connected to the other IGBT (Q.sub.I2) and the capacitor C.sub.1 in parallel. The IGBT (Q.sub.I1) is connected in antiparallel to the other IGBT (Q.sub.I2).

(24) Further, the second auxiliary valve may include two (2) IGBTs (Q.sub.I1 and Q.sub.I2) and a capacitor C.sub.2, the IGBT (Q.sub.R2) and the capacitor C.sub.2 are connected serially, and the IGBT (Q.sub.R1) is in parallel connected to the other IGBT (Q.sub.R2) and the capacitor C.sub.2. The IGBT (Q.sub.R1) is connected in antiparallel to the other IGBT (Q.sub.R2).

(25) The first inductor L.sub.1 is serially connected to the second inductor L.sub.2, and the first auxiliary valve is serially connected to the second auxiliary valve.

(26) One end of the first capacitor C.sub.3 is connected to a contact between the first inductor L.sub.1 and the second inductor L.sub.2, and the other end of the first capacitor C.sub.3 is connected to a contact between the first auxiliary valve and the second auxiliary valve.

(27) The DC/DC converter is connected to both ends of the capacitors C.sub.1 and C.sub.2 included in the first and second auxiliary valves, so that it serves to bypass a DC offset current.

(28) Further, the P/S (Power Supply) is connected to both ends of the capacitor C.sub.2 included in the second auxiliary valve, so that it serves to charge a test valve and an auxiliary valve at an initial start-up operation and compensate for a power loss at a normal operation. The P/S (Power Supply) may charge the capacitors C.sub.1 and C.sub.2, the first capacitor C.sub.3 and the capacitors C.sub.1 and C.sub.R, that are included in the first and second auxiliary valves through a switching control.

(29) Such a synthetic test circuit may be controlled by a control system (not illustrated), which controls switch on/off according to a set operation method to test operations of it on a rectifier mode and a inverter mode.

(30) Referring to FIG. 11, switch signals and current waveforms of a test valve and an auxiliary valve of a rectifier REC unit are as follows. Such conditions as following expressions are required in order to similarly simulate a current waveform flowing through a sub-module when actually operating a voltage source HVDC system.

(31) $V_{C2}=V_{C1}=V_{\mathrm{CR}}=V_{C1}$$V_{C3}=\frac{3}{4}{V}_{C2}$

(32) a. Mode 1 (t.sub.0t<t.sub.1)

(33) When turning on Q.sub.RD and Q.sub.R1, the rectifier input

(34) current i.sub.R rises as follows.

(35) $i_R=\frac{V_{C3}}{L_2}t$

(36) Here, the voltage drop in an ON state of the IGBT valve is ignored and it is assumed that all components are ideal, hereinafter. At t=t.sub.1, Q.sub.RD is turned off.

(37) b. Mode 2 (t.sub.1t<t.sub.2)

(38) When turning off Q.sub.RD, the current flowing through Q.sub.RD

(39) starts to flow through D.sub.RU and the magnitude of the current is as follows. Here, i(t.sub.1) is an instantaneous value of the current flowing at a time

(40) $i_R=i_{\mathrm{DRU}}=i\left(t_1\right)+\frac{\left(V_{C3}-V_{\mathrm{CR}}\right)}{L_2}t=i\left(t_1\right)-\frac{V_{\mathrm{CR}}}{4L_2}t$

(41) c. Mode 3 (t.sub.2t<t.sub.3)

(42) At t=t.sub.2, Q.sub.R1 is turned off and Q.sub.RD is turned on.

(43) Then, the current starts to flow along such a route as C.sub.3.fwdarw.L.sub.2.fwdarw.Q.sub.RD.fwdarw.C.sub.2.fwdarw.D(Q.sub.R2).fwdarw.C.sub.3 and the magnitude of it is as follows.

(44) $i_R=i_{\mathrm{QRD}}=i\left(t_2\right)+\frac{\left(V_{C3}-V_{C2}\right)}{L_2}t=i\left(t_2\right)-\frac{V_{C2}}{4L_2}t$

(45) When such current decreases to 0, Q.sub.RD is turned off.

(46) d. Mode 4 (t.sub.3t<t.sub.4)

(47) At t=t.sub.3, when Q.sub.RU is turned on, the current starts to

(48) increase along such a route as C.sub.R.fwdarw.Q.sub.RU.fwdarw.L.sub.2.fwdarw.C.sub.3.fwdarw.D (Q.sub.R1).fwdarw.C.sub.R.

(49) $i_R=i_{\mathrm{QRU}}=i\left(t_3\right)+\frac{\left(V_{C3}-V_{\mathrm{CR}}\right)}{L_2}t=-\frac{V_{\mathrm{CR}}}{4L_2}t$

(50) e. Mode 5 (t.sub.4t<t.sub.5)

(51) At t=t.sub.4, Q.sub.RU is turned off and Q.sub.R2 is turned on.

(52) Then, the current flowing through the Q.sub.RU is transferred to the D.sub.RD to flow.

(53) $i_R=i_{\mathrm{DRD}}=i\left(t_4\right)+\frac{\left(V_{C3}-V_{C2}\right)}{L_2}t=i\left(t_4\right)-\frac{V_{C2}}{4L_2}t$

(54) f Mode 6 (t.sub.5t<t.sub.6)

(55) At t=t.sub.5, when turning off Q.sub.R2 and turning on Q.sub.RU,

(56) the current moves to Q.sub.RU, again.

(57) $i_R=i_{\mathrm{QRU}}=i\left(t_5\right)+\frac{\left(V_{C3}-V_{\mathrm{CR}}\right)}{L_2}t=i\left(t_5\right)-\frac{V_{\mathrm{CR}}}{4L_2}t$

(58) g. Mode 7 (t.sub.6t<t.sub.7)

(59) At t=t.sub.6, when turning off Q.sub.RU and turning on Q.sub.R2,

(60) the current moves from Q.sub.RU to D.sub.RD.

(61) $i_R=i_{\mathrm{DRD}}=i\left(t_6\right)+\frac{\left(V_{C3}-V_{C2}\right)}{L_2}t=i\left(t_6\right)-\frac{V_{C2}}{4L_2}t$

(62) h. Mode 8 (t.sub.7t<t.sub.8)

(63) At t=t.sub.7, when turning off Q.sub.R2 and turning on Q.sub.RU,

(64) the current moves from D.sub.RD to Q.sub.RU, again.

(65) $i_R=i_{\mathrm{DRU}}=i\left(t_7\right)+\frac{\left(V_{C3}-V_{\mathrm{CR}}\right)}{L_2}t=i\left(t_7\right)-\frac{V_{\mathrm{CR}}}{4L_2}t$

(66) i. Mode 9 (t.sub.8t<t.sub.9)

(67) At t=t.sub.8, when turning off Q.sub.RU and turning on

(68) Q.sub.R1, the current becomes as follows.

(69) 0$i_R=i_{\mathrm{DRD}}=i\left(t_8\right)+\frac{V_{C3}}{L_2}t$

(70) When the magnitude of the current becomes 0, Q.sub.R1 is turned off.

(71) Referring to FIG. 12, switch signals and current waveforms of the test valve and auxiliary valve of the inverter INV unit are as follows. Such conditions as following expressions are required in order to similarly simulate a waveform of a current flowing through a sub-module when actually operating a voltage source HVDC system.

(72) a. Mode 1 (t.sub.0t<t.sub.1)

(73) When turning on Q.sub.ID and Q.sub.I1, the inverter input

(74) current i.sub.I rises as follows.

(75) $i_I=\frac{V_{C3}}{L_1}t$

(76) b. Mode 2 (t.sub.1t<t.sub.2)

(77) At t=t.sub.1, when turning off Q.sub.ID, the current moves

(78) from Q.sub.ID to D.sub.IU.

(79) $i_I=i_{\mathrm{DIU}}=i\left(t_1\right)+\frac{\left(V_{C3}-V_{\mathrm{CI}}\right)}{L_1}t=i\left(t_1\right)-\frac{V_{\mathrm{CI}}}{4L_1}t$

(80) c. Mode 3 (t.sub.2t<t.sub.3)

(81) At t=t.sub.2, when turning on Q.sub.ID, the current moves from D.sub.IU to Q.sub.ID.

(82) $i_I=i_{\mathrm{QID}}=i\left(t_2\right)+\frac{V_{C3}}{L_1}t$

(83) d. Mode 4 (t.sub.3t<t.sub.4)

(84) At t=t.sub.3, when turning off Q.sub.ID, the current moves to

(85) D.sub.IU, again.

(86) $i_I=i_{\mathrm{DIU}}=i\left(t_3\right)+\frac{\left(V_{C3}-V_{\mathrm{CI}}\right)}{L_1}t=i\left(t_3\right)-\frac{V_{\mathrm{CI}}}{4L_1}t$

(87) e. Mode 5 (t.sub.4t<t.sub.5)

(88) At t=t.sub.4, when turning off Q.sub.I1 and turning on Q.sub.I2 and

(89) Q.sub.ID, a reverse voltage is applied to L.sub.1 so that the magnitude of the current starts to decrease.

(90) $i_I=i_{\mathrm{QIU}}=i\left(t_4\right)+\frac{\left(V_{C3}-V_{C1}\right)}{L_1}t=i\left(t_4\right)-\frac{V_{C1}}{4L_1}t$

(91) f. Mode 6 (t.sub.5t<t.sub.6)

(92) At t=t.sub.5, when turning off Q.sub.ID and Q.sub.I2, and turning on

(93) Q.sub.I1, the current moves from Q.sub.ID to D.sub.IU.

(94) $i_I=i_{\mathrm{DIU}}=i\left(t_5\right)+\frac{\left(V_{C3}-V_{\mathrm{CI}}\right)}{L_1}t=i\left(t_5\right)-\frac{V_{\mathrm{CI}}}{4L_1}t$

(95) g. Mode 7 (t.sub.6t<t7)

(96) At t=t.sub.6, when turning off Q.sub.I1 and turning on Q.sub.ID and

(97) Q.sub.I2, the current moves from D.sub.IU to Q.sub.ID.

(98) $i_I=i_{\mathrm{QID}}=i\left(t_6\right)+\frac{\left(V_{C3}-V_{C1}\right)}{L_1}t=i\left(t_6\right)-\frac{V_{C1}}{4L_1}t$

(99) When the current decreases to 0, Q.sub.ID and Q.sub.I2 are turned off.

(100) h. Mode 8 (t.sub.7t<t.sub.8)

(101) At t=t7, when turning on Q.sub.I2, i.sub.I starts to increase

(102) in the minus () direction.

(103) $i_I=i_{\mathrm{QIU}}=i\left(t_7\right)+\frac{\left(V_{C3}-V_{\mathrm{CI}}\right)}{L_1}t=i\left(t_7\right)-\frac{V_{\mathrm{CI}}}{4L_1}t$

(104) i. Mode 9 (t.sub.8t<t.sub.9)

(105) At t=t.sub.8, when turning off Q.sub.IU and turning on Q.sub.I2,

(106) the current moves from Q.sub.IU to D.sub.ID.

(107) $i_I=i_{\mathrm{DID}}=i\left(t_8\right)+\frac{\left(V_{C3}-V_{C1}\right)}{L_1}t=i\left(t_8\right)-\frac{V_{C1}}{4L_1}t$

(108) j. Mode 10 (t.sub.9t<t.sub.10)

(109) At t=t.sub.9, when turning off Q.sub.I2 and turning on Q.sub.IU, the

(110) current moves from D.sub.ID to Q.sub.IU.

(111) 0$i_I=i_{\mathrm{QIU}}=i\left(t_9\right)+\frac{\left(V_{C3}-V_{\mathrm{CI}}\right)}{L_1}t=i\left(t_9\right)-\frac{V_{\mathrm{CI}}}{4L_1}t$

(112) k. Mode 11 (t.sub.10t<t.sub.11)

(113) At t=t.sub.10, when turning off Q.sub.IU, the current moves

(114) from Q.sub.IU to D.sub.ID.

(115) $i_I=i_{\mathrm{DID}}=i\left(t_{10}\right)+\frac{V_{C3}}{L_1}t$

(116) When the current becomes 0, the mode 11 is terminated.

(117) As can be understood from the operations of the rectifier REC unit and the inverter INV unit that are described above, the synthetic test circuit for a valve performance test of HVDC in accordance with some embodiments of the present disclosure may embody a synthetic test circuit that may simulate an actual situation as much as possible by enabling a DC offset to be added.

(118) That is, as can be seen from the current i.sub.R in FIG. 11 and the current i.sub.I in FIG. 12, the first test valve may have a positive DC current offset and the second test valve may have a negative DC current offset.

(119) Since an actual voltage source HVDC may have an offset current in the operation depending on a rectifier mode or an inverter mode, some embodiments of the present disclosure may embody a synthetic test circuit similar to that in such an actual situation, capable of securing the reliability.

(120) Further, the synthetic test circuit for a valve performance test of HVDC in accordance with some embodiments of the present disclosure may enable the current of the valve to be switched in a PWM scheme while controlling the pulse width within one (1) period, which is very similar to an actual situation, thereby maximizing a validity of the test circuit.

(121) In the synthetic test circuit for a valve performance test of HVDC in accordance with some embodiments of the present disclosure, since the power supplied to the synthetic test circuit only needs to provide the loss on the circuit, such as a switch loss of the IGBT valve and a line loss, it is possible to perform a high-power test of an actual capacity using a minimal power that is less than 1% of an actual power. Accordingly, there is an advantage that power consumption is very little in the test facility.

(122) The synthetic test circuit for a valve performance test of HVDC in accordance with some embodiments of the present disclosure may simultaneously test specimens to be tested in the inverter unit and the rectifier unit, thereby contributing to an enhanced productivity.

(123) Some embodiments of the present disclosure may provide a novel configuration of a synthetic test circuit for a valve performance test of HVDC.

(124) Further, some embodiments of the present disclosure may provide a synthetic test circuit for a valve performance test of HVDC, which is capable of providing a current including a DC offset.

(125) Further, some embodiments of the present disclosure may provide a configuration of a synthetic test circuit for a valve performance test of HVDC, which is capable of switching several times within a period.

(126) Further, some embodiments of the present disclosure may provide a synthetic test circuit for a valve performance test of HVDC, which consumes a little power and is capable of simultaneously testing the specimens to be tested of an inverter unit and a rectifier unit.

(127) Hereinbefore, although the present disclosure is described with reference to embodiments, they are only exemplary illustrations and are not to limit the disclosure. It will be clearly understood by those skilled in the art that various modifications and applications not illustrated above are possible without departing basic sprits of the embodiments. For example, each constitutional component illustrated in detail in the embodiments may be embodied in a modified form. Further, differences related to such modifications and applications should be construed to be included in scopes of the present disclosure defined by appended claims.