Wireless data and power transfer over an inductive telemetry link

Abstract

A telemetry device includes a resonant inductive link with a primary LC tank and secondary LC tank configured to resonate at a carrier frequency. A modulator assembly in communication with the secondary LC tank implements data-synchronized cyclic on-off keying modulation (COOK) to periodically create a short across the secondary LC tank in response to a pulse from a phase selector and phase-locked loop. During the full cycle-length of the short, data can be transmitted across the inductive link while the charge across the secondary LC tank is preserved. Power may be transferred across the link during non-shorted cycles.

Claims

1. A telemetry device, comprising: an inductive link comprising an external LC tank and an internal LC tank, wherein the inductive link is resonant at a carrier frequency comprising a plurality of cycles; a switch configured for shorting the internal LC tank in response to a data-synchronized modulation signal; and a modulator assembly configured to implement cyclic on-off keying to open and close the switch, wherein the switch is closed for data transmission and open for power transfer, the modulator assembly comprising: a full wave rectifier; a clock-recovery comparator; a phase-locked loop configured for generating a plurality of pulses; and a phase selector configured to select at least one pulse from the plurality of pulses for input to the rectifier.

2. The telemetry device of claim 1, wherein the modulator assembly causes the switch to close for a full cycle within the plurality of cycles.

3. The telemetry device of claim 1, wherein the carrier frequency is 13.56 MHz.

4. The telemetry device of claim 1, wherein data transmission occurs at a data bit rate on the order of one half of the carrier frequency.

5. The telemetry device of claim 1, wherein the phase selector uses feedback phase selection.

6. The telemetry device of claim 1, wherein the phase selector selects a first pulse for closing the switch and a second pulse for opening the switch.

7. The telemetry device of claim 1, further comprising a data decoder configured for receiving an input data transmission, the data decoder comprising a peak detector and a comparator.

8. The telemetry device of claim 7, wherein the data decoder further comprises a peak-aligning diode configured to set a threshold voltage at the external LC tank.

9. A telemetry device, comprising: a resonant inductive link comprising a primary LC tank and secondary LC tank configured to resonate at a carrier frequency comprising a plurality of cycles; a modulator assembly in communication with the secondary LC tank and configured to implement cyclic on-off keying modulation to periodically create a short across the secondary LC tank in response to a pulse, wherein data is transmitted across the inductive link when the secondary LC tank is shorted and power is transferred across the inductive otherwise, and wherein the modulator assembly comprises: a switch configured for creating the short; a full wave rectifier configured for controlling the switch; a phase-locked loop configured for generating a plurality of pulses; a clock-recovery comparator configured to provide an input to the phase-locked loop; and a phase selector configured to select at least one pulse from the plurality of pulses for input to the rectifier.

10. The telemetry device of claim 9, wherein the modulator assembly causes the switch to close for a full cycle within the plurality of cycles.

11. The telemetry device of claim 9, wherein the data has a bit rate on the order of one-half of the carrier frequency.

12. The telemetry device of claim 9, wherein the phase selector uses feedback phase selection.

13. The telemetry device of claim 9, wherein the phase selector selects a first pulse for closing the switch and a second pulse for opening the switch.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A is a block diagram for an embodiment of the inventive modulation scheme in the power transfer mode; FIG. 1B is a block diagram showing the data transfer mode; FIG. 1C diagrammatically illustrates the proposed modulation scheme; FIG. 1D shows the measured waveforms of the data modulation scheme at the secondary and primary sides.

(2) FIG. 2A is an exemplary system block diagram according to an embodiment of the invention; FIG. 2B is a micrograph of an actual integrated circuit implementation of the embodiment of FIG. 2A; FIG. 2C is a circuit schematic for an exemplary multi-phase PLL and phase selector for use in an embodiment of the invention; FIG. 2D is a circuit schematic for an exemplary full-wave rectifier for use in an embodiment of the invention.

(3) FIG. 3A is an illustration of phase-based rectification; FIG. 3B is a plot of rectified V.sub.DD and power over load current; FIG. 3C shows recorded waveforms for rectification during data transfer.

(4) FIG. 4A is a simplified diagram of an embodiment of the data decoder (RX1) at the primary with the peak-aligning diode; FIG. 4B shows the recorded V.sub.L1 signal for data decoding at the primary, and the effect of the peak-aligning diode on decoding performance.

(5) FIG. 5A illustrates the time-based symbol bit mapping according to an embodiment of the invention; FIG. 5B provides a comparison of the inventive time-based encoding versus a simple encoding approach used in the prior art; FIG. 5C shows recorded transmitted and received data; FIG. 5D is a histogram of the peak values of V.sub.L1.

(6) FIG. 6A is a plot of measured waveforms showing rectification according to an embodiment of the invention; FIG. 6B shows measured signals generated during transmission and rectification; FIG. 6C is a plot of rectified voltage and power with current.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

(7) According to embodiments of the present invention, synchronous cyclic on-off keying (COOK) is exploited to retain almost all stored energy in the LC (inductor-capacitor) resonant tank during modulation of the carrier signal, thus providing the ability to achieve very high data rate with very low power consumption.

(8) Referring to FIGS. 1A and 1B, the block diagram for the inventive data modulation scheme is same as LSKthe difference lies in the timing when it closes the switch and opens the switch. Briefly, the basic components of the inductive telemetry circuit 100 include an external unit 102 and an internal unit 104, with mutually coupled external coil (L.sub.1) 122 and implanted coil (L.sub.2) 124. The degree of coupling between these two coils can be described in terms of M=k{square root over (L.sub.1L.sub.2)} their mutual inductance. The coupling factor, k, corresponds to the proportion of the external coil's 122 field that is captured by the implanted coil 124. The external capacitor (C.sub.1) 126 and the implanted capacitor (C.sub.2) 128 are used to form tuned-in-series external and tuned-in-parallel implanted circuits, respectively. The tuned circuit achieve a high voltage at the output (V.sub.LL) of the implanted unit 104 compared with the voltage at the input of the external unit 102 at the frequency of the carrier signal. At the internal unit 104, the received waveform is demodulated and the originally-transmitted binary data is recovered. The received waveform is rectified (at full wave rectifier 130) and regulated to deliver an appropriate supply voltage to the implant. According to the inventive modulation method, as shown in FIG. 1B, switch 132 is closed when all energy of the LC tank is in inductor 124, so the voltage across the LC tank 124,128 is zero and the current through the inductor 124 is at its maximum.

(9) In addition to the modified modulation scheme, the inventive approach uses a multi-phase phase-locked loop (PLL) to control timing in waveform sampling from the sinusoidal voltage signal in the LC tank to adiabatically convert and regulate power in generating multiple constant voltage supplies and/or time-varying stimulation voltage signals. This approach provides precise supply and waveform control with minimum power losses, saving energy and avoiding heating of biomedical implants and other wireless sensors and actuators.

(10) The inventive approach for uplink data modulation involves closing the switch across the secondary parallel LC tank for an entire single cycle. Referring to FIGS. 1C and 1D, the switch 132 begins to close when the voltage across the inductor (L.sub.2) 124 is zero and the current I.sub.L2 is at maximum (time point 140). During the shorted cycle 142, the constant current circulates through the inductor, instantaneously disrupting the inductive coupling to the primary side resulting in a voltage change V.sub.L1. During the shorted phase, there is no charge dissipation in the LC tank except through the parasitic resistances of the inductor and switch. As shown in FIGS. 1C and 1D, V.sub.LL and V.sub.RR resume oscillation at the same phase (time point 144), recovering to the peak resonance amplitudes within a few cycles 146. This technique does not disturb resonance, so it does not compromise the high Q of the coil for resonant power transfer, unlike most other data telemetry schemes. The full-cycle shorting can be phase shifted for the opposite polarity 148. FIG. 1D provides a sample measurement for data transmission including responses at the primary coil 122, which demonstrates a clear peak 150 in the voltage V.sub.L1 across the coil.

(11) FIG. 2A provides an schematic diagram of an exemplary embodiment of the inductive link at the 13.56-MHz ISM band 202 and the power/data telemetry IC 200 according to the invention. The inductors L.sub.1 and L.sub.2 were implemented using PCB-based planar coils with the following parameters: L.sub.1=6.7 H, diameter=7 cm and number of windings (N.sub.1)=16; L.sub.2=1.26 H, diameter=4.2 cm and N.sub.2=8. A low-power slow common-gate comparator 220 recovers a clock from the LC tank (L.sub.2C.sub.2). The clock 220 is fed to a phase-locked loop (PLL) 222, which generates signals for data transmission by transmitter 224. In the exemplary embodiment, PLL 222 is a 22 phase 2 PLL for multi-phase based rectification and regulation. The PLL's inputs may be masked when transmitting data.

(12) The circuit 200, which was fabricated into a 1.2 mm0.77 integrated circuit using a standard IBM 65 nm CMOS process, also includes data receivers 226 and 228 in each side. FIG. 2B is the micrograph of the actual fabricated IC. The total chip area is 0.92 mm.sup.2. The areas of the various blocks are: full wave rectifier 230: 0.04 mm.sup.2, PLL+Tx2 222: 0.029 mm.sup.2, Rx1 226: 0.006 mm.sup.2, and Rx2 228: 0.009 mm.sup.2. A schematic for PLL 222 with a 22-phase ring VCO and a divider-by-2 is provided in FIG. 2C. PLL 222 doubles the incoming clock from the low power clock recovery common-gate comparator. The PLL and phase selector 222 generate phase-tuned pulses P.sub.INL and P.sub.INR gating the pMOS switches of the full-wave rectifier 230 shown in FIG. 2D. The rectifier has nMOS cross-coupled pair and pMOS switches. During data transmission, the clocks to PFD are gated for more stable PLL operation. The dynamic body bias generator (inset in FIG. 2D) tracks the highest voltage among V.sub.LL, V.sub.RR and V.sub.DD. The nMOS across V.sub.LL and V.sub.RR act as the shorting switch (132 in FIGS. 1A and 1B) for data transmission.

(13) Rather than employing a high-speed scheme using an offset-controlled comparator, the inventive approach uses a slow lower-power clock recovery comparator and digital logic, and a multi-phase PLL for synchronizing and generating timing control signals for rectification and data transmission. Selecting a PLL feedback clock and controlling the phase delay of the VCO finely compensates the response delay of the comparator, aligning the 22 phases 302 over a half cycle, as depicted in FIG. 3A. One pulse 310 of the 22 phase pulses 302 is selected to close the pMOS switches, extracting charge from the LC tank, inducing a corresponding rectified V.sub.DD. FIG. 3B shows the rectified V.sub.DD and power over load current with this rectification technique. The maximum transferred power to the load is 6.3 mW. FIG. 3C shows measured waveforms of V.sub.LL, V.sub.DD (upper) and the rectification pulse P.sub.INL (lower), respectively.

(14) FIG. 4A illustrates the data receiver (decoder) (RX1) 228 that resides at the primary side shown in FIG. 2A. Data receiver 228, which includes a peak detection circuit 402 and a clocked comparator 404, aligns low peaks of V.sub.L1 in order to clarify distinct high peaks enhancing bit error rate (BER) as shown in FIG. 4B. Sample input data 408 at a rate of 6.78 Mbps is shown in FIG. 4B. Signal 410 illustrates a sample measurement for multiple data transmission without control of voltage V.sub.L1. As indicated, there are many near-miss and actual false positives 414 and false negatives 416 due to the fluctuation in the LC oscillation. It is important for these peaks to be reliably detected, so the inventive approach sets a threshold voltage by applying a DC bias voltage V.sub.PA to V.sub.L1 through a peak-aligning diode 406, shown in FIG. 4A. As indicated by the sample measurement signal 412, false detections are removed by aligning the waveform.

(15) Because the timing of a bit can be precisely detected, a cyclic on-off keying (COOK) time-encoded symbol bit mapping, shown in FIG. 5A, can be used to encode two bits within four cycles. On average, three shorts per 16 cycles are required to achieve 6.78 Mbps data transfer rate while simultaneously rectifying for 81.25% of the time. FIG. 5B provides a comparison of the inventive encoding approach against a simple data encoding scheme such as is used in the prior art (upper), where shorting occurs once for every two cycles encodes 1 bit, resulting in a bit rate of 3.39 Mpbs. Using the inventive timing-based encoding, or pulse-position encoding, as shown in the lower portion of FIG. 5B, shorting only once per four cycles (or 3 per 16 cycles in average), achieves 6.78 Mbps in 13.56 MHz carrier, while reserving more than 80% time for power delivery (i.e., LC oscillation and rectification.)

(16) FIG. 5C shows recorded waveforms with the symbol mapping for transmission at the secondary and reception at the primary. No error was detected over 1.695 million bits transmitted, upper-bounding the BER at 5.910.sup.7. The BER is estimated to be 210.sup.9 using the histogram shown in FIG. 5D. A clear voltage gap of about 200 mV is reflected.

(17) FIGS. 6A-6C illustrate rectification results obtained using the inventive modulation scheme. FIG. 6A shows the measured waveforms, where one pulse of the 22 phase pulse is used to close the pMOS switches to extract power from the LC tank. Digital logic coordinates data transmission and rectification. As indicated in FIG. 6B, V.sub.LL drops and remains near 0 during data transmission. FIG. 6C shows the rectified V.sub.DD and power with current. Power can be delivered up to 6.3 mW.

(18) Tables 1 and 2 below provide performance comparisons between the inventive modulation scheme (COOK) and various approaches reported in the literature.

(19) TABLE-US-00001 TABLE 1 Car- Modu- rier Data Energy lation Freq. Rate Carrier per bit Ref Link Scheme [MHz] [Mbps] cycle/bit BER [pJ/bit] [1] Sin- LSK 13.56 0.1 135.6 N/A N/A [2] gle LSK 13.56 0.5 27.1 N/A N/A [3] PPSK 13.56 0.85 16 N/A N/A [4] LSK 400 1 400 <1.7 10.sup.7 N/A This Sin- COOK 13.56 6.78 2 .sup.<6 10.sup.7 3.5 Work gle References: [1] W. Xu et al., IEEE TCAS II, 56(9), pp. 714-718, 2009 [2] H.-M. Lee et al., IEEE TCAS I, 58(8), pp. 1749-1760, 2011 [3] D. Cirmirakis et al., Proc. IEEE ESSCIRC, pp. 301-304, 2012 [4] R. Muller et al., ISSCC Digest Tech. Papers, pp. 412-413, 2014

(20) TABLE-US-00002 TABLE 2 Carrier Data Energy Modulation Freq. Rate Carrier per bit Ref Link Scheme [MHz] [Mbps] cycle/bit BER [pJ/bit] [1] Single LSK 13.56 0.1 135.6 N/A N/A [2] LSK 13.56 0.5 27.1 N/A N/A [3] PPSK 13.56 0.85 16 N/A N/A [4] LSK 400 1 400 <1.7 10.sup.7 N/A [5] Multiple LSK 25 2.8 8.9 <10.sup.6 35.7 [6] OQPSK 13.56 4.16 3.3 2 10.sup.6 N/A [7] BPSK 48 3 16 2 10.sup.4 1962 This Work Single COOK 13.56 6.78 2 <6 10.sup.7 3.5 [1] W. Xu et al., IEEE TCAS II, 56(9), pp. 714-718, 2009 [2] H.-M. Lee et al., IEEE TCAS I, 58(8), pp. 1749-1760, 2011 [3] D. Cirmirakis et al., Proc. IEEE ESSCIRC, pp. 301-304, 2012 [4] R. Muller et al., ISSCC Digest Tech. Papers, pp. 412-413, 2014 [5] S. Mandal et al., IEEE TBioCAS, 2(4), pp. 301-315, 2008 [6] G. Simard et al., IEEE TBioCAS, 4(3), pp. 192-200, 2010 [7] A. Rush and P. R. Troyk, IEEE TBME, 59(11), pp. 3255-3262, 2012

(21) The inventive modulation scheme described herein, Cyclic on-off keying (COOK), allows simultaneous transmission of power and broadband data, at a bit rate of half the carrier frequency, over the same resonant inductive link. Data-synchronous adiabatic switching in COOK retains almost all stored energy in the LC resonant tank during modulation of the carrier signal, and incurs minimum power losses during rectification. A 0.92 mm.sup.2 CMOS COOK prototype in 65 nm CMOS transmits 6.78 Mbps data at 3.5 pJ/bit and delivers up to 6 mW of power over a single 13.56-MHz inductive link.

(22) The inventive modulation scheme provides a significant improvement with respect to energy efficiency, as indicated by the summary provided in Table 3 below showing the power consumption for each block within the charge recycling power/data telemetry IC (e.g., as shown in FIGS. 2A and 2B).

(23) TABLE-US-00003 TABLE 3 Block Power Consumption [W] Clock-recovery comparator 0.33 PLL (2x, 22-phase, f.sub.vco = 27.12 MHz) 9.32 Voltage bias generator 0.45 TX clock generator 3.43 TX data controller 0.94 TX switch driver (fanout = 4, R.sub.SW = 0.14 ) 9.29 Total 23.76

(24) The present invention provides a significant advancement over the existing art, allowing transmission of broadband data at a bit rate of half the carrier frequency while efficiently transmitting power over the same resonant inductive link. Using novel synchronous cyclic on-off keying (COOK), the device retains almost all stored energy in the LC (inductor-capacitor) resonant tank during modulation of the carrier signal. Hence, it is able to achieve very high data rate with very low power.

(25) In addition, the invention uses a multi-phase phase-locked loop (PLL) to control timing in waveform sampling from the sinusoidal voltage signal in the LC tank to adiabatically convert and regulate power in generating multiple constant voltage supplies and/or time-varying stimulation voltage signals. This feature allows the device to perform precise supply and waveform control with minimum power loss, saving energy and avoiding heating of biomedical implants and other wireless sensors and actuators.

(26) The following references are incorporated herein by reference as disclosing the general state of the art in the field of the invention. [1] S. Ha et al., Proc. IEEE ESSCIRC, pp. 141-144, 2013; [2] Z. Tang et al., IEEE TBME, 42(5), pp. 524-528, 1995; [3] W. Xu et al., IEEE TCAS II, 56(9), pp. 714-718 2009; [4] H.-M. Lee et al., IEEE TCAS I, 58(8), pp. 1749-1760, 2011; [5] Mandal et al., IEEE TBioCAS, 2(4), pp. 301-315, 2008; [6] G. Simard et al., IEEE TBioCAS, 4(3), pp. 192-200, 2010; [7] D. Cirmirakis et al., Proc. IEEE ESSCIRC, pp. 301-304, 2012; [8] S. Ha et al., Proc. IEEE VLSI Symposium, to appear, 2014.