Methods and computer program products for compression of sequencing data

Abstract

A compression method includes: measuring a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction; applying a first compression process to the waveform, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction; and applying a second compression process to the waveform, the second compression process including a data substitution process that replaces at least a portion of the waveform with a plurality of coefficients representative of the portion of the waveform.

Claims

1. A compression method, comprising: measuring a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction; and applying a first compression process to the waveform using a processor, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction thereby forming a compressed data structure and storing the compressed data structure in a memory.

2. The method of claim 1, wherein the truncating of data comprises determining, for each of a plurality of sensors in the sensor array, a cut-off time point for the waveform for that sensor defining a data range to be truncated.

3. The method of claim 2, wherein each cut-off time point is determined by mining a plurality of past analysis runs for a given sensor array geometry.

4. The method of claim 2, wherein each cut-off time point is determined prior to every run or during a calibration procedure.

5. The method of claim 2, wherein each cut-off time point is factory pre-determined for a given sensor array geometry.

6. The method of claim 2, wherein the sensors are arranged in a plurality of regions in the sensor array, and wherein each cut-off time point for sensors in a given region is determined to have a common cut-off time point determined for sensors for that region.

7. The method of claim 6, wherein each common cut-off time point is determined by finding a best fit to a linear hinge model on a median trace for a region.

8. The method of claim 6, wherein each common cut-off time point is determined empirically and depends on a position of that region relative to other regions along a fluidic flow of nucleotides onto the sensor array.

9. The method of claim 8, wherein the cut-off time point of sensors in a region substantially near a fluidic inlet is different from the cut-off time point of sensors in a region substantially near a fluidic outlet.

10. The method of claim 1, further comprising: applying a second compression process to the waveform using the processor, the second compression process including a data substitution process that replaces at least a second portion of the waveform with a plurality of coefficients representative of the second portion of the waveform, wherein the second portion is related to nucleotide incorporations in the genetic sequencing reaction.

11. The method of claim 10, wherein the second compression process includes replacing the second portion of the waveform with a plurality of coefficients of a linear combination of one or more principal component vectors representative of the second portion of the waveform.

12. The method of claim 11, wherein the second compression process includes storing the plurality of coefficients compactly in the memory by dynamically truncating the coefficients to a lower precision and encoding the truncated coefficients using a Huffman code.

13. The method of claim 11, wherein the second compression process includes replacing the second portion of the waveform with a plurality of coefficients of a linear combination of between about 5 and about 10 principal component vectors representative of the second portion of the waveform.

14. The method of claim 11, wherein the second compression process includes replacing the second portion of the waveform with a plurality of coefficients of a linear combination of 5 or 6 principal component vectors representative of the second portion of the waveform.

15. The method of claim 1, wherein the measuring the waveform comprises measuring the waveform of a dynamic response of an ion-sensitive field effect transistor (ISFET) array to a change in ionic strength of an analyte solution in fluid contact with the ISFET array, wherein the measuring the waveform of the dynamic response of the ISFET array comprises associating a portion of the waveform to a stepwise increase in ion concentration in the analyte solution and associating another portion of the waveform to at least one portion of the dynamic response outside of the stepwise increase in ion concentration.

16. A computer program product comprising a non-transitory computer-usable medium having computer program logic recorded thereon that, when executed by one or more processors, samples and compresses data from a sensor array, the computer program logic comprising: first computer readable program code that enables a processor to measure a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction; and second computer readable program code that enables a processor to apply a first compression process to the waveform, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction thereby forming a compressed data structure and storing the compressed data structure in a memory.

17. The computer program product of claim 16, further comprising third computer readable program code that enables a processor to apply a second compression process to the waveform, the second compression process including replacing at least a second portion of the waveform with a plurality of coefficients representative of the second portion of the waveform, wherein the second portion of the waveform is related to nucleotide incorporations in the genetic sequencing reaction.

18. A method for compressing nucleic acid sequencing data, comprising: obtaining raw data from a semiconductor-based sequencing sensor array comprising a plurality of sensors during a data acquisition time period, the raw data comprising at least a non-informative portion corresponding to a subinterval of the data acquisition time period having a location within the data acquisition time period that varies for different sensors according to a position of the sensor in the sensor array; and transforming the raw data into compressed data using a lossy compression process including a data truncation process, the data truncation process being related for each sensor to the position of the sensor in the sensor array and configured to discard the non-informative portion of the raw data thereby forming a compressed data structure and storing the compressed data structure in a memory.

19. The method of claim 18, wherein the lossy compression process further comprises a data substitution process adapted to replace at least a portion of the raw data for each sensor with a plurality of coefficients of a linear combination of one or more principal component vectors representative of the portion of the raw data for each sensor.

20. The method of claim 19, wherein the data substitution process comprises storing the plurality of coefficients compactly in the memory by dynamically truncating the coefficients to a lower precision and encoding the truncated coefficients using a Huffman code.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead being placed upon generally illustrating the various concepts discussed herein.

(2) FIG. 1 illustrates a cross-section of a p-type (p-channel) ion-sensitive field effect transistor (ISFET) fabricated using a conventional CMOS process.

(3) FIG. 2 illustrates an electric circuit representation of the p-channel ISFET shown in FIG. 1.

(4) FIG. 2A illustrates an exemplary ISFET transient response to a step-change in ion concentration of an analyte.

(5) FIG. 3 illustrates one column of a two-dimensional ISFET array based on the ISFET shown in FIG. 1.

(6) FIG. 4 illustrates a transmission gate including a p-channel MOSFET and an n-channel MOSFET that is employed in each pixel of the array column shown in FIG. 3.

(7) FIG. 5 is a diagram similar to FIG. 1, illustrating a wider cross-section of a portion of a substrate corresponding to one pixel of the array column shown in FIG. 3, in which the ISFET is shown alongside two n-channel MOSFETs also included in the pixel.

(8) FIG. 6 is a diagram similar to FIG. 5, illustrating a cross-section of another portion of the substrate corresponding to one pixel of the array column shown in FIG. 3, in which the ISFET is shown alongside the p-channel MOSFET of the transmission gate shown in FIG. 4.

(9) FIG. 7 illustrates an example of a complete two-dimensional ISFET pixel array based on the column design of FIG. 3, together with accompanying row and column decoder circuitry and measurement readout circuitry.

(10) FIG. 8 generally illustrates a nucleic acid processing system comprising a large scale chemFET array, according to one inventive embodiment of the present disclosure.

(11) FIG. 9 illustrates one column of an chemFET array similar to that shown in FIG. 8, according to one inventive embodiment of the present disclosure.

(12) FIG. 9A illustrates a circuit diagram for an exemplary amplifier employed in the array column shown in FIG. 9.

(13) FIG. 9B is a graph of amplifier bias vs. bandwidth, according to one inventive embodiment of the present disclosure.

(14) FIG. 10 illustrates a top view of a chip layout design for a pixel of the column of an chemFET array shown in FIG. 9, according to one inventive embodiment of the present disclosure.

(15) FIG. 10-1 illustrates a top view of a chip layout design for a cluster of four neighboring pixels of an chemFET array shown in FIG. 9, according to another inventive embodiment of the present disclosure.

(16) FIG. 11A shows a composite cross-sectional view along the line I-I of the pixel shown in FIG. 10, including additional elements on the right half of FIG. 10 between the lines II-II and III-III, illustrating a layer-by-layer view of the pixel fabrication according to one inventive embodiment of the present disclosure.

(17) FIG. 11A-1 shows a composite cross-sectional view of multiple neighboring pixels, along the line I-I of one of the pixels shown in FIG. 10-1, including additional elements of the pixel between the lines II-II, illustrating a layer-by-layer view of pixel fabrication according to another inventive embodiment of the present disclosure.

(18) FIGS. 11B(1)-(3) provide the chemical structures of ten PPi receptors (compounds 1 through 10).

(19) FIG. 11 C(1) is a schematic of a synthesis protocol for compound 7 from FIG. 11 B(3).

(20) FIG. 11 C(2) is a schematic of a synthesis protocol for compound 8 from FIG. 11B(3).

(21) FIG. 11 C(3) is a schematic of a synthesis protocol for compound 9 from FIG. 11B(3).

(22) FIGS. 11D(1) and (2) are schematics illustrating a variety of chemistries that can be applied to the passivation layer in order to bind molecular recognition compounds (such as but not limited to PPi receptors).

(23) FIG. 11E is a schematic of attachment of compound 7 from FIG. 11B(3) to a metal oxide surface.

(24) FIGS. 12A through 12L provide top views of each of the fabrication layers shown in FIG. 11A, according to one inventive embodiment of the present disclosure.

(25) FIGS. 12-1A through 12-1L provide top views of each of the fabrication layers shown in FIG. 11A-1, according to another inventive embodiment of the present disclosure.

(26) FIG. 13 illustrates a block diagram of an exemplary CMOS IC chip implementation of an chemFET sensor array similar to that shown in FIG. 8, based on the column and pixel designs shown in FIGS. 9-12, according to one inventive embodiment of the present disclosure.

(27) FIG. 14 illustrates a row select shift register of the array shown in FIG. 13, according to one inventive embodiment of the present disclosure.

(28) FIG. 15 illustrates one of two column select shift registers of the array shown in FIG. 13, according to one inventive embodiment of the present disclosure.

(29) FIG. 16 illustrates one of two output drivers of the array shown in FIG. 13, according to one inventive embodiment of the present disclosure.

(30) FIG. 17 illustrates a block diagram of the chemFET sensor array of FIG. 13 coupled to an array controller, according to one inventive embodiment of the present disclosure.

(31) FIG. 18 illustrates an exemplary timing diagram for various signals provided by the array controller of FIG. 17, according to one inventive embodiment of the present disclosure.

(32) FIG. 18A illustrates another exemplary timing diagram for various signals provided by the array controller of FIG. 17, according to one inventive embodiment of the present disclosure.

(33) FIG. 18B shows a flow chart illustrating an exemplary method for processing and correction of array data acquired at high acquisition rates, according to one inventive embodiment of the present disclosure.

(34) FIGS. 18C and 18D illustrate exemplary pixel voltages showing pixel-to-pixel transitions in a given array output signal, according to one embodiment of the present disclosure.

(35) FIGS. 19-20 illustrate block diagrams of alternative CMOS IC chip implementations of chemFET sensor arrays, according to other inventive embodiments of the present disclosure.

(36) FIG. 20A illustrates a top view of a chip layout design for a pixel of the chemFET array shown in FIG. 20, according to another inventive embodiment of the present disclosure.

(37) FIGS. 21-23 illustrate block diagrams of additional alternative CMOS IC chip implementations of chemFET sensor arrays, according to other inventive embodiments of the present disclosure.

(38) FIG. 24 illustrates the pixel design of FIG. 9 implemented with an n-channel chemFET and accompanying n-channel MOSFETs, according to another inventive embodiment of the present disclosure.

(39) FIGS. 25-27 illustrate alternative pixel designs and associated column circuitry for chemFET arrays according to other inventive embodiments of the present disclosure.

(40) FIGS. 28A and 28B are isometric illustrations of portions of microwell arrays as employed herein, showing round wells and rectangular wells, to assist three-dimensional visualization of the array structures.

(41) FIG. 29 is a diagrammatic depiction of a top view of one corner (i.e., the lower left corner) of the layout of a chip showing an array of individual ISFET sensors on a CMOS die.

(42) FIG. 30 is an illustration of an example of a layout for a portion of a (typically chromium) mask for a one-sensor-per-well embodiment of the above-described sensor array, corresponding to the portion of the die shown in FIG. 29.

(43) FIG. 31 is a corresponding layout for a mask for a 4-sensors-per-well embodiment.

(44) FIG. 32 is an illustration of a second mask used to mask an area which surrounds the array, to build a collar or wall (or basin, using that term in the geological sense) of resist which surrounds the active array of sensors on a substrate, as shown in FIG. 33A.

(45) FIG. 33 is an illustration of the resulting basin.

(46) FIG. 33A is an illustration of a three-layer PCM process for making the microwell array.

(47) FIG. 33B is a diagrammatic cross-section of a microwell with a bump feature etched into the bottom.

(48) FIG. 33B-1 is an image from a scanning electron microscope showing in cross-section a portion of an array architecture as taught herein, with microwells formed in a layer of silicon dioxide over ISFETs.

(49) FIG. 33B-2 is a diagrammatic illustration of a microwell in cross-section, the microwell being produced as taught herein and having sloped sides, and showing how a bead of a correspondingly appropriate diameter larger than that of the well bottom can be spaced from the well bottom by interference with the well sidewalls.

(50) FIG. 33B-3 is another diagrammatic illustration of such a microwell with beads of different diameters shown, and indicating optional use of packing beads below the nucleic acid-carrying bead such as a DNA-carrying bead.

(51) FIGS. 34-37 diagrammatically illustrate a first example of a suitable experiment apparatus incorporating a fluidic interface with the sensor array, with FIG. 35 providing a cross-section through the FIG. 34 apparatus along section line 35-35 and FIG. 36 expanding part of FIG. 35, in perspective, and FIG. 37 further expanding a portion of the structure to make the fluid flow more visible.

(52) FIG. 38 is a diagrammatic illustration of a substrate with an etched photoresist layer beginning the formation of an example flow cell of a certain configuration.

(53) FIGS. 39-41 are diagrams of masks suitable for producing a first configuration of flow cell consistent with FIG. 38.

(54) FIGS. 42-54 (but not including FIGS. 42A-42L) and 57-58 are pairs of partly isometric, sectional views of example apparatus and enlargements, showing ways of introducing a reference electrode into, and forming, a flow cell and flow chamber, using materials such as plastic and PDMS.

(55) FIG. 42A is an illustration of a possible cross-sectional configuration of a non-rectangular flow chamber antechamber (diffuser section) for use to promote laminar flow into a flow cell as used in the arrangements shown herein.

(56) FIGS. 42B-42F are diagrammatic illustrations of examples of flow cell structures for unifying fluid flow.

(57) FIG. 42F1 is a diagrammatic illustration of an example of a ceiling baffle arrangement for a flow cell in which fluid is introduced at one corner of the chip and exits at a diagonal corner, the baffle arrangement facilitating a desired fluid flow across the array.

(58) FIGS. 42F2-42F8 comprise a set of illustrations of an exemplary flow cell member that may be manufactured by injection molding and may incorporate baffles to facilitate fluid flow, as well as a metalized surface for serving as a reference electrode, including an illustration of said member mounted to a sensor array package over a sensor array, to form a flow chamber thereover.

(59) FIGS. 42G and 42H are diagrammatic illustrations of alternative embodiments of flow cells in which fluid flow is introduced to the middle of the chip assembly.

(60) FIGS. 42I and 42J are cross-sectional illustrations of the type of flow cell embodiments shown in FIGS. 42G and 42H, mounted on a chip assembly.

(61) FIGS. 42K and 42L are diagrammatic illustrations of flow cells in which the fluid is introduced at a corner of the chip assembly.

(62) FIG. 42M is a diagrammatic illustration of fluid flow from one corner of an array on a chip assembly to an opposite corner, in apparatus such as that depicted in FIGS. 42K and 42L.

(63) FIGS. 55 and 56 are schematic, cross-sectional views of two-layer glass (or plastic) arrangements for manufacturing fluidic apparatus for mounting onto a chip for use as taught herein.

(64) FIGS. 57 and 58 are schematic embodiments of a fluidic assembly.

(65) FIGS. 59A-59C are illustrations of the pieces for two examples of two-piece injection molded parts for forming a flow cell.

(66) FIG. 60 is a schematic illustration, in cross-section, for introducing a stainless steel capillary tube as an electrode, into a downstream port of a flow cell such as the flow cells of FIGS. 59A-59C, or other flow cells.

(67) FIG. 61A is a schematic illustrating the incorporation of a dNTP into a synthesized nucleic acid strand with concomitant release of inorganic pyrophosphate (PPi).

(68) FIG. 61B is a schematic illustrating an embodiment of the invention in which the single stranded region of the template is not hybridized to RNA oligomers. Hydrogen ion that is released as a result of nucleotide incorporation is able to interact with and possibly be sequestered by free bases on the single stranded region of the template. Such hydrogen ions are then unable to flow to the ISFET surface and be detected. The free bases in the single stranded regions are proton acceptors at pH below 7.5.

(69) FIG. 61 C is a schematic illustrating an embodiment of the invention in which the single stranded region of the template is hybridized to RNA oligomers. Hydrogen ion that is released as a result of nucleotide incorporation is not able to interact with the template which is hybridized to the RNA oligomers. These hydrogen ions are therefore able to flow to the ISFET surface and be detected.

(70) FIG. 61D is the structure of the potassium salt of PNSE.

(71) FIG. 61E is the structure of the sodium salt of poly(styrene sulfonic acid).

(72) FIG. 61F is the structure of the chloride salt of poly(diallydimethylammonium).

(73) FIG. 61G is the structure of the chloride salt of tetramethyl ammonium.

(74) FIG. 61H is a schematic showing the chemistry for covalently conjugating a primer to a bead.

(75) FIG. 61I is a table showing the possible reactive groups that can be used in combination at positions B1, B2, P1 and P2 in order to covalently conjugate a primer to a bead.

(76) FIGS. 61J and K are data capture images of microwell arrays following bead deposition. The white spots are beads. FIG. 61J is an optical microscope image and FIG. 61K is an image captured using the chemFET sensor underlying the microwell array.

(77) FIGS. 62-70 illustrate bead loading into the microfluidic arrays of the invention.

(78) FIG. 71 illustrates an exemplary sequencing process.

(79) FIGS. 72A-D are graphs showing on-chip detection of nucleotide incorporation using a template of known sequence.

(80) FIGS. 73A and B are graphs showing a trace from an ISFET device (A) and a nucleotide readout (B) from a sequencing reaction of a 23-mer synthetic oligonucleotide.

(81) FIGS. 74A and B are graphs showing a trace from an ISFET device (A) and a nucleotide readout (B) from a sequencing reaction of a 25-mer PCR product.

(82) FIG. 75A is a modeling circuit diagram for use in analyzing the factors influencing ISFET gate gain.

(83) FIG. 75B is a graph of simulated ISFET gate gain dependence on passivation layer thickness for a first set of parameters set forth in the specification.

(84) FIG. 75C is a graph of simulated ISFET gate gain dependence on passivation layer thickness for a second set of parameters set forth in the specification.

(85) FIG. 75D is a graph of simulated ISFET gate gain dependence on passivation layer thickness for a third set of parameters set forth in the specification.

(86) FIG. 75E is a diagrammatic illustration of two microwells formed over ISFETs having extended floating gate electrodes lining the walls of the microwells.

(87) FIG. 75F is a partially-circuit, partially diagrammatic illustration of an example embodiment of a four-transistor pixel (sensor) employing an active circuit design.

(88) FIG. 75G is a diagram of a second example of a four-transistor active pixel, employing a single-MOSFET current source to avoid (or at least minimize) introducing a disturbance at the sense node.

(89) FIG. 75H is a diagram of a group of four pixels, each similar to that of FIG. 75G, sharing certain components to reduce chip area requirements.

(90) FIG. 75I is a diagram of an active pixel employing six transistors. FIG. 75J is a diagram of a group of four pixels, each similar to that of FIG. 75I, sharing certain components to reduce chip area requirements.

(91) FIG. 75K is a diagrammatic illustration of an example of an array of ISFET sensors (pixels) as taught herein, sharing a common analog-to-digital converter (ADC) for producing digital pixel values.

(92) FIG. 75L is a diagrammatic illustration of another example of an ISFET array in which one ADC is provided per column (or group of columns) to speed up digital readout.

(93) FIGS. 75M and 75N are illustrations showing how the arrays of FIGS. 75K and 75L may be segmented to form sub-arrays, for example to speed operation or to treat differently different portions of the overall array.

(94) FIG. 75O is a partially schematic circuit, partially block diagram of a single pixel, illustrating basically how digital output may be generated at the individual pixel level in an array.

(95) FIG. 75P is a diagram of a group of four pixels, each similar to that of FIG. 75P, sharing an ADC and memory to provide per-pixel digital output.

(96) FIG. 75Q is a diagram of row addressing circuitry and column sense amplifiers providing readout functionality from a pixel array in which the pixels provide digital outputs.

(97) FIGS. 75R-75T are schematic circuit diagrams illustrating alternatives for diode-protecting ISFETs as discussed herein.

(98) FIG. 76A is a diagrammatic illustration of a cross-section of a first example of a fluid-fluid reference electrode interface in which the reference electrode is introduced downstream in the reagent path from the flow cell.

(99) FIGS. 76B and 76C are diagrammatic illustrations of two alternative examples of ways to construct apparatus to achieve the fluid-fluid interface of FIG. 76A.

(100) FIG. 76D is a diagrammatic illustration of a cross-section of a second example of a fluid-fluid reference electrode interface in which the reference electrode is introduced upstream in the reagent path from the flow cell.

(101) FIG. 77A is a high-level, partially block, partially circuit diagram showing a basic passive sensor pixel in which the voltage changes on the ISFET source and drain inject noise into the analyte, causing errors in the sensed values.

(102) FIG. 77B is a high-level partially block, partially circuit diagram showing a basic passive sensor pixel in which the voltage changes on the ISFET drain are eliminated by tying it to ground, the pixel output is obtained via a column buffer, and CDS is employed on the output of the column buffer to reduce correlated noise.

(103) FIG. 77C is a high-level partially block, partially circuit diagram showing a two-transistor passive sensor pixel in which the voltage changes on the ISFET drain and source are substantially eliminated, the pixel output is obtained via a buffer, and CDS is employed on the output of the column buffer to reduce correlated noise.

(104) FIG. 78A is an isometric, see-through, diagrammatic illustration of one example of a flow multiplexer for supplying fluids to a flow cell as shown herein.

(105) FIG. 78B is a top view of the apparatus of FIG. 78A.

(106) FIG. 78C is a diagrammatic illustration of flow through the multiplexer member of FIGS. 78A and 78B during reagent delivery mode.

(107) FIG. 78D is a diagrammatic illustration of flow through the multiplexer member of FIGS. 78A and 78B during ship washing and reagent priming modes.

(108) FIG. 78E is another diagrammatic illustration of wash solution flow through the multiplexer member.

(109) FIG. 79 is a diagrammatic illustration of flows in the apparatus of FIGS. 78A-78E.

(110) FIGS. 80A and 80B are, respectively, top and side views of an alternative, two-dimensional fluid multiplexer

(111) FIG. 81 is an illustration of an embodiment of a method for sampling a sensor array.

(112) FIG. 82 is an illustration of an example waveform of a stepwise change in the concentration of one or more ionic species in an analyte solution in fluid contact with an ISFET array.

(113) FIG. 83 is an illustration of an example computer system in which embodiments of the present invention can be implemented.

(114) FIG. 84 illustrates a compression method according to an exemplary embodiment.

(115) FIGS. 85(a)-85(c) illustrate a variable frame averaging compression process according to various exemplary embodiments.

(116) FIGS. 86(a)-86(d) illustrate a keyframe delta compression process according to various exemplary embodiments.

(117) FIGS. 87(a)-87(b) illustrate a t.sub.0 compression process according to an exemplary embodiment.

(118) FIG. 88 illustrates exemplary waveform and data acquisition windows defining a data flow according to an exemplary embodiment.

(119) FIG. 89 illustrates signal curves from a period prior to a nucleotide flow to a period after a subsequent wash flow for four exemplary regions in an exemplary ion detection chip (Ion 314 Chip).

(120) FIG. 90 illustrates signal curves from a period prior to a nucleotide flow to a period after a subsequent wash flow for four exemplary regions in an exemplary substantially larger ion detection chip (Ion Proton chip).

(121) FIG. 91 illustrates an exemplary compression method according to an embodiment.

(122) FIG. 92 illustrates three exemplary waveforms with or without compression using a substitution process according to an exemplary embodiment.

(123) FIG. 93 illustrates a relationship between sigma and a rate of proton concentration change after time zero.

(124) FIG. 94 illustrates a relationship between tmid_nuc and time zero.

(125) FIG. 95 illustrates exemplary time zero points and rates of pH changes after time zero based on raw data for wells in different regions on a chip.

(126) FIG. 96 illustrates relative weights of eigenvalues corresponding to the eigenvectors of the covariance matrix for wells in a 100 by 100 spatially contiguous region of a chip.

(127) FIG. 97 illustrates residuals per frame using a linear combination of the first 5 eigenvectors to represent wells in a 100 by 100 spatially contiguous region of a chip.

(128) FIGS. 98(a)-98(f) illustrate an exemplary linear combination of eigenvectors.

(129) FIG. 99 illustrates an exemplary method for compression of sequencing data.

DETAILED DESCRIPTION

(130) Following below are more detailed descriptions of various concepts related to, and embodiments of, inventive methods and apparatus relating to large scale chemFET arrays for analyte detection and/or measurement. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in any of numerous ways, as the disclosed concepts are not limited to any particular manner of implementation. Examples of specific implementations and applications are provided primarily for illustrative purposes.

(131) Various inventive embodiments according to the present disclosure are directed at least in part to a semiconductor-based/microfluidic hybrid system that combines the power of microelectronics with the biocompatibility of a microfluidic system. In some examples below, the microelectronics portion of the hybrid system is implemented in CMOS technology for purposes of illustration. It should be appreciated, however, that the disclosure is not intended to be limiting in this respect, as other semiconductor-based technologies may be utilized to implement various aspects of the microelectronics portion of the systems discussed herein.

(132) One embodiment disclosed herein is directed to a large sensor array (e.g., a two-dimensional array) of chemically-sensitive field effect transistors (chemFETs). In related embodiments, the individual chemFET sensor elements or pixels of the array are configured to detect analyte presence (or absence), analyte levels (or amounts), and/or analyte concentration in a sample such as an unmanipulated sample, or as a result of chemical and/or biological processes (e.g., chemical reactions, cell cultures, neural activity, nucleic acid sequencing reactions, etc.) occurring in proximity to the array. Examples of chemFETs contemplated by various embodiments discussed in greater detail below include, but are not limited to, ion-sensitive field effect transistors (ISFETs) and enzyme-sensitive field effect transistors (EnFETs). In one exemplary implementation, one or more microfluidic structures is/are fabricated above the chemFET sensor array to provide for containment and/or confinement of a biological or chemical reaction in which an analyte of interest may be captured, produced, or consumed, as the case may be. For example, in one implementation, the microfluidic structure(s) may be configured as one or more wells (or microwells, or reaction chambers, or reaction wells as the terms are used interchangeably herein) disposed above one or more sensors of the array, such that the one or more sensors over which a given well is disposed detect and measure analyte presence, level, and/or concentration in the given well. Preferably, there is a 1:1 correspondence of chemFET sensors and reaction wells.

(133) In another exemplary implementation, the invention encompasses a system comprising at least one two-dimensional array of reaction chambers, wherein each reaction chamber is coupled to a chemically-sensitive field effect transistor (chemFET) and each reaction chamber is no greater than 10 m.sup.3 (i.e., 1 pL) in volume. Preferably, each reaction chamber is no greater than 0.34 pL, and more preferably no greater than 0.096 pL or even 0.012 pL in volume. A reaction chamber can optionally be 2.sup.2, 3.sup.2, 4.sup.2, 5.sup.2, 6.sup.2, 7.sup.2, 8.sup.2, 9.sup.2 or 10.sup.2 square microns in cross-sectional area at the top. Preferably, the array has at least 10.sup.2, 10.sup.3, 10.sup.4, 10.sup.5, 10.sup.6, 10.sup.7, 10.sup.8, 10.sup.9, or more reaction chambers. The reaction chambers may be capacitively coupled to the chemFETs, and preferably are capacitively coupled to the chemFETs. Such systems may be used for high-throughput sequencing of nucleic acids.

(134) As used herein, an array is a planar arrangement of elements such as sensors or wells. The array may be one or two dimensional. A one dimensional array is an array having one column (or row) of elements in the first dimension and a plurality of columns (or rows) in the second dimension. An example of a one dimensional array is a 15 array. A two dimensional array is an array having a plurality of columns (or rows) in both the first and the second dimensions. The number of columns (or rows) in the first and second dimensions may or may not be the same. An example of a two dimensional array is a 510 array.

(135) In some embodiments, such a chemFET array/microfluidics hybrid structure may be used to analyze solution(s)/material(s) of interest containing nucleic acids. For example, such structures may be employed to sequence nucleic acids. Sequencing of nucleic acids may be performed to determine partial or complete nucleotide sequence of a nucleic acid, to detect the presence and in some instances nature of a mutation such as but not limited to a single nucleotide polymorphism in a nucleic acid, to identify source of a cell(s) or nucleic acid for example for forensic purposes, to detect abnormal cells such as cancer cells in the body optionally in the absence of detectable tumor masses, to identify pathogens in a sample such as a bodily sample for example for diagnostic and/or therapeutic purposes, to identify antibiotic resistant strains of pathogens in order to avoid unnecessary (and ineffective) therapeutic regimens, to determine what therapeutic regimen will be most effective to treat a subject having a particular condition as can be determined by the subject's genetic make-up (e.g., personalized medicine), to determine and compare nucleic acid expression profiles of two or more states (e.g., comparing expression profiles of diseased and normal tissue, or comparing expression profiles of untreated tissue and tissue treated with drug, enzymes, radiation or chemical treatment), to haplotype a sample (e.g., comparing genes or variations in genes on each of the two alleles present in a human subject), to karyotype a sample (e.g., analyzing chromosomal make-up of a cell or a tissue such as an embryo, to detect gross chromosomal or other genomic abnormalities), and to genotype (e.g., analyzing one or more genetic loci to determine for example carrier status and/or species-genus relationships).

(136) The systems described herein can be utilized to sequence the nucleic acids of an entire genome, or any portion thereof. Genomes that can be sequenced include mammalian genomes, and preferably human genomes. Other genomes that can be sequenced include bacterial, viral, fungal and parasitic genomes. Such sequencing may lead to the identification of mutations that give rise to drug resistance, or general evolutionary drift from known species. This latter aspect is useful in determining for example whether a prior therapeutic (such as a vaccine) may be effective against current infecting strains. A specific example is the detection of new influenza strains and a determination of whether a prior year's vaccine cocktail will be effective against a new flu outbreak.

(137) Thus the methods of the invention may be embraced by methods for detecting a nucleic acid in a sample. The nucleic acid may be a marker of its source such as a pathogen including but not limited to a virus, or a cancer or tumor in an individual. In the latter aspect, a sample such as a blood sample may be harvested from a subject and screened for the presence of an occult cancer cell such as one that has extravasated from its original tumor site. In yet another aspect, the methods may be used for forensic purposes in which samples are screened for the presence of a known nucleic acid (e.g., from a suspect or from a law enforcement DNA bank). In related aspects, a sample may be analyzed for nucleic acid heterogeneity in order to determine whether a sample is derived from one source (e.g., a single subject) or more than one source (e.g., a contaminated sample). The methods described herein may also be used to detect the presence of a nucleotide mutation such as but not limited to a single nucleotide polymorphism. Such mutation analysis or screening is typically performed in prenatal or postnatal diagnostics. The nature of the mutation can then be used to determine the most suitable course of therapy, in some instances. Thus the invention intends that any of the methods provided herein can be used in one or more diagnostic, forensic and/or therapeutic methods.

(138) Various aspects of the invention employ a sequencing-by-synthesis approach for sequencing nucleic acids. This approach involves the synthesis of a new nucleic acid strand using a template nucleic acid. The template strand may be primed intermolecularly by hybridizing a sequencing primer to it at one end, or intramolecularly by folding over on itself at one end. The template strand may also be primed by introducing a break or a nick in one strand of a double-stranded nucleic acid, preferably but not exclusively near an end, as described in greater detail herein. In these embodiments, known nucleotides are incorporated into the primer based on complementarity with the template. The method requires that nucleotides be contacted with the primer (and thus template) (in the presence of polymerase and any other factors required for incorporation) in a selective manner.

(139) In many embodiments, each nucleotide type is individually contacted with the primer and/or template. In other embodiments, combinations of two or three types of nucleotides may be contacted with the primer and/or template simultaneously. Since the identity of the nucleotides in contact with the primer and/or template at any given time is known, the identity of the incorporated nucleotides (if incorporated) is also known. And based on the necessary complementarity with the template, the sequence of the template can also be deduced. Using different types of nucleotides separately (e.g., using dATP, dCTP, dGTP or dTTP separately from each other), a high resolution sequence can be obtained. Using combinations (or mixtures) of nucleotides (e.g., using dATP, dCTP and dGTP together and separately from dTTP), a lower resolution sequence can be obtained that is nevertheless valuable for certain applications (e.g., ordering and aligning various higher resolution sequences). With regards to the latter embodiment, it will be understood that the invention contemplates using mixtures of any three nucleotides, and in some cases any two nucleotides, and not just the specific combinations recited above.

(140) The nucleotides (or nucleotide triphosphates or deoxyribonucleotides or dNTPs, as they are referred to herein interchangeably) need not be and typically are not extrinsically labeled. Thus, naturally occurring nucleotides (i.e., nucleotides identical to those that exist in vivo naturally) or their synthetic counterparts are suitable for use in the methods of the invention. Such nucleotides may be referred to herein as being unlabeled.

(141) Preferably, the nucleotides are delivered at substantially the same time to each template. Polymerase(s) are preferably already present, although they also may be introduced along with the nucleotides. The polymerases may be immobilized or may be free flowing. Once the nucleotides are incorporated (if complementarity exists) and any associated signal is detected, an enzyme, such as apyrase, is typically delivered to degrade any unused nucleotides, followed by a washing step to remove substantially all of the enzyme as well as any other remaining and undesirable components. The reaction may occur in a reaction chamber in some embodiments, while in others it may occur in the absence of reaction chambers. In these latter embodiments, the sensor surface may be continuous without any physical divider between sensors.

(142) In important embodiments, the sequencing reaction is performed simultaneously on a plurality of identical templates in a reaction chamber, and optionally in a plurality of reaction chambers. Sequencing a different template in each reaction chamber allows a greater amount of sequence data to be obtained in any given run. Thus, using as many reaction chambers (and sensors) as possible in a given run also maximizes the amount of sequence data that can be obtained in any given run. In important embodiments, the templates in a reaction well are immobilized (e.g., covalently or non-covalently) onto and/or in a bead, referred to herein as a capture bead, or onto a solid support such as the chemFET surface.

(143) It is to be understood that in this and other embodiments and aspects of the invention, a plurality may represent a subset of elements rather than the entirety of all elements. As an example, in the above embodiment, the plurality of templates in the reaction chamber that are sequenced may represent a subset or all of the templates in the reaction chamber. Thus this particular embodiment requires that at least two templates be sequenced, and it does not require that all the templates present in the reaction chamber be sequenced.

(144) As described extensively herein, in some embodiments, nucleotide incorporation is detected through byproducts of the incorporation or by changes in charge to the newly synthesized nucleic acid, especially where it is immobilized on a chemFET surface, rather than by detecting the incorporated nucleotide itself. More specifically, some embodiments exploit the release of inorganic pyrophosphate (PPi), inorganic phosphate (Pi), and hydrogen ions (all of which are considered sequencing reaction byproducts) that occurs following incorporation of a nucleotide into a nucleic acid (such as a primer, for example). In some embodiments of the invention, the method detects the released hydrogen ions as an indication of nucleotide incorporation. The chemFETs (and chemFET arrays) described herein are suited to the detection of these ions as well as other sequencing reaction byproducts. It is to be understood that the aspects and embodiments described herein related to chemFETs equally contemplate and embrace ISFETs unless otherwise stated.

(145) The invention includes methods for improving detection of the hydrogen ions by the chemFET. These methods include generating and/or detecting more hydrogen ions in a given sequencing reaction. This can be done by increasing the number of templates per reaction chamber, increasing the number of templates attached to each capture bead, increasing the number of templates being sequenced per reaction chamber, increasing the number of templates bound to the sensor surface, increasing the stability of the primer/template hybrid, increasing the processivity of the polymerase, and/or combining nucleotide incorporation with nucleotide excision (e.g., performing the sequencing-by-synthesis reaction in the context of a nick translation reaction), among other things. Another alternative or additional approach is to increase the number of released hydrogen ions that are actually detected by the chemFET. This can be done by preventing the released hydrogen ions from interacting with other components in the reaction well including any components with buffering potential. These embodiments include using buffering inhibitors (as described more fully herein) to saturate components that might otherwise sequester released hydrogen ions. Buffering inhibitors may be short RNA oligomers that bind to single stranded regions of the templates, or chemical compounds that interact with the materials comprised in the reaction chambers and/or chemFETs themselves.

(146) Some aspects and embodiments presented herein involve dense chemFET arrays and reaction chamber arrays. It will be apparent that as arrays become more dense, area and/or volume of individual elements (e.g., sensor surfaces and reaction chambers) will typically become smaller in order to accommodate a greater number of sensors or reaction chambers without a concomitant (or significant) increase in total array area. However, it has been determined in accordance with an aspect of the invention that as volume of a reaction chamber decreases, the signal to noise ratio can actually increase due to an increased nucleic acid concentration. For example, it has been determined that a roughly 2.3 fold decrease in reaction chamber volume can yield about a 1.5 fold increase in signal to noise ratio. This increase can occur even if the total number of nucleic acids being sequenced is reduced. Thus, in some instances rather than losing signal by moving to more dense arrays, the invention contemplates a greater signal due to an increased concentration of nucleic acids in the smaller volume reaction chambers.

(147) The invention also contemplates sequencing-by-synthesis methods that detect nucleotide incorporation events based on changes in charge at the chemFET surface due to the a change in charge of a moiety attached to the surface, such as a nucleic acid or a nucleic acid complex (e.g., a template/primer hybrid). Such methods include those that use or extend nucleic acids that are immobilized (e.g., covalently) to the surface of a chemFET. Nucleotide incorporation into a nucleic acid that is bound to a chemFET surface typically results in an increase in the negative charge of the bound nucleic acid or the complex in which it is present (e.g., a template/primer hybrid). In some instances, the primer will be bound to the chemFET surface while in other instances the template will be bound to the chemFET surface. In such instances, a plurality of identical, typically physically separate, nucleic acids are immobilized to individual chemFET surfaces and sequencing-by-synthesis reactions are performed on the plurality simultaneously and synchronously. In some embodiments, the nucleic acids are not concatemers and rather each will include only a single copy of the nucleic acid to be sequenced.

(148) It will be understood that the sequencing methods provided herein can be used to sequence a genome or part thereof. As an example, such a method may include delivering fragmented nucleic acids from the genome or part thereof to a system for high-throughput sequencing comprising at least one array of reaction chambers, wherein each reaction chamber is coupled to a chemFET, and detecting a sequencing reaction in a reaction chamber via a signal from the chemFET coupled with the reaction chamber. Alternatively, the method may include delivering fragmented nucleic acids from the genome or part thereof to a sequencing apparatus comprising an array of reaction chambers, wherein each of the reaction chambers is disposed in a sensing relationship with an individual associated chemFET, and detecting a sequencing reaction a reaction chambers via a signal from its associated chemFET. Typically, all four nucleotides are flowed into the same reaction chamber, either individually (or separately) or as some mixture of less than all four nucleotides, in an ordered and known manner.

(149) The methods provided herein may allow for at least 10.sup.3, preferably at least 10.sup.4, more preferably at least 10.sup.5, and even more preferably at least 10.sup.6 bases to be determined (or sequenced) per hour. In even more preferred embodiments, at least 10.sup.7 bases, at least 10.sup.8 bases, at least 10.sup.9 bases, or at least 10.sup.10 bases are sequenced per hour using the methods and arrays discussed herein. Thus, the methods may be used to sequence an entire human genome within about 24 hours, more preferably within about 20 hours, even more preferably within about 15 hours, even more preferably within about 10 hours, even more preferably within about 5 hours, and most preferably within about 1 hour.

(150) It should be appreciated, however, that while some illustrative examples of the concepts disclosed herein focus on nucleic acid sequencing, the invention contemplates a broader application of these methods and is not intended to be limited to these examples.

(151) FIG. 8 generally illustrates a nucleic acid processing system 1000 comprising a large scale chemFET array, according to one inventive embodiment of the present disclosure. An example of a nucleic acid processing system is a nucleic acid sequencing system. In the discussion that follows, the chemFET sensors of the array are described for purposes of illustration as ISFETs configured for sensitivity to static and/or dynamic ion concentration, including but not limited to hydrogen ion concentration. However, it should be appreciated that the present disclosure is not limited in this respect, and that in any of the embodiments discussed herein in which ISFETs are employed as an illustrative example, other types of chemFETs may be similarly employed in alternative embodiments, as discussed in further detail below. Similarly, it should be appreciated that various aspects and embodiments of the invention may employ ISFETs as sensors yet detect one or more ionic species that are not hydrogen ions.

(152) The system 1000 includes a semiconductor/microfluidics hybrid structure 300 comprising an ISFET sensor array 100 and a microfluidics flow cell 200. In one aspect, the flow cell 200 may comprise a number of wells (not shown in FIG. 8) disposed above corresponding sensors of the ISFET array 100. In another aspect, the flow cell 200 is configured to facilitate the sequencing of one or more identical template nucleic acids disposed in the flow cell via the controlled and ordered introduction to the flow cell of a number of sequencing reagents 272 (e.g., dATP, dCTP, dGTP, dTTP (generically referred to herein as dNTP), divalent cations such as but not limited to Mg.sup.2+, wash solutions, and the like.

(153) As illustrated in FIG. 8, the introduction of the sequencing reagents to the flow cell 200 may be accomplished via one or more valves 270 and one or more pumps 274 that are controlled by a computer 260. A number of techniques may be used to admit (i.e., introduce) the various processing materials (i.e., solutions, samples, reaction reagents, wash solutions, and the like) into the wells of such a flow cell. As illustrated in FIG. 8, reagents including dNTP may be admitted to the flow cell (e.g., via the computer controlled valve 270 and pumps 274) from which they diffuse into the wells, or reagents may be added to the flow cell by other means such as an ink jet. In yet another example, the flow cell 200 may not contain any wells, and diffusion properties of the reagents may be exploited to limit cross-talk between respective sensors of the ISFET array 100, or nucleic acids may be immobilized on the surfaces of sensors of the ISFET array 100.

(154) The flow cell 200 in the system of FIG. 8 may be configured in a variety of manners to provide one or more analytes (or one or more reaction solutions) in proximity to the ISFET array 100. For example, a template nucleic acid may be directly attached or applied in suitable proximity to one or more pixels of the sensor array 100, or in or on a support material (e.g., one or more beads) located above the sensor array but within the reaction chambers, or on the sensor surface itself. Processing reagents (e.g., enzymes such as polymerases) can also be placed on the sensors directly, or on one or more solid supports (e.g., they may be bound to the capture beads or to other beads) in proximity to the sensors, or they may be in solution and free-flowing. It is to be understood that the device may be used without wells or beads.

(155) In the system 1000 of FIG. 8, according to one embodiment the ISFET sensor array 100 monitors ionic species, and in particular, changes in the levels/amounts and/or concentration of ionic species, including hydrogen ions. In important embodiments, the species are those that result from a nucleic acid synthesis or sequencing reaction.

(156) Various embodiments of the present invention may relate to monitoring/measurement techniques that involve the static and/or dynamic responses of an ISFET. It is to be understood that although the particular example of a nucleic acid synthesis or sequencing reaction is provided to illustrate the transient or dynamic response of chemFET such as an ISFET, the transient or dynamic response of a chemFET such as an ISFET as discussed below may be exploited for monitoring/sensing other types of chemical and/or biological activity beyond the specific example of a nucleic acid synthesis or sequencing reaction.

(157) As noted above, the ISFET may be employed to measure steady state pH values, since in some embodiments pH change is proportional to the number of nucleotides incorporated into the newly synthesized nucleic acid strand. In other embodiments discussed in greater detail below, the FET sensor array may be particularly configured for sensitivity to other analytes that may provide relevant information about the chemical reactions of interest. An example of such a modification or configuration is the use of analyte-specific receptors to bind the analytes of interest, as discussed in greater detail herein.

(158) Via an array controller 250 (also under operation of the computer 260), the ISFET array may be controlled so as to acquire data (e.g., output signals of respective ISFETs of the array) relating to analyte detection and/or measurements, and collected data may be processed by the computer 260 to yield meaningful information associated with the processing (including sequencing) of the template nucleic acid.

(159) With respect to the ISFET array 100 of the system 1000 shown in FIG. 8, in one embodiment the array 100 is implemented as an integrated circuit designed and fabricated using standard CMOS processes (e.g., 0.35 micrometer process, 0.18 micrometer process), comprising all the sensors and electronics needed to monitor/measure one or more analytes and/or reactions. With reference again to FIG. 1, one or more reference electrodes 76 to be employed in connection with the ISFET array 100 may be placed in the flow cell 200 (e.g., disposed in unused wells of the flow cell) or otherwise exposed to a reference (e.g., one or more of the sequencing reagents 172) to establish a base line against which changes in analyte concentration proximate to respective ISFETs of the array 100 are compared. The reference electrode(s) 76 may be electrically coupled to the array 100, the array controller 250 or directly to the computer 260 to facilitate analyte measurements based on voltage signals obtained from the array 100; in some implementations, the reference electrode(s) may be coupled to an electric ground or other predetermined potential, or the reference electrode voltage may be measured with respect to ground, to establish an electric reference for ISFET output signal measurements, as discussed further below.

(160) The ISFET array 100 is not limited to any particular size, as one- or two-dimensional arrays, including but not limited to as few as two to 256 pixels (e.g., 16 by 16 pixels in a two-dimensional implementation) or as many as 54 mega-pixels (e.g., 7400 by 7400 pixels in a two-dimensional implementation) or even greater may be fabricated and employed for various chemical/biological analysis purposes pursuant to the concepts disclosed herein. In one embodiment of the exemplary system shown in FIG. 8, the individual ISFET sensors of the array may be configured for sensitivity to hydrogen ions; however, it should also be appreciated that the present disclosure is not limited in this respect, as individual sensors of an ISFET sensor array may be particularly configured for sensitivity to other types of ion concentrations for a variety of applications (materials sensitive to other ions such as sodium, silver, iron, bromine, iodine, calcium, and nitrate, for example, are known).

(161) More generally, a chemFET array according to various embodiments of the present disclosure may be configured for sensitivity to any one or more of a variety of analytes. In one embodiment, one or more chemFETs of an array may be particularly configured for sensitivity to one or more analytes and/or one or more binding events, and in other embodiments different chemFETs of a given array may be configured for sensitivity to different analytes. For example, in one embodiment, one or more sensors (pixels) of the array may include a first type of chemFET configured to be sensitive to a first analyte, and one or more other sensors of the array may include a second type of chemFET configured to be sensitive to a second analyte different from the first analyte. In one exemplary implementation, both a first and a second analyte may indicate a particular reaction such as for example nucleotide incorporation in a sequencing-by-synthesis method. Of course, it should be appreciated that more than two different types of chemFETs may be employed in any given array to detect and/or measure different types of analytes and/or other reactions. In general, it should be appreciated in any of the embodiments of sensor arrays discussed herein that a given sensor array may be homogeneous and include chemFETs of substantially similar or identical types to detect and/or measure a same type of analyte (e.g., hydrogen ions), or a sensor array may be heterogeneous and include chemFETs of different types to detect and/or measure different analytes. For simplicity of discussion, again the example of an ISFET is discussed below in various embodiments of sensor arrays, but the present disclosure is not limited in this respect, and several other options for analyte sensitivity are discussed in further detail below (e.g., in connection with FIG. 11A).

(162) The chemFET arrays configured for sensitivity to any one or more of a variety of analytes may be disposed in electronic chips, and each chip may be configured to perform one or more different biological reactions. The electronic chips can be connected to the portions of the above-described system which read the array output by means of pins coded in a manner such that the pins convey information to the system as to characteristics of the array and/or what kind of biological reaction(s) is(are) to be performed on the particular chip.

(163) In one embodiment, the invention encompasses an electronic chip configured for conducting biological reactions thereon, comprising one or more pins for delivering information to a circuitry identifying a characteristic of the chip and/or a type of reaction to be performed on the chip. Such reactions or applications may include, but are not limited to, nucleotide polymorphism detection, short tandem repeat detection, or general sequencing.

(164) In another embodiment, the invention encompasses a system adapted to perform more than one biological reaction on a chip the system comprising a chip receiving module adapted for receiving the chip, and a receiver for detecting information from the electronic chip, wherein the information determines a biological reaction to be performed on the chip. Typically, the system further comprises one or more reagents to perform the selected biological reaction.

(165) In another embodiment, the invention encompasses an apparatus for sequencing a polymer template comprising at least one integrated circuit that is configured to relay information about spatial location of a reaction chamber, the type of monomer added to the spatial location, and the time required to complete reaction of a reagent comprising a plurality of the monomers with an elongating polymer.

(166) In exemplary implementations based on 0.35 micrometer CMOS processing techniques (or CMOS processing techniques capable of smaller feature sizes), each pixel of the ISFET array 100 may include an ISFET and accompanying enable/select components, and may occupy an area on a surface of the array of approximately ten micrometers by ten micrometers (i.e., 100 micrometers.sup.2) or less; stated differently, arrays having a pitch (center of pixel-to-center of pixel spacing) on the order of 10 micrometers or less may be realized. An array pitch on the order of 10 micrometers or less using a 0.35 micrometer CMOS processing technique constitutes a significant improvement in terms of size reduction with respect to prior attempts to fabricate ISFET arrays, which resulted in pixel sizes on the order of at least 12 micrometers or greater.

(167) More specifically, in some embodiments discussed further below based on the inventive concepts disclosed herein, an array pitch of approximately nine (9) micrometers allows an ISFET array including over 256,000 pixels (e.g., a 512 by 512 array), together with associated row and column select and bias/readout electronics, to be fabricated on a 7 millimeter by 7 millimeter semiconductor die, and a similar sensor array including over four million pixels (e.g., a 2048 by 2048 array) to be fabricated on a 21 millimeter by 21 millimeter die. In other examples, an array pitch of approximately 5 micrometers allows an ISFET array including approximately 1.55 Mega-pixels (i.e., a 1348 by 1152 array) and associated electronics to be fabricated on a 9 millimeter by 9 millimeter die, and an ISFET sensor array including over 14 Mega-pixels and associated electronics on a 22 millimeter by 20 millimeter die. In yet other implementations, using a CMOS fabrication process in which feature sizes of less than 0.35 micrometers are possible (e.g., 0.18 micrometer CMOS processing techniques), ISFET sensor arrays with a pitch significantly below 5 micrometers may be fabricated (e.g., array pitch of 2.6 micrometers or pixel area of less than 8 or 9 micrometers.sup.2), providing for significantly dense ISFET arrays.

(168) As will be understood by those of skill in the art, the ability to miniaturize sequencing reactions reduces the time, cost and labor involved in sequencing of large genomes (such as the human genome). Of course, it should be appreciated that pixel sizes greater than 10 micrometers (e.g., on the order of approximately 20, 50, 100 micrometers or greater) may be implemented in various embodiments of chemFET arrays according to the present disclosure also.

(169) In other aspects of the system shown in FIG. 8, one or more array controllers 250 may be employed to operate the ISFET array 100 (e.g., selecting/enabling respective pixels of the array to obtain output signals representing analyte measurements). In various implementations, one or more components constituting one or more array controllers may be implemented together with pixel elements of the arrays themselves, on the same integrated circuit (IC) chip as the array but in a different portion of the IC chip, or off-chip. In connection with array control, analog-to-digital conversion of ISFET output signals may be performed by circuitry implemented on the same integrated circuit chip as the ISFET array, but located outside of the sensor array region (locating the analog to digital conversion circuitry outside of the sensor array region allows for smaller pitch and hence a larger number of sensors, as well as reduced noise). In various exemplary implementations discussed further below, analog-to-digital conversion can be 4-bit, 8-bit, 12-bit, 16-bit or other bit resolutions depending on the signal dynamic range required.

(170) In general, data may be removed from the array in serial or parallel or some combination thereof. On-chip controllers (or sense amplifiers) can control the entire chip or some portion of the chip. Thus, the chip controllers or signal amplifiers may be replicated as necessary according to the demands of the application. The array may, but need not be, uniform. For instance, if signal processing or some other constraint requires instead of one large array multiple smaller arrays, each with its own sense amplifiers or controller logic, that is quite feasible.

(171) Having provided a general overview of the role of a chemFET (e.g., ISFET) array 100 in an exemplary system 1000 for measuring one or more analytes, following below are more detailed descriptions of exemplary chemFET arrays according to various inventive embodiments of the present disclosure that may be employed in a variety of applications. Again, for purposes of illustration, chemFET arrays according to the present disclosure are discussed below using the particular example of an ISFET array, but other types of chemFETs may be employed in alternative embodiments. Also, again, for purposes of illustration, chemFET arrays are discussed in the context of nucleic acid sequencing applications, however, the invention is not so limited and rather contemplates a variety of applications for the chemFET arrays described herein.

(172) As noted above, various inventive embodiments disclosed herein specifically improve upon the ISFET array design of Milgrew et al. discussed above in connection with FIGS. 1-7, as well as other prior ISFET array designs, so as to significantly reduce pixel size and array pitch, and thereby increase the number of pixels of an ISFET array for a given semiconductor die size (i.e., increase pixel density). In some implementations, an increase in pixel density is accomplished while at the same time increasing the signal-to-noise ratio (SNR) of output signals corresponding to respective measurements relating to one or more analytes and the speed with which such output signals may be read from the array. In particular, by relaxing requirements for ISFET linearity and focusing on a more limited signal output/measurement range (e.g., signal outputs corresponding to a pH range of from approximately 7 to 9 or smaller rather than 1 to 14, as well as output signals that may not necessarily relate significantly to pH changes in sample), individual pixel complexity and size may be significantly reduced, thereby facilitating the realization of very large scale dense ISFET arrays.

(173) To this end, FIG. 9 illustrates one column 102.sub.j of an ISFET array 100, according to one inventive embodiment of the present disclosure, in which ISFET pixel design is appreciably simplified to facilitate small pixel size. The column 102.sub.j includes n pixels, the first and last of which are shown in FIG. 9 as the pixels 105.sub.1 and 105.sub.n. As discussed further below in connection with FIG. 13, a complete two-dimensional ISFET array 100 based on the column design shown in FIG. 9 includes m such columns 102.sub.j (j=I, 2, 3, . . . m) with successive columns of pixels generally arranged side by side. Of course, the ISFETs may be arrayed in other than a row-column grid, such as in a honeycomb pattern.

(174) In one aspect of the embodiment shown in FIG. 9, each pixel 105.sub.1 through 105.sub.n of the column 102.sub.j includes only three components, namely, an ISFET 150 (also labeled as Q1) and two MOSFET switches Q2 and Q3. The MOSFET switches Q2 and Q3 are both responsive to one of n row select signals (RowSel.sub.1 through RowSel.sub.n, logic low active) so as to enable or select a given pixel of the column 102.sub.j. Using pixel 105.sub.1 as an example that applies to all pixels of the column, the transistor switch Q3 couples a controllable current source 106.sub.j via the line 112.sub.1 to the source of the ISFET 150 upon receipt of the corresponding row select signal via the line 118.sub.1. The transistor switch Q2 couples the source of the ISFET 150 to column bias/readout circuitry 110.sub.j via the line 114.sub.1 upon receipt of the corresponding row select signal. The drain of the ISFET 150 is directly coupled via the line 116.sub.1 to the bias/readout circuitry 110.sub.j. Thus, only four signal lines per pixel, namely the lines 112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1, are required to operate the three components of the pixel 105.sub.1. In an array of m columns, a given row select signal is applied simultaneously to one pixel of each column (e.g., at same positions in respective columns).

(175) As illustrated in FIG. 9, the design for the column 102.sub.j according to one embodiment is based on general principles similar to those discussed above in connection with the column design of Milgrew et al. shown FIG. 3. In particular, the ISFET of each pixel, when enabled, is configured with a constant drain current I.sub.Dj and a constant drain-to-source voltage V.sub.DSj to obtain an output signal V.sub.Sj from an enabled pixel according to Eq. (3) above. To this end, the column 102.sub.j includes a controllable current source 106.sub.j, coupled to an analog circuitry positive supply voltage VDDA and responsive to a bias voltage VB1, that is shared by all pixels of the column to provide a constant drain current I.sub.Dj to the ISFET of an enabled pixel. In one aspect, the current source 106.sub.j is implemented as a current mirror including two long-channel length and high output impedance MOSFETs. The column also includes bias/readout circuitry 110.sub.j that is also shared by all pixels of the column to provide a constant drain-to-source voltage to the ISFET of an enabled pixel. The bias/readout circuitry 110.sub.j is based on a Kelvin Bridge configuration and includes two operational amplifiers 107A (A1) and 107B (A2) configured as buffer amplifiers and coupled to analog circuitry positive supply voltage VDDA and the analog supply voltage ground VSSA. The bias/readout circuitry also includes a controllable current sink 108.sub.j (similar to the current source 106.sub.j) coupled to the analog ground VSSA and responsive to a bias voltage VB2, and a diode-connected MOSFET Q6. The bias voltages VB1 and VB2 are set/controlled in tandem to provide a complimentary source and sink current. The voltage developed across the diode-connected MOSFET Q6 as a result of the current drawn by the current sink 108.sub.j is forced by the operational amplifiers to appear across the drain and source of the ISFET of an enabled pixel as a constant drain-source voltage V.sub.DSj.

(176) By employing the diode-connected MOSFET Q6 in the bias/readout circuitry 110.sub.j of FIG. 9, rather than the resistor R.sub.SDj as shown in the design of Milgrew et al. illustrated in FIG. 3, a significant advantage is provided in a CMOS fabrication process; specifically, matching resistors can be fabricated with error tolerances generally on the order of 20%, whereas MOSFET matching in a CMOS fabrication process is on the order of 1% or better. The degree to which the component responsible for providing a constant ISFET drain-to-source voltage V.sub.DSj can be matched from column to column significantly affects measurement accuracy (e.g., offset) from column to column. Thus, employing the MOSFET Q6 rather than a resistor appreciably mitigates measurement offsets from column-to-column. Furthermore, whereas the thermal drift characteristics of a resistor and an ISFET may be appreciably different, the thermal drift characteristics of a MOSFET and ISFET are substantially similar, if not virtually identical; hence, any thermal drift in MOSFET Q6 virtually cancels any thermal drift from ISFET Q1, resulting in greater measurement stability with changes in array temperature.

(177) In FIG. 9, the column bias/readout circuitry 110.sub.j also includes sample/hold and buffer circuitry to provide an output signal V.sub.COLj from the column. In particular, after one of the pixels 105.sub.1 through 105.sub.n is enabled or selected via the transistors Q2 and Q3 in each pixel, the output of the amplifier 107A (A1), i.e., a buffered V.sub.Sj, is stored on a column sample and hold capacitor C.sub.sh via operation of a switch (e.g., a transmission gate) responsive to a column sample and hold signal COL SH. Examples of suitable capacitances for the sample and hold capacitor include, but are not limited to, a range of from approximately 500 fF to 2 pF. The sampled voltage is buffered via a column output buffer amplifier 111j (BUF) and provided as the column output signal V.sub.COLj. As also shown in FIG. 9, a reference voltage VREF may be applied to the buffer amplifier 111j, via a switch responsive to a control signal CAL, to facilitate characterization of column-to-column non-uniformities due to the buffer amplifier 111j and thus allow post-read data correction.

(178) FIG. 9A illustrates an exemplary circuit diagram for one of the amplifiers 107A of the bias/readout circuitry 110.sub.j (the amplifier 107B is implemented identically), and FIG. 9B is a graph of amplifier bias vs. bandwidth for the amplifiers 107A and 107B. As shown in FIG. 9A, the amplifier 107A employs an arrangement of multiple current mirrors based on nine MOSFETs (M1 through M9) and is configured as a unity gain buffer, in which the amplifier's inputs and outputs are labeled for generality as IN+ and VOUT, respectively. The bias voltage VB4 (representing a corresponding bias current) controls the transimpedance of the amplifier and serves as a bandwidth control (i.e., increased bandwidth with increased current). With reference again to FIG. 9, due to the sample and hold capacitor Csh, the output of the amplifier 107A essentially drives a filter when the sample and hold switch is closed. Accordingly, to achieve appreciably high data rates, the bias voltage VB4 may be adjusted to provide higher bias currents and increased amplifier bandwidth. From FIG. 9B, it may be observed that in some exemplary implementations, amplifier bandwidths of at least 40 MHz and significantly greater may be realized. In some implementations, amplifier bandwidths as high as 100 MHz may be appropriate to facilitate high data acquisition rates and relatively lower pixel sample or dwell times (e.g., on the order of 10 to 20 microseconds).

(179) In another aspect of the embodiment shown in FIG. 9, unlike the pixel design of Milgrew et al. shown in FIG. 3, the pixels 105.sub.1 through 105.sub.n do not include any transmission gates or other devices that require both n-channel and p-channel FET components; in particular, the pixels 105.sub.1 through 105.sub.n of this embodiment include only FET devices of a same type (i.e., only n-channel or only p-channel). For purposes of illustration, the pixels 105.sub.1 and 105.sub.n illustrated in FIG. 9 are shown as comprising only p-channel components, i.e., two p-channel MOSFETs Q2 and Q3 and a p-channel ISFET 150. By not employing a transmission gate to couple the source of the ISFET to the bias/readout circuitry 110.sub.j, some dynamic range for the ISFET output signal (i.e., the ISFET source voltage V.sub.S) may be sacrificed. However, by potentially foregoing some output signal dynamic range (and thereby potentially limiting measurement range for a given static and/or dynamic chemical property, such as pH), the requirement of different type FET devices (both n-channel and p-channel) in each pixel may be eliminated and the pixel component count reduced. As discussed further below in connection with FIGS. 10-12, this significantly facilitates pixel size reduction. Thus, in one aspect, there is a beneficial tradeoff between reduced dynamic range and smaller pixel size.

(180) In yet another aspect of the embodiment shown in FIG. 9, unlike the pixel design of Milgrew et al., the ISFET 150 of each pixel 105.sub.1 through 105.sub.n does not have its body connection tied to its source (i.e., there is no electrical conductor coupling the body connection and source of the ISFET such that they are forced to be at the same electric potential during operation). Rather, the body connections of all ISFETs of the array are tied to each other and to a body bias voltage V.sub.BODY. While not shown explicitly in FIG. 9, the body connections for the MOSFETs Q2 and Q3 likewise are not tied to their respective sources, but rather to the body bias voltage V.sub.BODY. In one exemplary implementation based on pixels having all p-channel components, the body bias voltage V.sub.BODY is coupled to the highest voltage potential available to the array (e.g., VDDA), as discussed further below in connection with FIG. 17.

(181) By not tying the body connection of each ISFET to its source, the possibility of some non-zero source-to-body voltage V.sub.SB may give rise to the body effect, as discussed above in connection with FIG. 1, which affects the threshold voltage V.sub.TH of the ISFET according to a nonlinear relationship (and thus, according to Eq. (3), (4) and (5) may affect detection and/or measurement of analyte activity giving rise to surface potential changes at the analyte/passivation layer interface). However, by focusing on a reduced ISFET output signal dynamic range, any body effect that may arise in the ISFET from a non-zero source-to-body voltage may be relatively minimal. Thus, any measurement nonlinearity that may result over the reduced dynamic range may be ignored as insignificant or taken into consideration and compensated (e.g., via array calibration and data processing techniques, as discussed further below in connection with FIG. 17). By not tying each ISFET source to its body connection, all of the FETs constituting the pixel may share a common body connection, thereby further facilitating pixel size reduction, as discussed further below in connection with FIGS. 10-12. Accordingly, in another aspect, there is a beneficial tradeoff between reduced linearity and smaller pixel size.

(182) FIG. 10 illustrates a top view of a chip layout design for the pixel 105.sub.1 shown in FIG. 9, according to one inventive embodiment of the present disclosure. FIG. 11A shows a composite cross-sectional view along the line I-I of the pixel shown in FIG. 10, including additional elements on the right half of FIG. 10 between the lines II-II and III-III, illustrating a layer-by-layer view of the pixel fabrication, and FIGS. 12A through 12L provide top views of each of the fabrication layers shown in FIG. 11A (the respective images of FIGS. 12A through 12L are superimposed one on top of another to create the pixel chip layout design shown in FIG. 10). In one exemplary implementation, the pixel design illustrated in FIGS. 10-12 may be realized using a standard 4-metal, 2-poly, 0.35 micrometer CMOS process to provide a geometrically square pixel having a dimension e as shown in FIG. 10 of approximately 9 micrometers, and a dimension f corresponding to the ISFET sensitive area of approximately 7 micrometers.

(183) In the top view of FIG. 10, the ISFET 150 (labeled as Q1 in FIG. 10) generally occupies the right center portion of the pixel illustration, and the respective locations of the gate, source and drain of the ISFET are indicated as Q1.sub.G, Q1.sub.S and Q1.sub.D. The MOSFETs Q2 and Q3 generally occupy the left center portion of the pixel illustration; the gate and source of the MOSFET Q2 are indicated as Q2.sub.G and Q2.sub.S, and the gate and source of the MOSFET Q3 are indicated as Q3.sub.G and Q3.sub.S. In one aspect of the layout shown in FIG. 10, the MOSFETs Q2 and Q3 share a drain, indicated as Q2/3.sub.D. In another aspect, it may be observed generally from the top view of FIG. 10 that the ISFET is formed such that its channel lies along a first axis of the pixel (e.g., parallel to the line I-I), while the MOSFETs Q2 and Q3 are formed such that their channels lie along a second axis perpendicular to the first axis. FIG. 10 also shows the four lines required to operate the pixel, namely, the line 112.sub.1 coupled to the source of Q3, the line 114.sub.1 coupled to the source of Q2, the line 116.sub.1 coupled to the drain of the ISFET, and the row select line 118.sub.1 coupled to the gates of Q2 and Q3. With reference to FIG. 9, it may be appreciated that all pixels in a given column share the lines 112, 114 and 116 (e.g., running vertically across the pixel in FIG. 10), and that all pixels in a given row share the line 118 (e.g., running horizontally across the pixel in FIG. 10); thus, based on the pixel design of FIG. 9 and the layout shown in FIG. 10, only four metal lines need to traverse each pixel.

(184) With reference now to the cross-sectional view of FIG. 11A, highly doped p-type regions 156 and 158 (lying along the line I-I in FIG. 10) in n-well 154 constitute the source (S) and drain (D) of the ISFET, between which lies a region 160 of the n-well in which the ISFETs p-channel is formed below the ISFETs polysilicon gate 164 and a gate oxide 165. According to one aspect of the inventive embodiment shown in FIGS. 10 and 11, all of the FET components of the pixel 105.sub.1 are fabricated as p-channel FETs in the single n-type well 154 formed in a p-type semiconductor substrate 152. This is possible because, unlike the design of Milgrew et al., 1) there is no requirement for a transmission gate in the pixel; and 2) the ISFETs source is not tied to the n-well's body connection. More specifically, highly doped n-type regions 162 provide a body connection (B) to the n-well 154 and, as shown in FIG. 10, the body connection B is coupled to a metal conductor 322 around the perimeter of the pixel 105.sub.1. However, the body connection is not directly electrically coupled to the source region 156 of the ISFET (i.e., there is no electrical conductor coupling the body connection and source such that they are forced to be at the same electric potential during operation), nor is the body connection directly electrically coupled to the gate, source or drain of any component in the pixel. Thus, the other p-channel FET components of the pixel, namely Q2 and Q3, may be fabricated in the same n-well 154.

(185) In the composite cross-sectional view of FIG. 11A, a highly doped p-type region 159 is also visible (lying along the line I-I in FIG. 10), corresponding to the shared drain (D) of the MOSFETs Q2 and Q3. For purposes of illustration, a polysilicon gate 166 of the MOSFET Q3 also is visible in FIG. 11A, although this gate does not lie along the line I-I in FIG. 10, but rather behind the plane of the cross-section along the line I-I. However, for simplicity, the respective sources of the MOSFETs Q2 and Q3 shown in FIG. 10, as well as the gate of Q2, are not visible in FIG. 11A, as they lie along the same axis (i.e., perpendicular to the plane of the figure) as the shared drain (if shown in FIG. 11A, these elements would unduly complicate the composite cross-sectional view of FIG. 11A).

(186) Above the substrate, gate oxide, and polysilicon layers shown in FIG. 11A, a number of additional layers are provided to establish electrical connections to the various pixel components, including alternating metal layers and oxide layers through which conductive vias are formed. Pursuant to the example of a 4-Metal CMOS process, these layers are labeled in FIG. 11A as Contact, Metal1, Via1, Metal2, Via2, Metal3, Via3, and Metal4. (Note that more or fewer metal layers may be employed.) To facilitate an understanding particularly of the ISFET electrical connections, the composite cross-sectional view of FIG. 11A shows additional elements of the pixel fabrication on the right side of the top view of FIG. 10 between the lines II-II and III-III. With respect to the ISFET electrical connections, the topmost metal layer 304 corresponds to the ISFETs sensitive area 178, above which is disposed an analyte-sensitive passivation layer 172. The topmost metal layer 304, together with the ISFET polysilicon gate 164 and the intervening conductors 306, 308,312, 316,320, 326 and 338, form the ISFETs floating gate structure 170, in a manner similar to that discussed above in connection with a conventional ISFET design shown in FIG. 1. An electrical connection to the ISFETs drain is provided by the conductors 340, 328, 318, 314 and 310 coupled to the line 116.sub.1. The ISFETs source is coupled to the shared drain of the MOSFETs Q2 and Q3 via the conductors 334 and 336 and the conductor 324 (which lies along the line I-I in FIG. 10). The body connections 162 to the n-well 154 are electrically coupled to a metal conductor 322 around the perimeter of the pixel on the Metal1 layer via the conductors 330 and 332.

(187) As indicated above, FIGS. 12A through 12L provide top views of each of the fabrication layers shown in FIG. 11A (the respective images of FIGS. 12A through 12L are superimposed one on top of another to create the pixel chip layout design shown in FIG. 10). In FIG. 12, the correspondence between the lettered top views of respective layers and the cross-sectional view of FIG. 11A is as follows: A) n-type well 154; B) Implant; C) Diffusion; D) polysilicon gates 164 (ISFET) and 166 (MOSFETs Q2 and Q3); E) contacts; F) Metal1; G) Via1; H) Metal2; I) Via2; J) Metal3; K) Via3; L) Metal4 (top electrode contacting ISFET gate). The various reference numerals indicated in FIGS. 12A through 12L correspond to the identical features that are present in the composite cross-sectional view of FIG. 11A.

(188) At least in some applications, pixel capacitance may be a salient parameter for some type of analyte measurements. Accordingly, in another embodiment related to pixel layout and design, various via and metal layers may be reconfigured so as to at least partially mitigate the potential for parasitic capacitances to arise during pixel operation. For example, in one such embodiment, pixels are designed such that there is a greater vertical distance between the signal lines 112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1, and the topmost metal layer 304 constituting the floating gate structure 170.

(189) In the embodiment described immediately above, with reference again to FIG. 11A, it may be readily observed that the topmost metal layer 304 is formed in the Metal4 layer (also see FIG. 12L), and the signal lines 112.sub.1, 114.sub.1, and 116.sub.1 are formed in the Metal3 layer (also see FIG. 12J). Also, while not visible in the view of FIG. 11A, it may be observed from FIG. 12H that the signal line 1181 is formed in the Metal2 layer. As one or more of these signals may be grounded from time to time during array operation, a parasitic capacitance may arise between any one or more of these signal lines and metal layer 304. By increasing a distance between these signal lines and the metal layer 304, such parasitic capacitance may be reduced.

(190) To this end, in another embodiment some via and metal layers are reconfigured such that the signal lines 112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1 are implemented in the Metal1 and Metal2 layers, and the Metal3 layer is used only as a jumper between the Metal2 layer component of the floating gate structure 170 and the topmost metal layer 304, thereby ensuring a greater distance between the signal lines and the metal layer 304. FIG. 10-1 illustrates a top view of a such a chip layout design for a cluster of four neighboring pixels of an chemFET array shown in FIG. 9, with one particular pixel 105.sub.1 identified and labeled. FIG. 11A-1 shows a composite cross-sectional view of neighboring pixels, along the line I-I of the pixel 1051 shown in FIG. 10-1, including additional elements between the lines II-II, illustrating a layer-by-layer view of the pixel fabrication, and FIGS. 12-1A through 12-1L provide top views of each of the fabrication layers shown in FIG. 11A-1 (the respective images of FIGS. 12-1A through 12-1L are superimposed one on top of another to create the pixel chip layout design shown in FIG. 10-1).

(191) In FIG. 10-1, it may be observed that the pixel top view layout is generally similar to that shown in FIG. 10. For example, in the top view, the ISFET 150 generally occupies the right center portion of each pixel, and the MOSFETs Q2 and Q3 generally occupy the left center portion of the pixel illustration. Many of the component labels included in FIG. 10 are omitted from FIG. 10-1 for clarity, although the ISFET polysilicon gate 164 is indicated in the pixel 1051 for orientation. FIG. 10-1 also shows the four lines (112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1) required to operate the pixel. One noteworthy difference between FIG. 10 and FIG. 10-1 relates to the metal conductor 322 (located on the Metal1 layer) which provides an electrical connection to the body region 162; namely, in FIG. 10, the conductor 322 surrounds a perimeter of the pixel, whereas in FIG. 10-1, the conductor 322 does not completely surround a perimeter of the pixel but includes discontinuities 727. These discontinuities 727 permit the line 1181 to also be fabricated on the Metal1 layer and traverse the pixel to connect to neighboring pixels of a row.

(192) With reference now to the cross-sectional view of FIG. 11A-1, three adjacent pixels are shown in cross-section, with the center pixel corresponding to the pixel 105.sub.1 in FIG. 10-1 for purposes of discussion. As in the embodiment of FIG. 11A, all of the FET components of the pixel 105.sub.1 are fabricated as p-channel FETs in the single n-type well 154. Additionally, as in FIG. 11A, in the composite cross-sectional view of FIG. 11A-1 the highly doped p-type region 159 is also visible (lying along the line I-I in FIG. 10-1), corresponding to the shared drain (D) of the MOSFETs Q2 and Q3. For purposes of illustration, the polysilicon gate 166 of the MOSFET Q3 also is visible in FIG. 11A-1, although this gate does not lie along the line I-I in FIG. 10-1, but rather behind the plane of the cross-section along the line I-I. However, for simplicity, the respective sources of the MOSFETs Q2 and Q3 shown in FIG. 10-1, as well as the gate of Q2, are not visible in FIG. 11A-1, as they lie along the same axis (i.e., perpendicular to the plane of the figure) as the shared drain. Furthermore, to facilitate an understanding of the ISFET floating gate electrical connections, the composite cross-sectional view of FIG. 11A-1 shows additional elements of the pixel fabrication between the lines II-II of FIG. 10-1.

(193) More specifically, as in the embodiment of FIG. 11A, the topmost metal layer 304 corresponds to the ISFETs sensitive area 178, above which is disposed an analyte-sensitive passivation layer 172. The topmost metal layer 304, together with the ISFET polysilicon gate 164 and the intervening conductors 306, 308, 312, 316, 320, 326 and 338, form the ISFETs floating gate structure 170. However, unlike the embodiment of FIG. 11A, an electrical connection to the ISFETs drain is provided by the conductors 340, 328, and 318, coupled to the line 1161 which is formed in the Metal2 layer rather than the Metal3 layer. Additionally, the lines 112.sub.1 and 114.sub.1 also are shown in FIG. 11A-1 as formed in the Metal2 layer rather than the Metal3 layer. The configuration of these lines, as well as the line 118.sub.1, may be further appreciated from the respective images of FIGS. 12-1A through 12-1L (in which the correspondence between the lettered top views of respective layers and the cross-sectional view of FIG. 11A-1 is the same as that described in connection with FIGS. 12A-12L); in particular, it may be observed in FIG. 12-1F that the line 118.sub.1, together with the metal conductor 322, is formed in the Metal1 layer, and it may be observed that the lines 112.sub.1, 114.sub.1 and 116.sub.1 are formed in the Metal2 layer, leaving only the jumper 308 of the floating gate structure 170 in the Metal3 layer shown in FIG. 12-1J.

(194) Accordingly, by consolidating the signal lines 112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1 to the Metal1 and Metal2 layers and thereby increasing the distance between these signal lines and the topmost layer 304 of the floating gate structure 170 in the Metal4 layer, parasitic capacitances in the ISFET may be at least partially mitigated. It should be appreciated that this general concept (e.g., including one or more intervening metal layers between signal lines and topmost layer of the floating gate structure) may be implemented in other fabrication processes involving greater numbers of metal layers. For example, distance between pixel signal lines and the topmost metal layer may be increased by adding additional metal layers (more than four total metal layers) in which only jumpers to the topmost metal layer are formed in the additional metal layers. In particular, a six-metal-layer fabrication process may be employed, in which the signal lines are fabricated using the Metal1 and Metal2 layers, the topmost metal layer of the floating gate structure is formed in the Metal6 layer, and jumpers to the topmost metal layer are formed in the Metal3, Metal4 and Metal5 layers, respectively (with associated vias between the metal layers). In another exemplary implementation based on a six-metal-layer fabrication process, the general pixel configuration shown in FIGS. 10, 11A, and 12A-12L may be employed (signal lines on Metal2 and Metal3 layers), in which the topmost metal layer is formed in the Metal6 layer and jumpers are formed in the Metal4 and Metal5 layers, respectively.

(195) In yet another aspect relating to reduced capacitance, a dimension f of the topmost metal layer 304 (and thus the ISFET sensitive area 178) may be reduced so as to reduce cross-capacitance between neighboring pixels. As may be observed in FIG. 11A-1 (and as discussed further below in connection with other embodiments directed to well fabrication above an ISFET array), the well 725 may be fabricated so as to have a tapered shape, such that a dimension g at the top of the well is smaller than the pixel pitch e but yet larger than a dimension f at the bottom of the well. Based on such tapering, the topmost metal layer 304 also may be designed with the dimension f rather than the dimension g so as to provide for additional space between the top metal layers of neighboring pixels. In some illustrative non-limiting implementations, for pixels having a dimension e on the order of 9 micrometers the dimension f may be on the order of 6 micrometers (as opposed to 7 micrometers, as discussed above), and for pixels having a dimension e on the order of 5 micrometers the dimension f may be on the order of 3.5 micrometers.

(196) Thus, the pixel chip layout designs respectively shown in FIGS. 10, 11A, and 12A through 12L, and FIGS. 10-1, 11A-1, and 12-1A through 12-1L, illustrate that according to various embodiments FET devices of a same type may be employed for all components of a pixel, and that all components may be implemented in a single well. This dramatically reduces the area required for the pixel, thereby facilitating increased pixel density in a given area.

(197) In one exemplary implementation, the gate oxide 165 for the ISFET may be fabricated to have a thickness on the order of approximately 75 Angstroms, giving rise to a gate oxide capacitance per unit area C.sub.ox of 4.5 fF/m.sup.2. Additionally, the polysilicon gate 164 may be fabricated with dimensions corresponding to a channel width W of 1.2 m and a channel length L of from 0.35 to 0.6 m (i.e., W/L ranging from approximately 2 to 3.5), and the doping of the region 160 may be selected such that the carrier mobility for the p-channel is 190 cm.sup.2V.Math.s (i.e., 1.9E10 m.sup.2V.Math.s). From Eq. (2) above, this results in an ISFET transconductance parameter on the order of approximately 170 to 300 A/V.sup.2. In other aspects of this exemplary implementation, the analog supply voltage VDDA is 3.3 Volts, and VB1 and VB2 are biased so as to provide a constant ISFET drain current I.sub.Dj on the order of 5 A (in some implementations, VB1 and VB2 may be adjusted to provide drain currents from approximately 1 A to 20 A). Additionally, the MOSFET Q6 (see bias/readout circuitry 110.sub.j in FIG. 9) is sized to have a channel width to length ratio (e.g., W/L of approximately 50) such that the voltage across Q6, given I.sub.Dj of 5 A, is 800 mV (i.e., V.sub.DSj=800 mV). From Eq. (3), based on these exemplary parameters, this provides for pixel output voltages V.sub.Sj over a range of approximately 0.5 to 2.5 Volts for ISFET threshold voltage changes over a range of approximately 0 to 2 Volts.

(198) With respect to the analyte-sensitive passivation layer 172 shown in FIG. 11A, in exemplary CMOS implementations the passivation layer may be significantly sensitive to the concentration of various ion species, including hydrogen, and may include silicon nitride (Si.sub.3N.sub.4) and/or silicon oxynitride (Si.sub.2N.sub.2O). In conventional CMOS processes, a passivation layer may be formed by one or more successive depositions of these materials, and is employed generally to treat or coat devices so as to protect against contamination and increase electrical stability. The material properties of silicon nitride and silicon oxynitride are such that a passivation layer comprising these materials provides scratch protection and serves as a significant barrier to the diffusion of water and sodium, which can cause device metallization to corrode and/or device operation to become unstable. A passivation layer including silicon nitride and/or silicon oxynitride also provides ion-sensitivity in ISFET devices, in that the passivation layer contains surface groups that may donate or accept protons from an analyte solution with which they are in contact, thereby altering the surface potential and the device threshold voltage V.sub.TH, as discussed above in connection with FIGS. 1 and 2A.

(199) For CMOS processes involving aluminum as the metal (which has a melting point of approximately 650 degrees Celsius), a silicon nitride and/or silicon oxynitride passivation layer generally is formed via plasma-enhanced chemical vapor deposition (PECVD), in which a glow discharge at 250-350 degrees Celsius ionizes the constituent gases that form silicon nitride or silicon oxynitride, creating active species that react at the wafer surface to form a laminate of the respective materials. In one exemplary process, a passivation layer having a thickness on the order of approximately 1.0 to 1.5 m may be formed by an initial deposition of a thin layer of silicon oxynitride (on the order of 0.2 to 0.4 m) followed by a slighting thicker deposition of silicon oxynitride (on the order of 0.5 m) and a final deposition of silicon nitride (on the order of 0.5 m). Because of the low deposition temperature involved in the PECVD process, the aluminum metallization is not adversely affected.

(200) However, while a low temperature PECVD process provides adequate passivation for conventional CMOS devices, the low-temperature process results in a generally low-density and somewhat porous passivation layer, which in some cases may adversely affect ISFET threshold voltage stability. In particular, during ISFET device operation, a low-density porous passivation layer over time may absorb and become saturated with ions from the solution, which may in turn cause an undesirable time-varying drift in the ISFETs threshold voltage V.sub.TH, making accurate measurements challenging.

(201) In view of the foregoing, in one embodiment a CMOS process that uses tungsten metal instead of aluminum may be employed to fabricate ISFET arrays according to the present disclosure. The high melting temperature of Tungsten (above 3400 degrees Celsius) permits the use of a higher temperature low pressure chemical vapor deposition (LPCVD) process (e.g., approximately 700 to 800 degrees Celsius) for a silicon nitride or silicon oxynitride passivation layer. The LPCVD process typically results in significantly more dense and less porous films for the passivation layer, thereby mitigating the potentially adverse effects of ion absorption from the analyte solution leading to ISFET threshold voltage drift.

(202) In yet another embodiment in which an aluminum-based CMOS process is employed to fabricate ISFET arrays according to the present disclosure, the passivation layer 172 shown in FIG. 11A may comprise additional depositions and/or materials beyond those typically employed in a conventional CMOS process. For example, the passivation layer 172 may include initial low-temperature plasma-assisted depositions (PECVD) of silicon nitride and/or silicon oxynitride as discussed above; for purposes of the present discussion, these conventional depositions are illustrated in FIG. 11A as a first portion 172A of the passivation layer 172. In one embodiment, following the first portion 172A, one or more additional passivation materials are disposed to form at least a second portion 172B to increase density and reduce porosity of (and absorption by) the overall passivation layer 172. While one additional portion 172B is shown primarily for purposes of illustration in FIG. 11A, it should be appreciated that the disclosure is not limited in this respect, as the overall passivation layer 172 may comprise two or more constituent portions, in which each portion may comprise one or more layers/depositions of same or different materials, and respective portions may be configured similarly or differently. Regardless of the specific materials, the passivation layer(s) provide chemical isolation between the analyte and the circuitry.

(203) Examples of materials suitable for the second portion 172B (or other additional portions) of the passivation layer 172 include, but are not limited to, silicon nitride, silicon oxynitride, aluminum oxide (Al.sub.2O.sub.3), tantalum oxide (Ta.sub.3O.sub.5), tin oxide (SnO.sub.2) and silicon dioxide (SiO.sub.2). In one aspect, the second portion 172B (or other additional portions) may be deposited via a variety of relatively low temperature processes including, but not limited to, RF sputtering, DC magnetron sputtering, thermal or e-beam evaporation, and ion-assisted depositions. In another aspect, a pre-sputtering etch process may be employed, prior to deposition of the second portion 172B, to remove any native oxide residing on the first portion 172A (alternatively, a reducing environment, such as an elevated temperature hydrogen environment, may be employed to remove native oxide residing on the first portion 172A). In yet another aspect, a thickness of the second portion 172B may be on the order of approximately 0.04 m to 0.06 m (400 to 600 Angstroms) and a thickness of the first portion may be on the order of 1.0 to 1.5 m, as discussed above. In some exemplary implementations, the first portion 172A may include multiple layers of silicon oxynitride and silicon nitride having a combined thickness of 1.0 to 1.5 m, and the second portion 172B may include a single layer of either aluminum oxide or tantalum oxide having a thickness of approximately 400 to 600 Angstroms. Again, it should be appreciated that the foregoing exemplary thicknesses are provided primarily for purposes of illustration, and that the disclosure is not limited in these respects.

(204) Thus it is to be understood that the chemFET arrays described herein may be used to detect and/or measure various analytes and, by doing so, may monitor a variety of reactions and/or interactions. It is also to be understood that the discussion herein relating to hydrogen ion detection (in the form of a pH change) is for the sake of convenience and brevity and that static or dynamic levels/concentrations of other analytes (including other ions) can be substituted for hydrogen in these descriptions. In particular, sufficiently fast concentration changes of any one or more of various ion species present in the analyte may be detected via the transient or dynamic response of a chemFET, as discussed above in connection with FIG. 2A. As also discussed above in connection with the Site-Dissociation (or Site-Binding) model for the analyte/passivation layer interface, it should be appreciated that various parameters relating to the equilibrium reactions at the analyte/passivation layer interface (e.g., rate constants for forward and backward equilibrium reactions, total number of proton donor/acceptor sites per unit area on the passivation layer surface, intrinsic buffering capacity, pH at point of zero charge) are material dependent properties and thus are affected by the choice of materials employed for the passivation layer.

(205) The chemFETs, including ISFETs, described herein are capable of detecting any analyte that is itself capable of inducing a change in electric field when in contact with or otherwise sensed or detected by the chemFET surface. The analyte need not be charged in order to be detected by the sensor. For example, depending on the embodiment, the analyte may be positively charged (i.e., a cation), negatively charged (i.e., an anion), zwitterionic (i.e., capable of having two equal and opposite charges but being neutral overall), and polar yet neutral. This list is not intended as exhaustive as other analyte classes as well as species within each class will be readily contemplated by those of ordinary skill in the art based on the disclosure provided herein.

(206) In the broadest sense of the invention, the passivation layer may or may not be coated and the analyte may or may not interact directly with the passivation layer.

(207) Passivation Layer Specificity

(208) In some embodiments, the passivation layer and/or the layers and/or molecules coated thereon dictate the analyte specificity of the array readout.

(209) Detection of hydrogen ions, and other analytes as determined by the invention, can be carried out using a passivation layer made of silicon nitride (Si.sub.3N.sub.4), silicon oxynitride (Si.sub.2N.sub.2O), silicon oxide (SiO.sub.2), aluminum oxide (Al.sub.2O.sub.3), tantalum pentoxide (Ta.sub.2O.sub.5), tin oxide or stannic oxide (SnO.sub.2), and the like.

(210) The passivation layer can also detect other ion species directly including but not limited to calcium, potassium, sodium, iodide, magnesium, chloride, lithium, lead, silver, cadmium, nitrate, phosphate, dihydrogen phosphate, and the like.

(211) In some embodiments, the passivation layer is coated with a receptor for the analyte of interest. Preferably, the receptor binds selectively to the analyte of interest or in some instances to a class of agents to which the analyte belongs. As used herein, a receptor that binds selectively to an analyte is a molecule that binds preferentially to that analyte (i.e., its binding affinity for that analyte is greater than its binding affinity for any other analyte). Its binding affinity for the analyte of interest may be 2-fold, 3-fold, 4-fold, 5-fold, 6-fold, 7-fold, 8-fold, 9-fold, 10-fold, 15-fold, 20-fold, 25-fold, 30-fold, 40-fold, 50-fold, 100-fold or more than its binding affinity for any other analyte. In addition to its relative binding affinity, the receptor must also have an absolute binding affinity that is sufficiently high to efficiently bind the analyte of interest (i.e., it must have a sufficient sensitivity). Receptors having binding affinities in the picomolar to micromolar range are suitable. Preferably such interactions are reversible.

(212) The receptor may be of any nature (e.g., chemical, nucleic acid, peptide, lipid, combinations thereof and the like). In such embodiments, the analyte too may be of any nature provided there exists a receptor that binds to it selectively and in some instances specifically. It is to be understood however that the invention further contemplates detection of analytes in the absence of a receptor. An example of this is the detection of PPi and Pi by the passivation layer in the absence of PPi or Pi receptors.

(213) In one aspect, the invention contemplates receptors that are ionophores. As used herein, an ionophore is a molecule that binds selectively to an ionic species, whether anion or cation. In the context of the invention, the ionophore is the receptor and the ion to which it binds is the analyte. Ionophores of the invention include art-recognized carrier ionophores (i.e., small lipid-soluble molecules that bind to a particular ion) derived from microorganisms. Various ionophores are commercially available from sources such as Calbiochem.

(214) Detection of some ions can be accomplished through the use of the passivation layer itself or through the use of receptors coated onto the passivation layer. For example, potassium can be detected selectively using polysiloxane, valinomycin, or salinomycin; sodium can be detected selectively using monensin, nystatin, or SQI-Pr; calcium can be detected selectively using ionomycin, calcimycine (A23187), or CA 1001 (ETH 1001).

(215) Receptors able to bind more than one ion can also be used in some instances. For example, beauvericin can be used to detect calcium and/or barium ions, nigericin can be used to detect potassium, hydrogen and/or lead ions, and gramicidin can be used to detect hydrogen, sodium and/or potassium ions. One of ordinary skill in the art will recognize that these compounds can be used in applications in which single ion specificity is not required or in which it is unlikely (or impossible) that other ions which the compounds bind will be present or generated. Similarly, receptors that bind multiple species of a particular genus may also be useful in some embodiments including those in which only one species within the genus will be present or in which the method does not require distinction between species.

(216) As another example, receptors for neurotoxins are described in Simonian Electroanalysis 2004, 16: 1896-1906.

(217) Passivation Layer and PPi Receptors

(218) In other embodiments, including but not limited to nucleic acid sequencing applications, receptors that bind selectively to PPi can be used. Examples of PPi receptors include those compounds shown in FIGS. 11B(1)-(3) (compounds 1-10). Compound 1 is described in Angew Chem Int (Ed 2004) 43:4777-4780 and US 2005/0119497 A1 and is referred to as p-naphthyl-bis[(bis(2-pyridylmethyl)amino)methyl]phenol. Compound 2 is described in J Am Chem Soc 2003 125:7752-7753 and US 2005/0119497 A1 and is referred to as p-(p-nitrophenylazo)-bis[(bis(2-pyridylmethyl-1)amino)methyl]phenol (or its dinuclear Zn complex). Synthesis schemes for compounds 1 and 2 are shown provided in US 2005/0119497 A1. Compound 3 is described by Lee et al. Organic Letters 2007 9(2):243-246, and in Sensors and Actuators B 1995 29:324-327. Compound 4 is described in Angew, Chem Int (Ed 2002) 41(20):3811-3814. Exemplary syntheses for compounds 7, 8 and 9 are shown in FIGS. 11C(1)-(3). Compound 5 is described in WO 2007/002204 and is referred to therein as bis-Zn.sup.2+-dipicolylamine (Zn.sup.2+-DPA). Compound 6 is illustrated in FIG. 11B(3) bound to PPi. (McDonough et al. Chern. Commun. 2006 2971-2973.) Attachment of compound 7 to a metal oxide surface is shown in FIG. 11E.

(219) Passivation LayerReceptor Binding

(220) Receptors may be attached to the passivation layer covalently or non-covalently. Covalent attachment of a receptor to the passivation layer may be direct or indirect (e.g., through a linker). FIGS. 11D(1) and (2) illustrate the use of silanol chemistry to covalently bind receptors to the passivation layer. Receptors may be immobilized on the passivation layer using for example aliphatic primary amines (bottom left panel) or aryl isothiocyanates (bottom right panel). In these and other embodiments, the passivation layer which itself may be comprised of silicon nitride, aluminum oxide, silicon oxide, tantalum pentoxide, or the like, is bonded to a silanation layer via its reactive surface groups. For greater detail on silanol chemistry for covalent attachment to the FET surface, reference can be made to at least the following publications: for silicon nitride, see Sensors and Actuators B 1995 29:324-327, Jpn J Appl Phys 1999 38:3912-3917 and Langmuir 2005 21:395-402; for silicon oxide, see Protein Sci 1995 4:2532-2544 and Am Biotechnol Lab 2002 20(7):16-18; and for aluminum oxide, see Colloids and Surfaces 1992 63:1-9, Sensors and Actuators B 2003 89:40-47, and Bioconjugate Chem 1997 8:424-433. The receptor is then conjugated to the silanation layer reactive groups. This latter binding can occur directly or indirectly through the use of a bifunctional linker, as illustrated in FIGS. 11D(1) and (2).

(221) A bifunctional linker is a compound having at least two reactive groups to which two entities may be bound. In some instances, the reactive groups are located at opposite ends of the linker. In some embodiments, the bifunctional linker is a universal bifunctional linker such as that shown in FIGS. 11D(1) and (2). A universal linker is a linker that can be used to link a variety of entities. It should be understood that the chemistries shown in FIGS. 11D(1) and (2) are meant to be illustrative and not limiting.

(222) The bifunctional linker may be a homo-bifunctional linker or a hetero-bifunctional linker, depending upon the nature of the molecules to be conjugated. Homo-bifunctional linkers have two identical reactive groups. Hetero-bifunctional linkers are have two different reactive groups. Various types of commercially available linkers are reactive with one or more of the following groups: primary amines, secondary amines, sulphydryls, carboxyls, carbonyls and carbohydrates. Examples of amine-specific linkers are bis(sulfosuccinimidyl) suberate, bis[2-(succinimidooxycarbonyloxy)ethyl]sulfone, disuccinimidyl suberate, disuccinimidyl tartarate, dimethyl adipimate.2 HCl, dimethyl pimelimidate.2 HCl, dimethyl suberimidate.2 HCl, and ethylene glycolbis-[succinimidyl-[succinate]]. Linkers reactive with sulfhydryl groups include bismaleimidohexane, 1,4-di-[3-(2-pyridyldithio)-propionamido)]butane, 1-[p-azidosalicylamido]-4-[iodoacetamido]butane, and N-[4-(p-azidosalicylamido) butyl]-3-[2-pyridyldithio]propionamide. Linkers preferentially reactive with carbohydrates include azidobenzoyl hydrazine. Linkers preferentially reactive with carboxyl groups include 4-[p-azidosalicylamido]butylamine.

(223) Heterobifunctional linkers that react with amines and sulfhydryls include N-succinimidyl-3-[2-pyridyldithio]propionate, succinimidyl[4-iodoacetyl]aminobenzoate, succinimidyl 4-[N-maleimidomethyl]cyclohexane-1-carboxylate, m-maleimidobenzoyl-N-hydroxysuccinimide ester, sulfosuccinimidyl 6-[3-[2-pyridyldithio]propionamido]hexanoate, and sulfosuccinimidyl 4-[N-maleimidomethyl]cyclohexane-1-carboxylate. Heterobifunctional linkers that react with carboxyl and amine groups include 1-ethyl-3-[3-dimethylaminopropyl]-carbodiimide hydrochloride. Heterobifunctional linkers that react with carbohydrates and sulfhydryls include 4-[N-maleimidomethyl]-cyclohexane-1-carboxylhydrazide.2 HCl, 4-(4-N-maleimidophenyl)-butyric acid hydrazide.2 HCl, and 3-[2-pyridyldithio]propionyl hydrazide.

(224) Alternatively, receptors may be non-covalently coated onto the passivation layer. Non-covalent deposition of the receptor onto the passivation layer may involve the use of a polymer matrix. The polymer may be naturally occurring or non-naturally occurring and may be of any type including but not limited to nucleic acid (e.g., DNA, RNA, PNA, LNA, and the like, or mimics, derivatives, or combinations thereof), amino acid (e.g., peptides, proteins (native or denatured), and the like, or mimics, derivatives, or combinations thereof, lipids, polysaccharides, and functionalized block copolymers. The receptor may be adsorbed onto and/or entrapped within the polymer matrix. The nature of the polymer will depend on the nature of the receptor being used and/or analyte being detected.

(225) Alternatively, the receptor may be covalently conjugated or crosslinked to the polymer (e.g., it may be grafted onto a functionalized polymer).

(226) An example of a suitable peptide polymer is poly-lysine (e.g., poly-L-lysine). Examples of other polymers include block copolymers that comprise polyethylene glycol (PEG), polyamides, polycarbonates, polyalkylenes, polyalkylene glycols, polyalkylene oxides, polyalkylene terepthalates, polyvinyl alcohols, polyvinyl ethers, polyvinyl esters, polyvinyl halides, polyvinylpyrrolidone, polyglycolides, polysiloxanes, polyurethanes, alkyl cellulose, hydroxyalkyl celluloses, cellulose ethers, cellulose esters, nitrocelluloses, polymers of acrylic and methacrylic esters, methyl cellulose, ethyl cellulose, hydroxypropyl cellulose, hydroxypropyl methyl cellulose, hydroxybutyl methyl cellulose, cellulose acetate, cellulose propionate, cellulose acetate butyrate, cellulose acetate phthalate, carboxylethyl cellulose, cellulose triacetate, cellulose sulphate sodium salt, poly(methyl methacrylate), poly(ethyl methacrylate), poly(butylmethacrylate), poly(isobutyl methacrylate), poly(hexylmethacrylate), poly(isodecyl methacrylate), poly(lauryl methacrylate), poly(phenyl methacrylate), poly(methyl acrylate), poly(isopropyl acrylate), poly(isobutyl acrylate), poly(octadecyl acrylate), polyethylene, polypropylene, poly(ethylene glycol), poly(ethylene oxide), poly(ethylene terephthalate), poly(vinyl alcohols), polyvinyl acetate, polyvinyl chloride, polystyrene, polyhyaluronic acids, casein, gelatin, glutin, polyanhydrides, polyacrylic acid, alginate, chitosan, poly(methyl methacrylates), poly(ethyl methacrylates), poly(butylmethacrylate), poly(isobutyl methacrylate), poly(hexylmethacrylate), poly(isodecyl methacrylate), poly(lauryl methacrylate), poly(phenyl methacrylate), poly(methyl acrylate), poly(isopropyl acrylate), poly(isobutyl acrylate), and poly(octadecyl acrylate), poly(lactide-glycolide), copolyoxalates, polycaprolactones, polyesteramides, polyorthoesters, polyhydroxybutyric acid, polyanhydrides, poly(styrene-b-isobutylene-b-styrene) (SIBS) block copolymer, ethylene vinyl acetate, poly(meth)acrylic acid, polymers of lactic acid and glycolic acid, polyanhydrides, poly(ortho)esters, polyurethanes, poly(butic acid), poly(valeric acid), and poly(lactide-cocaprolactone), and natural polymers such as alginate and other polysaccharides including dextran and cellulose, collagen, albumin and other hydrophilic proteins, zein and other prolamines and hydrophobic proteins, copolymers and mixtures thereof, and chemical derivatives thereof including substitutions and/or additions of chemical groups, for example, alkyl, alkylene, hydroxylations, oxidations, and other modifications routinely made by those skilled in the art.

(227) Trapped Charge

(228) Another issue that relates to ISFET threshold voltage stability and/or predictability involves trapped charge that may accumulate (especially) on metal layers of CMOS-fabricated devices as a result of various processing activities during or following array fabrication (e.g., back-end-of-line processing such as plasma metal etching, wafer cleaning, dicing, packaging, handling, etc.). In particular, with reference to FIG. 11A, trapped charge may in some instances accumulate on one or more of the various conductors 304, 306, 308, 312, 316, 320, 326, 338, and 164 constituting the ISFETs floating gate structure 170. This phenomenon also is referred to in the relevant literature as the antenna effect.

(229) One opportunity for trapped charge to accumulate includes plasma etching of the topmost metal layer 304. Other opportunities for charge to accumulate on one or more conductors of the floating gate structure or other portions of the FETs includes wafer dicing, during which the abrasive process of a dicing saw cutting through a wafer generates static electricity, and/or various post-processing wafer handling/packaging steps, such as die-to-package wire bonding, where in some cases automated machinery that handles/transports wafers may be sources of electrostatic discharge (ESD) to conductors of the floating gate structure. If there is no connection to the silicon substrate (or other semi-conductor substrate) to provide an electrical path to bleed off such charge accumulation, charge may build up to the point of causing undesirable changes or damage to the gate oxide 165 (e.g., charge injection into the oxide, or low-level oxide breakdown to the underlying substrate). Trapped charge in the gate oxide or at the gate oxide-semiconductor interface in turn can cause undesirable and/or unpredictable variations in ISFET operation and performance, such as fluctuations in threshold voltage.

(230) In view of the foregoing, other inventive embodiments of the present disclosure are directed to methods and apparatus for improving ISFET performance by reducing trapped charge or mitigating the antenna effect. In one embodiment, trapped charge may be reduced after a sensor array has been fabricated, while in other embodiments the fabrication process itself may be modified to reduce trapped charge that could be induced by some conventional process steps. In yet other embodiments, both during fabrication and post fabrication techniques may be employed in combination to reduce trapped charge and thereby improve ISFET performance.

(231) With respect to alterations to the fabrication process itself to reduce trapped charge, in one embodiment the thickness of the gate oxide 165 shown in FIG. 11A may be particularly selected so as to facilitate bleeding of accumulated charge to the substrate; in particular, a thinner gate oxide may allow a sufficient amount of built-up charge to pass through the gate oxide to the substrate below without becoming trapped. In another embodiment based on this concept, a pixel may be designed to include an additional sacrificial device, i.e., another transistor having a thinner gate oxide than the gate oxide 165 of the ISFET. The floating gate structure of the ISFET may then be coupled to the gate of the sacrificial device such that it serves as a charge bleed-off transistor. Of course, it should be appreciated that some trade-offs for including such a sacrificial device include an increase in pixel size and complexity.

(232) In another embodiment, the topmost metal layer 304 of the ISFETs floating gate structure 170 shown in FIG. 11A may be capped with a dielectric prior to plasma etching to mitigate trapped charge. As discussed above, charge accumulated on the floating gate structure may in some cases be coupled from the plasma being used for metal etching. Typically, a photoresist is applied over the metal to be etched and then patterned based on the desired geometry for the underlying metal. In one exemplary implementation, a capping dielectric layer (e.g., an oxide) may be deposited over the metal to be etched, prior to the application of the photoresist, to provide an additional barrier on the metal surface against charge from the plasma etching process. In one aspect, the capping dielectric layer may remain behind and form a portion of the passivation layer 172.

(233) In yet another embodiment, the metal etch process for the topmost metal layer 304 may be modified to include wet chemistry or ion-beam milling rather than plasma etching. For example, the metal layer 304 could be etched using an aqueous chemistry selective to the underlying dielectric (e.g., see website for Transene relating to aluminum, which is hereby incorporated herein by reference). Another alternative approach employs ion-milling rather than plasma etching for the metal layer 304. Ion-milling is commonly used to etch materials that cannot be readily removed using conventional plasma or wet chemistries. The ion-milling process does not employ an oscillating electric field as does a plasma, so that charge build-up does not occur in the metal layer(s). Yet another metal etch alternative involves optimizing the plasma conditions so as to reduce the etch rate (i.e. less power density).

(234) In yet another embodiment, architecture changes may be made to the metal layer to facilitate complete electrical isolation during definition of the floating gate. In one aspect, designing the metal stack-up so that the large area ISFET floating gate is not connected to anything during its final definition may require a subsequent metal layer serving as a jumper to realize the electrical connection to the floating gate of the transistor. This jumper connection scheme prevents charge flow from the large floating gate to the transistor. This method may be implemented as follows (M=metal layer): i) M1 contacting Poly gate electrode; ii) M2 contacting M1; iii) M3 defines floating gate and separately connects to M2 with isolated island; iv) M4 jumper, having very small area being etched over the isolated islands and connections to floating gate M3, connects the M3 floating gate to the M1/M2/M3 stack connected to the Poly gate immediately over the transistor active area; and v) M3 to M4 interlayer dielectric is removed only over the floating gate so as to expose the bare M3 floating gate. In the method outlined immediately above, step v) need not be done, as the ISFET architecture according to some embodiments discussed above leaves the M4 passivation in place over the M4 floating gate. In one aspect, removal may nonetheless improve ISFET performance in other ways (i.e. sensitivity). In any case, the final sensitive passivation layer may be a thin sputter-deposited ion-sensitive metal-oxide layer. It should be appreciated that the over-layer jumpered architecture discussed above may be implemented in the standard CMOS fabrication flow to allow any of the first three metal layers to be used as the floating gates (i.e. M1, M2 or M3).

(235) With respect to post-fabrication processes to reduce trapped charge, in one embodiment a forming gas anneal may be employed as a post-fabrication process to mitigate potentially adverse effects of trapped charge. In a forming gas anneal, CMOS-fabricated ISFET devices are heated in a hydrogen and nitrogen gas mixture. The hydrogen gas in the mixture diffuses into the gate oxide 165 and neutralizes certain forms of trapped charges. In one aspect, the forming gas anneal need not necessarily remove all gate oxide damage that may result from trapped charges; rather, in some cases, a partial neutralization of some trapped charge is sufficient to significantly improve ISFET performance. In exemplary annealing processes according to the present disclosure, ISFETs may be heated for approximately 30 to 60 minutes at approximately 400 to 425 degrees Celsius in a hydrogen/nitrogen mixture that includes 10% to 15% hydrogen. In one particular implementation, annealing at 425 degrees Celsius at 30 minutes in a hydrogen/nitrogen mixture that includes 10% hydrogen is observed to be particularly effective at improving ISFET performance. For aluminum CMOS processes, the temperature of the anneal should be kept at or below 450 degrees Celsius to avoid damaging the aluminum metallurgy. In another aspect of an annealing process according to the present disclosure, the forming gas anneal is performed after wafers of fabricated ISFET arrays are diced, so as to ensure that damage due to trapped charge induced by the dicing process itself, and/or other pre-dicing processing steps (e.g., plasma etching of metals) may be effectively ameliorated. In yet another aspect, the forming gas anneal may be performed after die-to-package wirebonding to similarly ameliorate damage due to trapped charge. At this point in the assembly process, a diced array chip is typically in a heat and chemical resistant ceramic package, and low-tolerance wirebonding procedures as well as heat-resistant die-to-package adhesives may be employed to withstand the annealing procedure. Thus, in one exemplary embodiment, the invention encompasses a method for manufacturing an array of FETs, each having or coupled to a floating gate having a trapped charge of zero or substantially zero comprising: fabricating a plurality of FETs in a common semiconductor substrate, each of a plurality of which is coupled to a floating gate; applying a forming gas anneal to the semiconductor prior to a dicing step; dicing the semiconductor; and applying a forming gas anneal to the semiconductor after the dicing step. Preferably, the semiconductor substrate comprises at least 100,000 FETs. Preferably, the plurality of FETs are chemFETs. The method may further comprise depositing a passivation layer on the semiconductor, depositing a polymeric, glass, ion-reactively etchable or photodefineable material layer on the passivation layer and etching the polymeric, glass ion-reactively etchable or photodefineable material to form an array of reaction chambers in the glass layer.

(236) In yet other processes for mitigating potentially adverse effects of trapped charge according to embodiments of the present disclosure, a variety of electrostatic discharge (ESD)-sensitive protocols may be adopted during any of a variety of wafer post-fabrication handling/packaging steps. For example, in one exemplary process, anti-static dicing tape may be employed to hold wafer substrates in place (e.g., during the dicing process). Also, although high-resistivity (e.g., 10 M) deionized water conventionally is employed in connection with cooling of dicing saws, according to one embodiment of the present disclosure less resistive/more conductive water may be employed for this purpose to facilitate charge conduction via the water; for example, deionized water may be treated with carbon dioxide to lower resistivity and improve conduction of charge arising from the dicing process. Furthermore, conductive and grounded die-ejection tools may be used during various wafer dicing/handling/packaging steps, again to provide effective conduction paths for charge generated during any of these steps, and thereby reduce opportunities for charge to accumulate on one or more conductors of the floating gate structure of respective ISFETs of an array.

(237) In yet another embodiment involving a post-fabrication process to reduce trapped charge, the gate oxide region of an ISFET may be irradiated with UV radiation. With reference again to FIG. 11A, in one exemplary implementation based on this embodiment, an optional hole or window 302 is included during fabrication of an ISFET array in the top metal layer 304 of each pixel of the array, proximate to the ISFET floating gate structure. This window is intended to allow UV radiation, when generated, to enter the ISFETs gate region; in particular, the various layers of the pixel 105.sub.1. as shown in FIGS. 11 and 12 A-L, are configured such that UV radiation entering the window 302 may impinge in an essentially unobstructed manner upon the area proximate to the polysilicon gate 164 and the gate oxide 165.

(238) To facilitate a UV irradiation process to reduce trapped charge, materials other than silicon nitride and silicon oxynitride generally need to be employed in the passivation layer 172 shown in FIG. 11A, as silicon nitride and silicon oxynitride significantly absorb UV radiation. In view of the foregoing, these materials need to be substituted with others that are appreciably transparent to UV radiation, examples of which include, but are not limited to, phososilicate glass (PSG) and boron-doped phososilicate glass (BPSG). PSG and BPSG, however, are not impervious to hydrogen and hydroxyl ions; accordingly, to be employed in a passivation layer of an ISFET designed for pH sensitivity, PSG and BPSG may be used together with an ion-impervious material that is also significantly transparent to UV radiation, such as aluminum oxide (Al.sub.2O.sub.3), to form the passivation layer. For example, with reference again to FIG. 11A, PSG or BPSG may be employed as a substitute for silicon nitride or silicon oxynitride in the first portion 172A of the passivation layer 172, and a thin layer (e.g., 400 to 600 Angstroms) of aluminum oxide may be employed in the second portion 172B of the passivation layer 172 (e.g., the aluminum oxide may be deposited using a post-CMOS lift-off lithography process).

(239) In another aspect of an embodiment involving UV irradiation, each ISFET of a sensor array must be appropriately biased during a UV irradiation process to facilitate reduction of trapped charge. In particular, high energy photons from the UV irradiation, impinging upon the bulk silicon region 160 in which the ISFET conducting channel is formed, create electron-hole pairs which facilitate neutralization of trapped charge in the gate oxide as current flows through the ISFETs conducting channel. To this end, an array controller, discussed further below in connection with FIG. 17, generates appropriate signals for biasing the ISFETs of the array during a UV irradiation process. In particular, with reference again to FIG. 9, each of the signals RowSel.sub.1 through RowSel.sub.n is generated so as to enable/select (i.e., turn on) all rows of the sensor array at the same time and thereby couple all of the ISFETs of the array to respective controllable current sources 106.sub.j in each column. With all pixels of each column simultaneously selected, the current from the current source 106.sub.j of a given column is shared by all pixels of the column. The column amplifiers 107A and 107B are disabled by removing the bias voltage VB4, and at the same time the output of the amplifier 107B, connected to the drain of each ISFET in a given column, is grounded via a switch responsive to a control signal UV. Also, the common body voltage V.sub.BODY for all ISFETs of the array is coupled to electrical ground (i.e., V.sub.BODY=0 Volts) (as discussed above, during normal operation of the array, the body bias voltage V.sub.BODY is coupled to the highest voltage potential available to the array, e.g., VDDA). In one exemplary procedure, the bias voltage VB1 for all of the controllable current sources 106.sub.j is set such that each pixel's ISFET conducts approximately 1 A of current. With the ISFET array thusly biased, the array then is irradiated with a sufficient dose of UV radiation (e.g., from an EPROM eraser generating approximately 20 milliWatts/cm.sup.2 of radiation at a distance of approximately one inch from the array for approximately 1 hour). After irradiation, the array may be allowed to rest and stabilize over several hours before use for measurements of chemical properties such as ion concentration.

(240) Utilizing at least one of the above-described techniques for reducing trapped charge, we have been able to fabricate FETs floating gates having a trapped charge of zero or substantially zero. Thus, in some embodiments, an aspect of the invention encompasses a floating gate having a surface area of about 4 m.sup.2 to about 50 m.sup.2 having baseline threshold voltage and preferably a trapped charge of zero or substantially zero. Preferably the FETs are chemFETs. The trapped charge should be kept to a level that does not cause appreciable variations from FET to FET across the array, as that would limit the dynamic range of the devices, consistency of measurements, and otherwise adversely affect performance.

(241) Array and Chip Design

(242) FIG. 13 illustrates a block diagram of an exemplary CMOS IC chip implementation of an ISFET sensor array 100 based on the column and pixel designs discussed above in connection with FIGS. 9-12, according to one embodiment of the present disclosure. In one aspect of this embodiment, the array 100 includes 512 columns 102.sub.1 through 102.sub.512 with corresponding column bias/readout circuitry 110.sub.1 through 110.sub.512 (one for each column, as shown in FIG. 9), wherein each column includes 512 geometrically square pixels 105.sub.1 through 105.sub.512, each having a size of approximately 9 micrometers by 9 micrometers (i.e., the array is 512 columns by 512 rows). In another aspect, the entire array (including pixels together with associated row and column select circuitry and column bias/readout circuitry) may be fabricated on a semiconductor die as an application specific integrated circuit (ASIC) having dimensions of approximately 7 millimeters by 7 millimeters. While an array of 512 by 512 pixels is shown in the embodiment of FIG. 13, it should be appreciated that arrays may be implemented with different numbers of rows and columns and different pixel sizes according to other embodiments, as discussed further below in connection with FIGS. 19-23.

(243) Also, as discussed above, it should be appreciated that arrays according to various embodiments of the present invention may be fabricated according to conventional CMOS fabrications techniques, as well as modified CMOS fabrication techniques (e.g., to facilitate realization of various functional aspects of the chemFET arrays discussed herein, such as additional deposition of passivation materials, process steps to mitigate trapped charge, etc.) and other semiconductor fabrication techniques beyond those conventionally employed in CMOS fabrication. Additionally, various lithography techniques may be employed as part of an array fabrication process. For example, in one exemplary implementation, a lithography technique may be employed in which appropriately designed blocks are stitched together by overlapping the edges of a step and repeat lithography exposures on a wafer substrate by approximately 0.2 micrometers. In a single exposure, the maximum die size typically is approximately 21 millimeters by 21 millimeters. By selectively exposing different blocks (sides, top & bottoms, core, etc.) very large chips can be defined on a wafer (up to a maximum, in the extreme, of one chip per wafer, commonly referred to as wafer scale integration).

(244) In one aspect of the array 100 shown in FIG. 13, the first and last two columns 102.sub.1, 102.sub.2, 102.sub.511 and 102.sub.512, as well as the first two pixels 105.sub.1 and 105.sub.2 and the last two pixels 105.sub.511 and 105.sub.512 of each of the columns 102.sub.3 through 102.sub.510 (e.g., two rows and columns of pixels around a perimeter of the array) may be configured as reference or dummy pixels 103. With reference to FIG. 11A, for the dummy pixels of an array, the topmost metal layer 304 of each dummy pixel's ISFET (coupled ultimately to the ISFETs polysilicon gate 164) is tied to the same metal layer of other dummy pixels and is made accessible as a terminal of the chip, which in turn may be coupled to a reference voltage VREF. As discussed above in connection with FIG. 9, the reference voltage VREF also may be applied to the bias/readout circuitry of respective columns of the array. In some exemplary implementations discussed further below, preliminary test/evaluation data may be acquired from the array based on applying the reference voltage VREF and selecting and reading out dummy pixels, and/or reading out columns based on the direct application of VREF to respective column buffers (e.g., via the CAL signal), to facilitate offset determination (e.g., pixel-to-pixel and column-to-column variances) and array calibration.

(245) In yet another implementation of an array similar to that shown in FIG. 13, rather than reserving the first and last two columns of 512 columns and the first and last two pixels of each column of 512 pixels as reference pixels, the array may be fabricated to include an additional two rows/columns of reference pixels surrounding a perimeter of a 512 by 512 region of active pixels, such that the total size of the array in terms of actual pixels is 516 by 516 pixels. As arrays of various sizes and configurations are contemplated by the present disclosure, it should be appreciated that the foregoing concept may be applied to any of the other array embodiments discussed herein. For purposes of the discussion immediately below regarding the exemplary array 100 shown in FIG. 13, a total pixel count for the array of 512 by 512 pixels is considered.

(246) In FIG. 13, various power supply and bias voltages required for array operation (as discussed above in connection with FIG. 9) are provided to the array via electrical connections (e.g., pins, metal pads) and labeled for simplicity in block 195 as supply and bias connections. The array 100 of FIG. 13 also includes a row select shift register 192, two sets of column select shift registers 194.sub.1,2 and two output drivers 198.sub.1 and 198.sub.2 to provide two parallel array output signals, Vout1 and Vout2, representing sensor measurements (i.e., collections of individual output signals generated by respective ISFETs of the array). The various power supply and bias voltages, control signals for the row and column shift registers, and control signals for the column bias/readout circuitry shown in FIG. 13 are provided by an array controller, as discussed further below in connection with FIG. 17, which also reads the array output signals Vout1 and Vout2 (and other optional status/diagnostic signals) from the array 100. In another aspect of the array embodiment shown in FIG. 13, configuring the array such that multiple regions (e.g., multiple columns) of the array may be read at the same time via multiple parallel array output signals (e.g., Vout1 and Vout2) facilitates increased data acquisition rates, as discussed further below in connection with FIGS. 17 and 18. While FIG. 13 illustrates an array having two column select registers and parallel array output signals Vout1 and Vout2 to acquire data simultaneously from two columns at a time, it should be appreciated that, in other embodiments, arrays according to the present disclosure may be configured to have only one measurement signal output, or more than two measurement signal outputs; in particular, as discussed further below in connection with FIGS. 19-23, more dense arrays according to other inventive embodiments may be configured to have four our more parallel measurement signal outputs and simultaneously enable different regions of the array to provide data via the four or more outputs.

(247) FIG. 14 illustrates the row select shift register 192, FIG. 15 illustrates one of the column select shift registers 194.sub.2 and FIG. 16 illustrates one of the output drivers 198.sub.2 of the array 100 shown in FIG. 13, according to one exemplary implementation. As shown in FIGS. 14 and 15, the row and column select shift registers are implemented as a series of D-type flip-flops coupled to a digital circuitry positive supply voltage VDDD and a digital supply ground VSSD. In the row and column shift registers, a data signal is applied to a D-input of first flip-flop in each series and a clock signal is applied simultaneously to a clock input of all of the flip-flops in the series. For each flip-flop, a Q output reproduces the state of the D-input upon a transition (e.g., falling edge) of the clock signal. With reference to FIG. 14, the row select shift register 192 includes 512 D-type flip-flops, in which a first flip-flop 193 receives a vertical data signal DV and all flip-flops receive a vertical clock signal CV. A Q output of the first flip-flop 193 provides the first row select signal RowSel.sub.1 and is coupled to the D-input of the next flip-flop in the series. The Q outputs of successive flip-flops are coupled to the D-inputs of the next flip-flop in the series and provide the row select signals RowSel.sub.2 through RowSel.sub.512 with successive falling edge transitions of the vertical clock signal CV, as discussed further below in connection with FIG. 18. The last row select signal RowSel.sub.512 also may be taken as an optional output of the array 100 as the signal LSTV (Last STage Vertical), which provides an indication (e.g., for diagnostic purposes) that the last row of the array has been selected. While not shown explicitly in FIG. 14, each of the row select signals RowSel.sub.1 through RowSel.sub.512 is applied to a corresponding inverter, the output of which is used to enable a given pixel in each column (as illustrated in FIG. 9 by the signals RowSel.sub.1 through RowSel.sub.n).

(248) Regarding the column select shift registers 194.sub.1 and 194.sub.2, these are implemented in a manner similar to that of the row select shift registers, with each column select shift register comprising 256 series-connected flip-flops and responsible for enabling readout from either the odd columns of the array or the even columns of the array. For example, FIG. 15 illustrates the column select shift register 194.sub.2, which is configured to enable readout from all of the even numbered columns of the array in succession via the column select signals ColSel.sub.2, ColSel.sub.4, . . . COLSEL.sub.512, whereas another column select shift register 194.sub.1 is configured to enable readout from all of the odd numbered columns of the array in succession (via column select signals ColSel.sub.1, ColSel.sub.3, . . . ColSel.sub.511). Both column select shift registers are controlled simultaneously by the horizontal data signal DH and the horizontal clock signal CH to provide the respective column select signals, as discussed further below in connection with FIG. 18. As shown in FIG. 15, the last column select signal ColSel.sub.512 also may be taken as an optional output of the array 100 as the signal LSTH (Last STage Horizontal), which provides an indication (e.g., for diagnostic purposes) that the last column of the array has been selected.

(249) With reference again for the moment to FIG. 7, an implementation for array row and column selection based on shift registers, as discussed above in connection with FIGS. 13-15, is a significant improvement to the row and column decoder approach employed in various prior art ISFET array designs, including the design of Milgrew et al. shown in FIG. 7. In particular, regarding the row decoder 92 and the column decoder 94 shown in FIG. 7, the complexity of implementing these components in an integrated circuit array design increases dramatically as the size of the array is increased, as additional inputs to both decoders are required. For example, an array having 512 rows and columns as discussed above in connection with FIG. 13 would require nine inputs (2.sup.9=512) per row and column decoder if such a scheme were employed for row and column selection; similarly, arrays having 7400 rows and 7400 columns, as discussed below in connection with other embodiments, would require 13 inputs (2.sup.13=8192) per row and column decoder. In contrast, the row and column select shift registers shown in FIGS. 14 and 15 require no additional input signals as array size is increased, but rather additional D-type flip-flops (which are routinely implemented in a CMOS process). Thus, the shift register implementations shown in FIGS. 14 and 15 provide an easily scalable solution to array row and column selection.

(250) In the embodiment of FIG. 13, the odd column select shift register 194.sub.1 provides odd column select signals to an odd output driver 198.sub.1 and the even column select shift register 194.sub.2 provides even column select signals to an even output driver 198.sub.2. Both output drivers are configured similarly, and an example of the even output driver 198.sub.2 is shown in FIG. 16. In particular, FIG. 16 shows that respective even column output signals V.sub.COL2, V.sub.COL4, . . . V.sub.COL512 (refer to FIG. 9 for the generic column signal output V.sub.COLj) are applied to corresponding switches 191.sub.2, 191.sub.4, . . . 191.sub.512, responsive to the even column select signals ColSel.sub.2, ColSel.sub.4, . . . ColSel.sub.512 provided by the column select register 194.sub.2, to successively couple the even column output signals to the input of a buffer amplifier 199 (BUF) via a bus 175. In FIG. 16, the buffer amplifier 199 receives power from an output buffer positive supply voltage VDDO and an output buffer supply ground VSSO, and is responsive to an output buffer bias voltage VBO0 to set a corresponding bias current for the buffer output. Given the high impedance input of the buffer amplifier 199, a current sink 197 responsive to a bias voltage VB3 is coupled to the bus 175 to provide an appropriate drive current (e.g., on the order of approximately 100 A) for the output of the column output buffer (see the buffer amplifier 111j of FIG. 9) of a selected column. The buffer amplifier 199 provides the output signal Vout2 based on the selected even column of the array; at the same time, with reference to FIG. 13, a corresponding buffer amplifier of the odd output driver 198.sub.1 provides the output signal Vout1 based on a selected odd column of the array.

(251) In one exemplary implementation, the switches of both the even and odd output drivers 198.sub.1 and 198.sub.2 (e.g., the switches 191.sub.2, 191.sub.4, . . . 191.sub.512 shown in FIG. 16) may be implemented as CMOS-pair transmission gates (including an n-channel MOSFET and a p-channel MOSFET; see FIG. 4), and inverters may be employed so that each column select signal and its complement may be applied to a given transmission gate switch 191 to enable switching. Each switch 191 has a series resistance when enabled or on to couple a corresponding column output signal to the bus 175; likewise, each switch adds a capacitance to the bus 175 when the switch is off. A larger switch reduces series resistance and allows a higher drive current for the bus 175, which generally allows the bus 175 to settle more quickly; on the other hand, a larger switch increases capacitance of the bus 175 when the switch is off, which in turn increases the settling time of the bus 175. Hence, there is a trade-off between switch series resistance and capacitance in connection with switch size.

(252) The ability of the bus 175 to settle quickly following enabling of successive switches in turn facilitates rapid data acquisition from the array. To this end, in some embodiments the switches 191 of the output drivers 198.sub.1 and 198.sub.2 are particularly configured to significantly reduce the settling time of the bus 175. Both the n-channel and the p-channel MOSFETs of a given switch add to the capacitance of the bus 175; however, n-channel MOSFETs generally have better frequency response and current drive capabilities than their p-channel counterparts. In view of the foregoing, some of the superior characteristics of n-channel MOSFETs may be exploited to improve settling time of the bus 175 by implementing asymmetric switches in which respective sizes for the n-channel MOSFET and p-channel MOSFET of a given switch are different.

(253) For example, in one embodiment, with reference to FIG. 16, the current sink 197 may be configured such that the bus 175 is normally pulled down when all switches 191.sub.2, 191.sub.4, . . . 191.sub.512 are open or off (not conducting). Given a somewhat limited expected signal dynamic range for the column output signals based on ISFET measurements, when a given switch is enabled or on (conducting), in many instances most of the conduction is done by the n-channel MOSFET of the CMOS-pair constituting the switch. Accordingly, in one aspect of this embodiment, the n-channel MOSFET and the p-channel MOSFET of each switch 191 are sized differently; namely, in one exemplary implementation, the n-channel MOSFET is sized to be significantly larger than the p-channel MOSFET. More specifically, considering equally-sized n-channel and p-channel MOSFETs as a point of reference, in one implementation the n-channel MOSFET may be increased to be about 2 to 2.5 times larger, and the p-channel MOSFET may be decreased in size to be about 8 to 10 times smaller, such that the n-channel MOSFET is approximately 20 times larger than the p-channel MOSFET. Due to the significant decrease in size of the p-channel MOSFET and the relatively modest increase in size of the n-channel MOSFET, the overall capacitance of the switch in the off state is notably reduced, and there is a corresponding notable reduction in capacitance for the bus 175; at the same time, due to the larger n-channel MOSFET, there is a significant increase in current drive capability, frequency response and transconductance of the switch, which in turn results in a significant reduction in settling time of the bus 175.

(254) While the example above describes asymmetric switches 191 for the output drivers 198.sub.1 and 198.sub.2 in which the n-channel MOSFET is larger than the p-channel MOSFET, it should be appreciated that in another embodiment, the converse may be implemented, namely, asymmetric switches in which the p-channel MOSFET is larger than the n-channel MOSFET. In one aspect of this embodiment, with reference again to FIG. 16, the current sink 197 may alternatively serve as a source of current to appropriately drive the output of the column output buffer (see the buffer amplifier 111j of FIG. 9) of a selected column, and be configured such that the bus 175 is normally pulled up when all switches 191.sub.2, 191.sub.4, . . . 191.sub.512 are open or off (not conducting). In this situation, most of the switch conduction may be accomplished by the p-channel MOSFET of the CMOS-pair constituting the switch. Benefits of reduced switch capacitance (and hence reduced bus capacitance) may be realized in this embodiment, although the overall beneficial effect of reduced settling time for the bus 175 may be somewhat less than that described previously above, due to the lower frequency response of p-channel MOSFETs as compared to n-channel MOSFETs. Nevertheless, asymmetric switches based on larger p-channel MOSFETs may still facilitate a notable reduction in bus settling time, and may also provide for circuit implementations in which the column output buffer amplifier (111j of FIG. 9) may be a body-tied source follower with appreciably increased gain.

(255) In yet another embodiment directed to facilitating rapid settling of the bus 175 shown in FIG. 16, it may be appreciated that fewer switches 191 coupled to the bus 175 results in a smaller bus capacitance. With this in mind, and with reference again to FIG. 13, in yet another embodiment, more than two output drivers 198.sub.1 and 198.sub.2 may be employed in the ISFET array 100 such that each output driver handles a smaller number of columns of the array. For example, rather than having all even columns handled by one driver and all odd columns handled by another driver, the array may include four column select registers 194.sub.1,2,3,4 and four corresponding output drivers 198.sub.1,2,3,4 such that each output driver handles one-fourth of the total columns of the array, rather than one-half of the columns. In such an implementation, each output driver would accordingly have half the number of switches 191 as compared with the embodiment discussed above in connection with FIG. 16, and the bus 175 of each output driver would have a corresponding lower capacitance, thereby improving bus settling time. While four output drivers are discussed for purposes of illustration in this example, it should be appreciated that the present disclosure is not limited in this respect, and virtually any number of output drivers greater than two may be employed to improve bus settling time in the scenario described above. Other array embodiments in which more than two output drivers are employed to facilitate rapid data acquisition from the array are discussed in greater detail below (e.g., in connection with FIGS. 19-23).

(256) For purposes of illustration, the bus 175 may have a capacitance in the range of approximately 5 pF to 20 pF in any of the embodiments discussed immediately above (e.g. symmetric switches, asymmetric switches, greater numbers of output drivers, etc.). Of course, it should be appreciated that the capacitance of the bus 175 is not limited to these exemplary values, and that other capacitance values are possible in different implementations of an array according to the present disclosure.

(257) In one aspect of the array design discussed above in connection with FIGS. 13-16, separate analog supply voltage connections (for VDDA, VSSA), digital supply voltage connections (for VDDD, VSSD) and output buffer supply voltage connections (for VDDO, VSSO) are provided on the array to facilitate noise isolation and reduce signal cross-talk amongst various array components, thereby increasing the signal-to-noise ratio (SNR) of the output signals Vout1 and Vout2. In one exemplary implementation, the positive supply voltages VDDA, VDDD and VDDO each may be approximately 3.3 Volts. In another aspect, these voltages respectively may be provided off chip by one or more programmable voltage sources, as discussed further below in connection with FIG. 17.

(258) FIG. 17 illustrates a block diagram of the sensor array 100 of FIG. 13 coupled to an array controller 250, according to one inventive embodiment of the present disclosure. In various exemplary implementations, the array controller 250 may be fabricated as a stand alone controller, or as one or more computer compatible cards forming part of a computer 260, as discussed above in connection with FIG. 8. In one aspect, the functions of the array controller 250 may be controlled by the computer 260 through an interface block 252 (e.g., serial interface, via USB port or PCI bus, Ethernet connection, etc.), as shown in FIG. 17. In one embodiment, all or a portion of the array controller 250 is fabricated as one or more printed circuit boards, and the array 100 is configured to plug into one of the printed circuit boards, similar to a conventional IC chip (e.g., the array 100 is configured as an ASIC that plugs into a chip socket, such as a zero-insertion-force or ZIF socket, of a printed circuit board). In one aspect of such an embodiment, an array 100 configured as an ASIC may include one or more pins/terminal connections dedicated to providing an identification code, indicated as ID in FIG. 17, that may be accessed/read by the array controller 250 and/or passed on to the computer 260. Such an identification code may represent various attributes of the array 100 (e.g., size, number of pixels, number of output signals, various operating parameters such as supply and/or bias voltages, etc.) and may be processed to determine corresponding operating modes, parameters and or signals provided by the array controller 250 to ensure appropriate operation with any of a number of different types of arrays 100. In one exemplary implementation, an array 100 configured as an ASIC may be provided with three pins dedicated to an identification code, and during the manufacturing process the ASIC may be encoded to provide one of three possible voltage states at each of these three pins (i.e., a tri-state pin coding scheme) to be read by the array controller 250, thereby providing for 27 unique array identification codes. In another aspect of this embodiment, all or portions of the array controller 250 may be implemented as a field programmable gate array (FPGA) configured to perform various array controller functions described in further detail below.

(259) Generally, the array controller 250 provides various supply voltages and bias voltages to the array 100, as well as various signals relating to row and column selection, sampling of pixel outputs and data acquisition. In particular, the array controller 250 reads one or more analog output signals (e.g., Vout1 and Vout2) including multiplexed respective pixel voltage signals from the array 100 and then digitizes these respective pixel signals to provide measurement data to the computer 260, which in turn may store and/or process the data. In some implementations, the array controller 250 also may be configured to perform or facilitate various array calibration and diagnostic functions, and an optional array UV irradiation treatment as discussed above in connection with FIG. 11A.

(260) As illustrated in FIG. 17, the array controller 250 generally provides to the array 100 the analog supply voltage and ground (VDDA, VSSA), the digital supply voltage and ground (VDDD, VSSD), and the buffer output supply voltage and ground (VDDO, VSSO). In one exemplary implementation, each of the supply voltages VDDA, VDDD and VDDO is approximately 3.3 Volts. In another implementation, the supply voltages VDDA, VDDD and VDDO may be as low as approximately 1.8 Volts. As discussed above, in one aspect each of these power supply voltages is provided to the array 100 via separate conducting paths to facilitate noise isolation. In another aspect, these supply voltages may originate from respective power supplies/regulators, or one or more of these supply voltages may originate from a common source in a power supply 258 of the array controller 250. The power supply 258 also may provide the various bias voltages required for array operation (e.g., VB1, VB2, VB3, VB4, VBO0, V.sub.BODY) and the reference voltage VREF used for array diagnostics and calibration.

(261) In another aspect, the power supply 258 includes one or more digital-to-analog converters (DACs) that may be controlled by the computer 260 to allow any or all of the bias voltages, reference voltage, and supply voltages to be changed under software control (i.e., programmable bias settings). For example, a power supply 258 responsive to computer control (e.g., via software execution) may facilitate adjustment of one or more of the supply voltages (e.g., switching between 3.3 Volts and 1.8 Volts depending on chip type as represented by an identification code), and/or adjustment of one or more of the bias voltages VB1 and VB2 for pixel drain current, VB3 for column bus drive, VB4 for column amplifier bandwidth, and VBO0 for column output buffer current drive. In some aspects, one or more bias voltages may be adjusted to optimize settling times of signals from enabled pixels. Additionally, the common body voltage V.sub.BODY for all ISFETs of the array may be grounded during an optional post-fabrication UV irradiation treatment to reduce trapped charge, and then coupled to a higher voltage (e.g., VDDA) during diagnostic analysis, calibration, and normal operation of the array for measurement/data acquisition. Likewise, the reference voltage VREF may be varied to facilitate a variety of diagnostic and calibration functions.

(262) As also shown in FIG. 17, the reference electrode 76 which is typically employed in connection with an analyte solution to be measured by the array 100 (as discussed above in connection with FIG. 1), may be coupled to the power supply 258 to provide a reference potential for the pixel output voltages. For example, in one implementation the reference electrode 76 may be coupled to a supply ground (e.g., the analog ground VSSA) to provide a reference for the pixel output voltages based on Eq. (3) above. In other exemplary implementations, the reference electrode voltage may be set by placing a solution/sample of interest having a known pH level in proximity to the sensor array 100 and adjusting the reference electrode voltage until the array output signals Vout1 and Vout2 provide pixel voltages at a desired reference level, from which subsequent changes in pixel voltages reflect local changes in pH with respect to the known reference pH level. In general, it should be appreciated that a voltage associated with the reference electrode 76 need not necessarily be identical to the reference voltage VREF discussed above (which may be employed for a variety of array diagnostic and calibration functions), although in some implementations the reference voltage VREF provided by the power supply 258 may be used to set the voltage of the reference electrode 76.

(263) Regarding data acquisition from the array 100, in one embodiment the array controller 250 of FIG. 17 may include one or more preamplifiers 253 to further buffer the one or more output signals (e.g., Vout1 and Vout2) from the sensor array and provide selectable gain. In one aspect, the array controller 250 may include one preamplifier for each output signal (e.g., two preamplifiers for two analog output signals). In other aspects, the preamplifiers may be configured to accept input voltages from 0.0 to 1.8 Volts or 0.0 to 3.3 Volts, may have programmable/computer selectable gains (e.g., 1, 2, 5, 10 and 20) and low noise outputs (e.g., <10 nV/sqrtHz), and may provide low pass filtering (e.g., bandwidths of 5 MHz and 25 MHz). With respect to noise reduction and increasing signal-to-noise ratio, in one implementation in which the array 100 is configured as an ASIC placed in a chip socket of a printed circuit board containing all or a portion of the array controller 250, filtering capacitors may be employed in proximity to the chip socket (e.g., the underside of a ZIF socket) to facilitate noise reduction. In yet another aspect, the preamplifiers may have a programmable/computer selectable offset for input and/or output voltage signals to set a nominal level for either to a desired range.

(264) The array controller 250 of FIG. 17 also comprises one or more analog-to-digital converters 254 (ADCs) to convert the sensor array output signals Vout1 and Vout2 to digital outputs (e.g., 10-bit or 12-bit) so as to provide data to the computer 260. In one aspect, one ADC may be employed for each analog output of the sensor array, and each ADC may be coupled to the output of a corresponding preamplifier (if preamplifiers are employed in a given implementation). In another aspect, the ADC(s) may have a computer-selectable input range (e.g., 50 mV, 200 mV, 500 mV, 1 V) to facilitate compatibility with different ranges of array output signals and/or preamplifier parameters. In yet other aspects, the bandwidth of the ADC(s) may be greater than 60 MHz, and the data acquisition/conversion rate greater than 25 MHz (e.g., as high as 100 MHz or greater).

(265) In the embodiment of FIG. 17, ADC acquisition timing and array row and column selection may be controlled by a timing generator 256. In particular, the timing generator provides the digital vertical data and clock signals (DV, CV) to control row selection, the digital horizontal data and clock signals (DH, CH) to control column selection, and the column sample and hold signal COL SH to sample respective pixel voltages for an enabled row, as discussed above in connection with FIG. 9. The timing generator 256 also provides a sampling clock signal CS to the ADC(s) 254 so as to appropriately sample and digitize consecutive pixel values in the data stream of a given array analog output signal (e.g., Vout1 and Vout2), as discussed further below in connection with FIG. 18. In some implementations, the timing generator 256 may be implemented by a microprocessor executing code and configured as a multi-channel digital pattern generator to provide appropriately timed control signals. In one exemplary implementation, the timing generator 256 may be implemented as a field-programmable gate array (FPGA).

(266) FIG. 18 illustrates an exemplary timing diagram for various array control signals, as provided by the timing generator 256, to acquire pixel data from the sensor array 100. For purposes of the following discussion, a frame is defined as a data set that includes a value (e.g., pixel output signal or voltage V.sub.S) for each pixel in the array, and a frame rate is defined as the rate at which successive frames may be acquired from the array. Thus, the frame rate corresponds essentially to a pixel sampling rate for each pixel of the array, as data from any given pixel is obtained at the frame rate.

(267) In the example of FIG. 18, an exemplary frame rate of 20 frames/sec is chosen to illustrate operation of the array (i.e., row and column selection and signal acquisition); however, it should be appreciated that arrays and array controllers according to the present disclosure are not limited in this respect, as different frame rates, including lower frame rates (e.g., 1 to 10 frames/second) or higher frame rates (e.g., 25, 30, 40, 50, 60, 70 to 100 frames/sec., etc.), with arrays having the same or higher numbers of pixels, are possible. In some exemplary applications, a data set may be acquired that includes many frames over several seconds to conduct an experiment on a given analyte or analytes. Several such experiments may be performed in succession, in some cases with pauses in between to allow for data transfer/processing and/or washing of the sensor array ASIC and reagent preparation for a subsequent experiment.

(268) For example, with respect to the method for detecting nucleotide incorporation, appropriate frame rates may be chosen to sufficiently sample the ISFET's output signal. In some exemplary implementations, a hydrogen ion signal may have a full-width at half-maximum (FWHM) on the order of approximately 1 second to approximately 2.5 seconds, depending on the number of nucleotide incorporation events. Given these exemplary values, a frame rate (or pixel sampling rate) of 20 Hz is sufficient to reliably resolve the signals in a given pixel's output signal. Again, the frame rates given in this example are provided primarily for purposes of illustration, and different frame rates may be involved in other implementations.

(269) In one implementation, the array controller 250 controls the array 100 to enable rows successively, one at a time. For example, with reference again for the moment to FIG. 9, a first row of pixels is enabled via the row select signal RowSel.sub.1. The enabled pixels are allowed to settle for some time period, after which the COL SH signal is asserted briefly to close the sample/hold switch in each column and store on the column's sample/hold capacitor Csh the voltage value output by the first pixel in the column. This voltage is then available as the column output voltage V.sub.COLj applied to one of the two (odd and even column) array output drivers 198.sub.1 and 198.sub.2 (e.g., see FIG. 16). The COL SH signal is then de-asserted, thereby opening the sample/hold switches in each column and decoupling the column output buffer 111j from the column amplifiers 107A and 107B. Shortly thereafter, the second row of pixels is enabled via the row select signal RowSel.sub.2. During the time period in which the second row of pixels is allowed to settle, the column select signals are generated two at a time (one odd and one even; odd column select signals are applied in succession to the odd output driver, even column select signals are applied in succession to the even output driver) to read the column output voltages associated with the first row. Thus, while a given row in the array is enabled and settling, the previous row is being read out, two columns at a time. By staggering row selection and sampling/readout (e.g., via different vertical and horizontal clock signals and column sample/hold), and by reading multiple columns at a time for a given row, a frame of data may be acquired from the array in a significantly streamlined manner.

(270) FIG. 18 illustrates the timing details of the foregoing process for an exemplary frame rate of 20 frames/sec. Given this frame rate and 512 rows in the array, each row must be read out in approximately 98 microseconds, as indicated by the vertical delineations in FIG. 18. Accordingly, the vertical clock signal CV has a period of 98 microseconds (i.e., a clock frequency of over 10 kHz), with a new row being enabled on a trailing edge (negative transition) of the CV signal. The left side of FIG. 18 reflects the beginning of a new frame cycle, at which point the vertical data signal DV is asserted before a first trailing edge of the CV signal and de-asserted before the next trailing edge of the CV signal (for data acquisition from successive frames, the vertical data signal is reasserted again only after row 512 is enabled). Also, immediately before each trailing edge of the CV signal (i.e., new row enabled), the COL SH signal is asserted for 2 microseconds, leaving approximately 50 nanoseconds before the trailing edge of the CV signal.

(271) In FIG. 18, the first occurrence of the COL SH signal is actually sampling the pixel values of row 512 of the array. Thus, upon the first trailing edge of the CV signal, the first row is enabled and allowed to settle (for approximately 96 microseconds) until the second occurrence of the COL SH signal. During this settling time for the first row, the pixel values of row 512 are read out via the column select signals. Because two column select signals are generated simultaneously to read 512 columns, the horizontal clock signal CH must generate 256 cycles within this period, each trailing edge of the CH signal generating one odd and one even column select signal. As shown in FIG. 18, the first trailing edge of the CH signal in a given row is timed to occur two microseconds after the selection of the row (after deactivation of the COL SH signal) to allow for settling of the voltage values stored on the sample/hold capacitors C.sub.sh and provided by the column output buffers. It should be appreciated however that, in other implementations (e.g., as discussed below in connection with FIG. 18A), the time period between the first trailing edge of the CH signal and a trailing edge (i.e., deactivation) of the COL SH signal may be significantly less than two microseconds, and in some cases as small as just over 50 nanoseconds. Also for each row, the horizontal data signal DH is asserted before the first trailing edge of the CH signal and de-asserted before the next trailing edge of the CH signal. The last two columns (e.g., 511 and 512) are selected before the occurrence of the COL SH signal which, as discussed above, occurs approximately two microseconds before the next row is enabled. Thus, 512 columns are read, two at a time, within a time period of approximately 94 microseconds (i.e., 98 microseconds per row, minus two microseconds at the beginning and end of each row). This results in a data rate for each of the array output signals Vout1 and Vout2 of approximately 2.7 MHz.

(272) FIG. 18A illustrates another timing diagram of a data acquisition process from an array 100 that is slightly modified from the timing diagram of FIG. 18. As discussed above in connection with FIG. 13, in some implementations an array similar to that shown in FIG. 13 may be configured to include a region of 512 by 512 active pixels that are surrounded by a perimeter of reference pixels (i.e., the first and last two rows and columns of the array), resulting in an array having a total pixel count of 516 by 516 pixels. Accordingly, given the exemplary frame rate of 20 frames/sec and 516 rows in the array, each row must be read out in approximately 97 microseconds, as indicated by the vertical delineations in FIG. 18A. Accordingly, the vertical clock signal CV has a slightly smaller period of 97 microseconds. Because two column select signals are generated simultaneously to read 516 columns, the horizontal clock signal CH must generate 258 cycles within this period, as opposed to the 256 cycles referenced in connection with FIG. 18. Accordingly, in one aspect illustrated in FIG. 18A, the first trailing edge of the CH signal in a given row is timed to occur just over 50 nanoseconds from the trailing edge (i.e., deactivation) of the COL SH signal, so as to squeeze additional horizontal clock cycles into a slightly smaller period of the vertical clock signal CV. As in FIG. 18, the horizontal data signal DH is asserted before the first trailing edge of the CH signal, and as such also occurs slightly earlier in the timing diagram of FIG. 18A as compared to FIG. 18. The last two columns (i.e., columns 515 and 516, labeled as Ref-3,4 in FIG. 18A) are selected before the occurrence of the COL SH signal which, as discussed above, occurs approximately two microseconds before the next row is enabled. Thus, 516 columns are read, two at a time, within a time period of approximately 95 microseconds (i.e., 97 microseconds per row, minus two microseconds at the end of each row and negligible time at the beginning of each row). This results in essentially the same data rate for each of the array output signals Vout1 and Vout2 provided by the timing diagram of FIG. 18, namely, approximately 2.7 MHz.

(273) As discussed above in connection with FIG. 17, the timing generator 256 also generates the sampling clock signal CS to the ADC(s) 254 so as to appropriately sample and digitize consecutive pixel values in the data stream of a given array output signal. In one aspect, the sampling clock signal CS provides for sampling a given pixel value in the data stream at least once. Although the sampling clock signal CS is not shown in the timing diagrams of FIGS. 18 and 18A, it may be appreciated that in exemplary implementations the signal CS may essentially track the timing of the horizontal clock signal CH; in particular, the sampling clock signal CS may be coordinated with the horizontal clock signal CH so as to cause the ADC(s) to sample a pixel value immediately prior to a next pixel value in the data stream being enabled by CH, thereby allowing for as much signal settling time as possible prior to sampling a given pixel value. For example, the ADC(s) may be configured to sample an input pixel value upon a positive transition of CS, and respective positive transitions of CS may be timed by the timing generator 256 to occur immediately prior to, or in some cases essentially coincident with, respective negative transitions of CH, so as to sample a given pixel just prior to the next pixel in the data stream being enabled. In another exemplary implementation, the ADC(s) 254 may be controlled by the timing generator 256 via the sampling clock signal CS to sample the output signals Vout1 and Vout2 at a significantly higher rate to provide multiple digitized samples for each pixel measurement, which may then be averaged (e.g., the ADC data acquisition rate may be approximately 100 MHz to sample the 2.7 MHz array output signals, thereby providing as many as approximately 35-40 samples per pixel measurement).

(274) In one embodiment, once pixel values are sampled and digitized by the ADC(s) 254, the computer 260 may be programmed to process pixel data obtained from the array 100 and the array controller 250 so as to facilitate high data acquisition rates that in some cases may exceed a sufficient settling time for pixel voltages represented in a given array output signal. A flow chart illustrating an exemplary method according to one embodiment of the present invention that may be implemented by the computer 260 for processing and correction of array data acquired at high acquisition rates is illustrated in FIG. 18B. In various aspects of this embodiment, the computer 260 is programmed to first characterize a sufficient settling time for pixel voltages in a given array output signal, as well as array response at appreciably high operating frequencies, using a reference or dry input to the array (e.g., no analyte present). This characterization forms the basis for deriving correction factors that are subsequently applied to data obtained from the array at the high operating frequencies and in the presence of an analyte to be measured.

(275) Regarding pixel settling time, with reference again to FIG. 16, as discussed above a given array output signal (e.g., Vout2 in FIG. 16) includes a series of pixel voltage values resulting from the sequential operation of the column select switches 191 to apply respective column voltages V.sub.COLi via the bus 175 to the buffer amplifier 199 (the respective column voltages V.sub.COLi in turn represent buffered versions of ISFET source voltages V.sub.Sj). In some implementations, it is observed that voltage changes V.sub.PIX in the array output signal between two consecutive pixel reads is characterized as an exponential process given by
V.sub.PIX(t)=A(1e.sup.t/),(PP)
where A is the difference (V.sub.COLjV.sub.COLj-1) between two pixel voltage values and k is a time constant associated with a capacitance of the bus 175. FIGS. 18C and 18D illustrate exemplary pixel voltages in a given array output signal Vout (e.g., one of Vout1 and Vout2) showing pixel-to-pixel transitions in the output signal as a function of time, plotted against exemplary sampling clock signals CS. In FIG. 18C, the sampling clock signal CS has a period 524, and an ADC controlled by CS samples a pixel voltage upon a positive transition of CS (as discussed above, in one implementation CS and CH have essentially a same period). FIG. 18C indicates two samples 525A and 525B, between which an exponential voltage transition 522 corresponding to V.sub.PIX (t), between a voltage difference A, may be readily observed.

(276) For purposes of the present discussion, pixel settling time t.sub.settle is defined as the time t at which V.sub.PIX(t) attains a value that differs from it's final value by an amount that is equal to the peak noise level of the array output signal. If the peak noise level of the array output signal is denoted as n.sub.p, then the voltage at the settling time t.sub.settle is given by V.sub.PIX(t.sub.settle)=A[1(n.sub.p/A)]. Substituting in Eq. (PP) and solving for t.sub.settle yields

(277) $\begin{array}{cc}{t}_{\mathrm{settle}}=-k\ln \left(\frac{n_p}{A}\right),& \left(\mathrm{QQ}\right)\end{array}$

(278) FIG. 18D conceptually illustrates a pixel settling time t.sub.settle (reference numeral 526) for a single voltage transition 522 between two pixel voltages having a difference A, using a sampling clock signal CS having a sufficiently long period so as to allow for full settling. To provide some exemplary parameters for purposes of illustration, in one implementation a maximum value for A, representing a maximum range for pixel voltage transitions (e.g., consecutive pixels at minimum and maximum values), is on the order of approximately 250 mV. Additionally, a peak noise level n.sub.p of the array output signal is taken as approximately 100 V, and the time constant k is taken as 5 nanoseconds. These values provide an exemplary settling time t.sub.settle of approximately 40 nanoseconds. If a maximum data rate of an array output signal is taken as the inverse of the settling time t.sub.settle, a settling time of 40 nanoseconds corresponds to maximum data rate of 25 MHz. In other implementations, A may be on the order of 20 mV and the time constant k may be on the order of 15 nanoseconds, resulting in a settling time t.sub.settle of approximately 80 nanoseconds and a maximum data rate of 12.5 MHz. The values of k indicated above generally correspond to capacitances for the bus 175 in a range of approximately 5 pF to 20 pF. It should be appreciated that the foregoing values are provided primarily for purposes of illustration, and that various embodiments of the present invention are not limited to these exemplary values; in particular, arrays according to various embodiment of the present invention may have different pixel settling times t.sub.settle (e.g., in some cases less than 40 nanoseconds).

(279) As indicated above, in one embodiment pixel data may be acquired from the array at data rates that exceed those dictated by the pixel settling time. FIG. 18B illustrates a flow chart for such a method according to one inventive embodiment of the present disclosure. In the method of FIG. 18B, sufficiently slow clock frequencies initially are chosen for the signals CV, CH and CS such that the resulting data rate per array output signal is equal to or lower than the reciprocal of the pixel settling time t.sub.settle to allow for fully settled pixel voltage values from pixel to pixel in a given output signal. With these clock frequencies, as indicated in block 502 of FIG. 18B, settled pixel voltage values are then acquired for the entire array in the absence of an analyte (or in the presence of a reference analyte) to provide a first dry or reference data image for the array. In block 504 of FIG. 18B, for each pixel voltage constituting the first data image, a transition value between the pixel's final voltage and the final voltage of the immediately preceding pixel in the corresponding output signal data stream (i.e., the voltage difference A) is collected and stored. The collection of these transition values for all pixels of the array provides a first transition value data set.

(280) Subsequently, in block 506 of FIG. 18B, the clock frequencies for the signals CV, CH and CS are increased such that the resulting data rate per array output signal exceeds a rate at which pixel voltage values are fully settled (i.e., a data rate higher than the reciprocal of the settling time t.sub.settle). For purposes of the present discussion, the data rate per array output signal resulting from the selection of such increased clock frequencies for the signals CV, CH and CS is referred to as an overspeed data rate. Using the clock frequencies corresponding to the overspeed data rate, pixel voltage values are again obtained for the entire array in the absence of an analyte (or in the presence of the same reference analyte) to provide a second dry or reference data image for the array. In block 508 of FIG. 18B, a second transition value data set based on the second data image obtained at the overspeed data rate is calculated and stored, as described above for the first data image.

(281) In block 510 of FIG. 18B, a correction factor for each pixel of the array is calculated based on the values stored in the first and second transition value data sets. For example, a correction factor for each pixel may be calculated as a ratio of its transition value from the first transition value data set and its corresponding transition value from the second transition value data set (e.g., the transition value from the first data set may be divided by the transition value from the second data set, or vice versa) to provide a correction factor data set which is then stored. As noted in blocks 512 and 514 of FIG. 18B, this correction factor data set may then be employed to process pixel data obtained from the array operated at clock frequencies corresponding to the overspeed data rate, in the presence of an actual analyte to be measured; in particular, data obtained from the array at the overspeed data rate in the presence of an analyte may be multiplied or divided as appropriate by the correction factor data set (e.g., each pixel multiplied or divided by a corresponding correction factor) to obtain corrected data representative of the desired analyte property to be measured (e.g., ion concentration). It should be appreciated that once the correction factor data set is calculated and stored, it may be used repeatedly to correct multiple frames of data acquired from the array at the overspeed data rate.

(282) In addition to controlling the sensor array and ADCs, the timing generator 256 may be configured to facilitate various array calibration and diagnostic functions, as well as an optional UV irradiation treatment. To this end, the timing generator may utilize the signal LSTV indicating the selection of the last row of the array and the signal LSTH to indicate the selection of the last column of the array. The timing generator 256 also may be responsible for generating the CAL signal which applies the reference voltage VREF to the column buffer amplifiers, and generating the UV signal which grounds the drains of all ISFETs in the array during a UV irradiation process (see FIG. 9). The timing generator also may provide some control function over the power supply 258 during various calibration and diagnostic functions, or UV irradiation, to appropriately control supply or bias voltages; for example, during UV irradiation, the timing generator may control the power supply to couple the body voltage V.sub.BODY to ground while the UV signal is activated to ground the ISFET drains. With respect to array calibration and diagnostics, as well as UV irradiation, in some implementations the timing generator may receive specialized programs from the computer 260 to provide appropriate control signals. In one aspect, the computer 260 may use various data obtained from reference and/or dummy pixels of the array, as well as column information based on the application of the CAL signal and the reference voltage VREF, to determine various calibration parameters associated with a given array and/or generate specialized programs for calibration and diagnostic functions.

(283) Having discussed several aspects of an exemplary ISFET array, FIGS. 19-23 illustrate block diagrams of alternative CMOS IC chip implementations of ISFET sensor arrays having greater numbers of pixels, according to yet other inventive embodiments. In one aspect, each of the ISFET arrays discussed further below in connection with FIGS. 19-23 may be controlled by an array controller similar to that shown in FIG. 17, in some cases with minor modifications to accommodate higher numbers of pixels (e.g., additional preamplifiers 253 and analog-to-digital converters 254).

(284) FIG. 19 illustrates a block diagram of an ISFET sensor array 100A based on the column and pixel designs discussed above in connection with FIGS. 9-12 and a 0.35 micrometer CMOS fabrication process, according to one inventive embodiment. The array 100A includes 2048 columns 102.sub.1 through 102.sub.2048, wherein each column includes 2048 geometrically square pixels 105.sub.1 through 105.sub.2048, each having a size of approximately 9 micrometers by 9 micrometers. Thus, the array includes over four million pixels (>4 Mega-pixels) and, in one exemplary implementation, the complete array (ISFET pixels and associated circuitry) may be fabricated as an integrated circuit chip having dimensions of approximately 20.5 millimeters by 20.5 millimeters.

(285) In one aspect of the embodiment shown in FIG. 19, the array 100A may be configured, at least in part, as multiple groups of pixels that may be respectively controlled. For example, each column of pixels may be divided into top and bottom halves, and the collection of pixels in respective top halves of columns form a first group 4001 of rows (e.g., a top group, rows 1-1024) and the collection of pixels in respective bottom halves of columns form a second group 400.sub.2 of rows (e.g., a bottom group, rows 1025-2048). In turn, each of the first and second (e.g., top and bottom) groups of rows is associated with corresponding row select registers, column bias/readout circuitry, column select registers, and output drivers. In this manner, pixel selection and data acquisition from each of the first and second groups of rows 400.sub.1 and 400.sub.2 is substantially similar to pixel selection and data acquisition from the entire array 100 shown in FIG. 13; stated differently, in one aspect, the array 100A of FIG. 19 substantially comprises two simultaneously controlled sub-arrays of different pixel groups to provide for significantly streamlined data acquisition from higher numbers of pixels.

(286) In particular, FIG. 19 shows that row selection of the first group 400.sub.1 of rows may be controlled by a first row select register 192.sub.1, and row selection of the second group 400.sub.2 of rows may be controlled by a second row select register 192.sub.2. In one aspect, each of the row select registers 192.sub.1 and 192.sub.2 may be configured as discussed above in connection with FIG. 14 to receive vertical clock (CV) and vertical data (DV) signals and generate row select signals in response; for example the first row select register 192.sub.1 may generate the signals RowSel.sub.1 through RowSel.sub.1024 and the second row select register 192.sub.2 may generate the signals RowSel.sub.1025 through RowSel.sub.2048. In another aspect, both row select registers 192.sub.1 and 192.sub.2 may simultaneously receive common vertical clock and data signals, such that two rows of the array are enabled at any given time, one from the top group and another from the bottom group.

(287) For each of the first and second groups of rows, the array 100A of FIG. 19 further comprises column bias/readout circuitry 110.sub.1T-110.sub.2048T (for the first row group 400.sub.1) and 110.sub.1B-110.sub.2048B (for the second row group 400.sub.2), such that each column includes two instances of the bias/readout circuitry 110j shown in FIG. 9. The array 100A also comprises two column select registers 192.sub.1,2 (odd and even) and two output drivers 198.sub.1,2 (odd and even) for the second row group 400.sub.2, and two column select registers 192.sub.3,4 (odd and even) and two output drivers 198.sub.3,4 (odd and even) for the first row group 400.sub.1 (i.e., a total of four column select registers and four output drivers). The column select registers receive horizontal clock signals (CHT and CHB for the first row group and second row group, respectively) and horizontal data signals (DHT and DHB for the first row group and second row group, respectively) to control odd and even column selection. In one implementation, the CHT and CHB signals may be provided as common signals, and the DHT and DHB may be provided as common signals, to simultaneously read out four columns at a time from the array (i.e., one odd and one even column from each row group); in particular, as discussed above in connection with FIGS. 13-18, two columns may be simultaneously read for each enabled row and the corresponding pixel voltages provided as two output signals. Thus, via the enablement of two rows at any given time, and reading of two columns per row at any given time, the array 100A may provide four simultaneous output signals Vout1, Vout2, Vout3 and Vout4.

(288) In one exemplary implementation of the array 100A of FIG. 19, in which complete data frames (all pixels from both the first and second row groups 400.sub.1 and 400.sub.2) are acquired at a frame rate of 20 frames/sec, 1024 pairs of rows are successively enabled for periods of approximately 49 microseconds each. For each enabled row, 1024 pixels are read out by each column select register/output driver during approximately 45 microseconds (allowing 2 microseconds at the beginning and end of each row, as discussed above in connection with FIG. 18). Thus, in this example, each of the array output signals Vout1, Vout2, Vout3 and Vout4 has a data rate of approximately 23 MHz. Again, it should be appreciated that in other implementations, data may be acquired from the array 100A of FIG. 19 at frame rates other than 20 frames/sec (e.g., 50-100 frames/sec).

(289) Like the array 100 of FIG. 13, in yet other aspects the array 100A of FIG. 19 may include multiple rows and columns of dummy or reference pixels 103 around a perimeter of the array to facilitate preliminary test/evaluation data, offset determination an/or array calibration. Additionally, various power supply and bias voltages required for array operation (as discussed above in connection with FIG. 9) are provided to the array 100A in block 195, in a manner similar to that discussed above in connection with FIG. 13.

(290) FIG. 20 illustrates a block diagram of an ISFET sensor array 100B based on a 0.35 micrometer CMOS fabrication process and having a configuration substantially similar to the array 100A discussed above in FIG. 19, according to yet another inventive embodiment. While the array 100B also is based generally on the column and pixel designs discussed above in connection with FIGS. 9-12, the pixel size/pitch in the array 100B is smaller than that of the pixel shown in FIG. 10. In particular, with reference again to FIGS. 10 and 11, the dimension e shown in FIG. 10 is substantially reduced in the embodiment of FIG. 20, without affecting the integrity of the active pixel components disposed in the central region of the pixel, from approximately 9 micrometers to approximately 5 micrometers; similarly, the dimension f shown in FIG. 10 is reduced from approximately 7 micrometers to approximately 4 micrometers. Stated differently, some of the peripheral area of the pixel surrounding the active components is substantially reduced with respect to the dimensions given in connection with FIG. 10, without disturbing the top-view and cross-sectional layout and design of the pixel's active components as shown in FIGS. 10 and 11. A top view of such a pixel 105A is shown in FIG. 20A, in which the dimension e is 5.1 micrometers and the dimension f is 4.1 micrometers. In one aspect of this pixel design, to facilitate size reduction, fewer body connections B are included in the pixel 105A (e.g., one at each corner of the pixel) as compared to the pixel shown in FIG. 10, which includes several body connections B around the entire perimeter of the pixel.

(291) As noted in FIG. 20, the array 100B includes 1348 columns 102.sub.1 through 102.sub.1348, wherein each column includes 1152 geometrically square pixels 105A.sub.1 through 105A.sub.1152, each having a size of approximately 5 micrometers by 5 micrometers. Thus, the array includes over 1.5 million pixels (>1.5 Mega-pixels) and, in one exemplary implementation, the complete array (ISFET pixels and associated circuitry) may be fabricated as an integrated circuit chip having dimensions of approximately 9 millimeters by 9 millimeters. Like the array 100A of FIG. 19, in one aspect the array 100B of FIG. 20 is divided into two groups of rows 400.sub.1 and 400.sub.2, as discussed above in connection with FIG. 19. In one exemplary implementation, complete data frames (all pixels from both the first and second row groups 400.sub.1 and 400.sub.2) are acquired at a frame rate of 50 frames/sec, thereby requiring 576 pairs of rows to be successively enabled for periods of approximately 35 microseconds each. For each enabled row, 674 pixels are read out by each column select register/output driver during approximately 31 microseconds (allowing 2 microseconds at the beginning and end of each row, as discussed above in connection with FIG. 18). Thus, in this example, each of the array output signals Vout1, Vout2, Vout3 and Vout4 has a data rate of approximately 22 MHz. Again, it should be appreciated that in other implementations, data may be acquired from the array 100B of FIG. 20 at frame rates other than 50 frames/sec.

(292) FIG. 21 illustrates a block diagram of an ISFET sensor array 100C based on a 0.35 micrometer CMOS fabrication process and incorporating the smaller pixel size discussed above in connection with FIGS. 20 and 20A (5.1 micrometer square pixels), according to yet another embodiment. As noted in FIG. 21, the array 100C includes 4000 columns 102.sub.1 through 102.sub.4000, wherein each column includes 3600 geometrically square pixels 105A.sub.1 through 105A.sub.3600, each having a size of approximately 5 micrometers by 5 micrometers. Thus, the array includes over 14 million pixels (>14 Mega-pixels) and, in one exemplary implementation, the complete array (ISFET pixels and associated circuitry) may be fabricated as an integrated circuit chip having dimensions of approximately 22 millimeters by 22 millimeters. Like the arrays 100A and 100B of FIGS. 19 and 20, in one aspect the array 100C of FIG. 21 is divided into two groups of rows 400.sub.1 and 400.sub.2. However, unlike the arrays 100A and 100B, for each row group the array 100C includes sixteen column select registers and sixteen output drivers to simultaneously read sixteen pixels at a time in an enabled row, such that thirty-two output signals Vout1-Vout32 may be provided from the array 100C. In one exemplary implementation, complete data frames (all pixels from both the first and second row groups 400.sub.1 and 400.sub.2) may be acquired at a frame rate of 50 frames/sec, thereby requiring 1800 pairs of rows to be successively enabled for periods of approximately 11 microseconds each. For each enabled row, 250 pixels (4000/16) are read out by each column select register/output driver during approximately 7 microseconds (allowing 2 microseconds at the beginning and end of each row). Thus, in this example, each of the array output signals Vout1-Vout32 has a data rate of approximately 35 MHz. As with the previous embodiments, it should be appreciated that in other implementations, data may be acquired from the array 100C at frame rates other than 50 frames/sec.

(293) While the exemplary arrays discussed above in connection with FIGS. 13-21 are based on a 0.35 micrometer conventional CMOS fabrication process, it should be appreciated that arrays according to the present disclosure are not limited in this respect, as CMOS fabrication processes having feature sizes of less than 0.35 micrometers may be employed (e.g., 0.18 micrometer CMOS processing techniques) to fabricate such arrays. Accordingly, ISFET sensor arrays with a pixel size/pitch significantly below 5 micrometers may be fabricated, providing for significantly denser ISFET arrays. For example, FIGS. 22 and 23 illustrate respective block diagrams of ISFET sensor arrays 100D and 100E according to yet other embodiments based on a 0.18 micrometer CMOS fabrication process, in which a pixel size of 2.6 micrometers is achieved. The pixel design itself is based substantially on the pixel 105A shown in FIG. 20A, albeit on a smaller scale due to the 0.18 micrometer CMOS process.

(294) The array 100D of FIG. 22 includes 2800 columns 102.sub.1 through 102.sub.2800, wherein each column includes 2400 geometrically square pixels each having a size of approximately 2.6 micrometers by 2.6 micrometers. Thus, the array includes over 6.5 million pixels (>6.5 Mega-pixels) and, in one exemplary implementation, the complete array (ISFET pixels and associated circuitry) may be fabricated as an integrated circuit chip having dimensions of approximately 9 millimeters by 9 millimeters. Like the arrays 100A, 100B and 100C of FIGS. 19-21, in one aspect the array 100D of FIG. 22 is divided into two groups of rows 400.sub.1 and 400.sub.2. However, unlike the arrays 100A, 100B, and 100C, for each row group the array 100D includes eight column select registers and eight output drivers to simultaneously read eight pixels at a time in an enabled row, such that sixteen output signals Vout1-Vout16 may be provided from the array 100D. In one exemplary implementation, complete data frames (all pixels from both the first and second row groups 400.sub.1 and 400.sub.2) may be acquired at a frame rate of 50 frames/sec, thereby requiring 1200 pairs of rows to be successively enabled for periods of approximately 16-17 microseconds each. For each enabled row, 350 pixels (2800/8) are read out by each column select register/output driver during approximately 14 microseconds (allowing 1 to 2 microseconds at the beginning and end of each row). Thus, in this example, each of the array output signals Vout1-Vout16 has a data rate of approximately 25 MHz. As with the previous embodiments, it should be appreciated that in other implementations, data may be acquired from the array 100D at frame rates other than 50 frames/sec.

(295) The array 100E of FIG. 23 includes 7400 columns 102.sub.1 through 102.sub.7400, wherein each column includes 7400 geometrically square pixels each having a size of approximately 2.6 micrometers by 2.6 micrometers. Thus, the array includes over 54 million pixels (>54 Mega-pixels) and, in one exemplary implementation, the complete array (ISFET pixels and associated circuitry) may be fabricated as an integrated circuit chip having dimensions of approximately 21 millimeters by 21 millimeters. Like the arrays 100A-100D of FIGS. 19-22, in one aspect the array 100E of FIG. 23 is divided into two groups of rows 400.sub.1 and 400.sub.2. However, unlike the arrays 100A-100D, for each row group the array 100E includes thirty-two column select registers and thirty-two output drivers to simultaneously read thirty-two pixels at a time in an enabled row, such that sixty-four output signals Vout1-Vout64 may be provided from the array 100E. In one exemplary implementation, complete data frames (all pixels from both the first and second row groups 400.sub.1 and 400.sub.2) may be acquired at a frame rate of 100 frames/sec, thereby requiring 3700 pairs of rows to be successively enabled for periods of approximately 3 microseconds each. For each enabled row, 230 pixels (7400/32) are read out by each column select register/output driver during approximately 700 nanoseconds. Thus, in this example, each of the array output signals Vout1-Vout64 has a data rate of approximately 328 MHz. As with the previous embodiments, it should be appreciated that in other implementations, data may be acquired from the array 100D at frame rates other than 100 frames/sec.

(296) Thus, in various examples of ISFET arrays based on the inventive concepts disclosed herein, an array pitch of approximately nine (9) micrometers (e.g., a sensor surface area of less than ten micrometers by ten micrometers) allows an ISFET array including over 256,000 pixels (i.e., a 512 by 512 array), together with associated row and column select and bias/readout electronics, to be fabricated on a 7 millimeter by 7 millimeter semiconductor die, and a similar sensor array including over four million pixels (i.e., a 2048 by 2048 array, over 4 Mega-pixels) to be fabricated on a 21 millimeter by 21 millimeter die. In other examples, an array pitch of approximately 5 micrometers allows an ISFET array including approximately 1.55 Mega-pixels (i.e., a 1348 by 1152 array) and associated electronics to be fabricated on a 9 millimeter by 9 millimeter die, and an ISFET sensor array including over 14 Mega-pixels and associated electronics on a 22 millimeter by 20 millimeter die. In yet other implementations, using a CMOS fabrication process in which feature sizes of less than 0.35 micrometers are possible (e.g., 0.18 micrometer CMOS processing techniques), ISFET sensor arrays with a pixel size/pitch significantly below 5 micrometers may be fabricated (e.g., array pitch of 2.6 micrometers or pixel/sensor area of less than 8 or 9 micrometers.sup.2), providing for significantly dense ISFET arrays.

(297) In the embodiments of ISFET arrays discussed above, array pixels employ a p-channel ISFET, as discussed above in connection with FIG. 9. It should be appreciated, however, that ISFET arrays according to the present disclosure are not limited in this respect, and that in other embodiments pixel designs for ISFET arrays may be based on an n-channel ISFET. In particular, any of the arrays discussed above in connection with FIGS. 13 and 19-23 may be implemented with pixels based on n-channel ISFETs.

(298) For example, FIG. 24 illustrates the pixel design of FIG. 9 implemented with an n-channel ISFET and accompanying n-channel MOSFETs, according to another inventive embodiment of the present disclosure. More specifically, FIG. 24 illustrates one exemplary pixel 105.sub.1 of an array column (i.e., the first pixel of the column), together with column bias/readout circuitry 110j, in which the ISFET 150 (Q1) is an n-channel ISFET. Like the pixel design of FIG. 9, the pixel design of FIG. 24 includes only three components, namely, the ISFET 150 and two n-channel MOSFET switches Q2 and Q3, responsive to one of n row select signals (RowSel.sub.1 through RowSel.sub.n, logic high active). No transmission gates are required in the pixel of FIG. 24, and all devices of the pixel are of a same type, i.e., n-channel devices. Also like the pixel design of FIG. 9, only four signal lines per pixel, namely the lines 112.sub.1, 114.sub.1, 116.sub.1 and 118.sub.1 are required to operate the three components of the pixel 105.sub.1 shown in FIG. 24. In other respects, the pixel designs of FIG. 9 and FIG. 24 are similar, in that they are both configured with a constant drain current I.sub.Dj and a constant drain-to-source voltage V.sub.DSj to obtain an output signal V.sub.Sj from an enabled pixel.

(299) One of the primary differences between the n-channel ISFET pixel design of FIG. 24 and the p-channel ISFET design of FIG. 9 is the opposite direction of current flow through the pixel. To this end, in FIG. 24, the element 106.sub.j is a controllable current sink coupled to the analog circuitry supply voltage ground VSSA, and the element 108.sub.j of the bias/readout circuitry 110.sub.j is a controllable current source coupled to the analog positive supply voltage VDDA. Additionally, the body connection of the ISFET 150 is not tied to its source, but rather to the body connections of other ISFETs of the array, which in turn is coupled to the analog ground VSSA, as indicated in FIG. 24.

(300) In addition to the pixel designs shown in FIGS. 9 and 24 (based on a constant ISFET drain current and constant ISFET drain-source voltage), alternative pixel designs are contemplated for ISFET arrays, based on both p-channel ISFETs and n-channel ISFETs, according to yet other inventive embodiments of the present disclosure, as illustrated in FIGS. 25-27. As discussed below, some alternative pixel designs may require additional and/or modified signals from the array controller 250 to facilitate data acquisition. In particular, a common feature of the pixel designs shown in FIGS. 25-27 includes a sample and hold capacitor within each pixel itself, in addition to a sample and hold capacitor for each column of the array. While the alternative pixel designs of FIGS. 25-27 generally include a greater number of components than the pixel designs of FIGS. 9 and 24, the feature of a pixel sample and hold capacitor enables snapshot types of arrays, in which all pixels of an array may be enabled simultaneously to sample a complete frame and acquire signals representing measurements of one or more analytes in proximity to respective ISFETs of the array. In some applications, this may provide for higher data acquisition speeds and/or improved signal sensitivity (e.g., higher signal-to-noise ratio).

(301) FIG. 25 illustrates one such alternative design for a single pixel 105C and associated column circuitry 110j. The pixel 105C employs an n-channel ISFET and is based generally on the premise of providing a constant voltage across the ISFET Q1 based on a feedback amplifier (Q4, Q5 and Q6). In particular, transistor Q4 constitutes the feedback amplifier load, and the amplifier current is set by the bias voltage VB1 (provided by the array controller). Transistor Q5 is a common gate amplifier and transistor Q6 is a common source amplifier. Again, the purpose of feedback amplifier is to hold the voltage across the ISFET Q1 constant by adjusting the current supplied by transistor Q3. Transistor Q2 limits the maximum current the ISFET Q1 can draw (e.g., so as to prevent damage from overheating a very large array of pixels). This maximum current is set by the bias voltage VB2 (also provided by the array controller). In one aspect of the pixel design shown in FIG. 25, power to the pixel 105C may be turned off by setting the bias voltage VB2 to 0 Volts and the bias voltage VB1 to 3.3 Volts. In this manner, the power supplied to large arrays of such pixels may be modulated (turned on for a short time period and then off by the array controller) to obtain ion concentration measurements while at the same time reducing overall power consumption of the array. Modulating power to the pixels also reduces heat dissipation of the array and potential heating of the analyte solution, thereby also reducing any potentially deleterious effects from sample heating.

(302) In FIG. 25, the output of the feedback amplifier (the gate of transistor Q3) is sampled by MOS switch Q7 and stored on a pixel sample and hold capacitor Csh within the pixel itself. The switch Q7 is controlled by a pixel sample and hold signal pSH (provided to the array chip by the array controller), which is applied simultaneously to all pixels of the array so as to simultaneously store the readings of all the pixels on their respective sample and hold capacitors. In this manner, arrays based on the pixel design of FIG. 25 may be considered as snapshot arrays, in that a full frame of data is sampled at any given time, rather than sampling successive rows of the array. After each pixel value is stored on the corresponding pixel sample and hold capacitor Csh, each pixel 105C (ISFET and feedback amplifier) is free to acquire another pH reading or it can by turned off to conserve power.

(303) In FIG. 25, the pixel values stored on all of the pixel sample and hold capacitors Csh are applied to the column circuitry 110j one row at a time through source follower Q8, which is enabled via the transistor Q9 in response to a row select signal (e.g., RowSel1). In particular, after a row is selected and has settled out, the values stored in the pixel sample and hold capacitors are then in turn stored on the column sample and hold capacitors Csh2, as enabled by the column sample and hold signal COL SH, and provided as the column output signal V.sub.COLj.

(304) FIG. 26 illustrates another alternative design for a single pixel 105D and associated column circuitry 110j, according to one embodiment of the present disclosure. In this embodiment, the ISFET is shown as a p-channel device. At the start of a data acquisition cycle, CMOS switches controlled by the signals pSH (pixel sample/hold) and pRST (pixel reset) are closed (these signals are supplied by the array controller). This pulls the source of ISFET (Q1) to the voltage VRST. Subsequently, the switch controlled by the signal pRST is opened, and the source of ISFET Q1 pulls the pixel sample and hold capacitor Csh to a threshold below the level set by pH. The switch controlled by the signal pSH is then opened, and the pixel output value is coupled, via operation of a switch responsive to the row select signal RowSel1, to the column circuitry 110j to provide the column output signal V.sub.COLj. Like the pixel design in the embodiment illustrated in FIG. 25, arrays based on the pixel 105D are snapshot type arrays in that all pixels of the array may be operated simultaneously. In one aspect, this design allows a long simultaneous integration time on all pixels followed by a high-speed read out of an entire frame of data.

(305) FIG. 27 illustrates yet another alternative design for a single pixel 105E and associated column circuitry 110j, according to one embodiment of the present disclosure. In this embodiment, again the ISFET is shown as a p-channel device. At the start of a data acquisition cycle, the switches operated by the control signals p1 and pRST are briefly closed. This clears the value stored on the sampling capacitor Csh and allows a charge to be stored on ISFET (Q1). Subsequently, the switch controlled by the signal pSH is closed, allowing the charge stored on the ISFET Q1 to be stored on the pixel sample and hold capacitor Csh. The switch controlled by the signal pSH is then opened, and the pixel output value is coupled, via operation of a switch responsive to the row select signal RowSel1, to the column circuitry 110j to provide the column output signal V.sub.COLj. Gain may be provided in the pixel 105E via the ratio of the ISFET capacitance to the Csh cap, i.e., gain=C.sub.Q1/C.sub.sh, or by enabling the pixel multiple times (i.e., taking multiple samples of the analyte measurement) and accumulating the ISFET output on the pixel sample and hold capacitor Csh without resetting the capacitor (i.e., gain is a function of the number of accumulations). Like the embodiments of FIGS. 25 and 26, arrays based on the pixel 105D are snapshot type arrays in that all pixels of the array may be operated simultaneously.

(306) Computer Hardware and Software

(307) With respect to the computer interface 252 of the array controller 250, in one exemplary implementation the interface is configured to facilitate a data rate of approximately 200 MB/sec to the computer 260, and may include local storage of up to 400 MB or greater. The computer 260 is configured to accept data at a rate of 200 MB/sec, and process the data so as to reconstruct an image of the pixels (e.g., which may be displayed in false-color on a monitor). For example, the computer may be configured to execute a general-purpose program with routines written in C++ or Visual Basic to manipulate the data and display is as desired.

(308) The systems described herein, when used for sequencing, typically involve a chemFET array supporting reaction chambers, the chemFETs being coupled to an interface capable of executing logic that converts the signals from the chemFETs into sequencing information.

(309) The sequencing information obtained from the system may be delivered to a handheld computing device, such as a personal digital assistant. Thus, in one embodiment, the invention encompasses logic for displaying a complete genome of an organism on a handheld computing device. The invention also encompasses logic adapted for sending data from a chemFET array to a handheld computing device. Any of such logic may be computer-implemented.

(310) Microfluidics and Microwell Arrays

(311) Turning from the sensor discussion, we will now be addressing the combining of the ISFET array with a microwell array and the attendant fluidics. As most of the drawings of the microwell array structure are presented only in cross-section or showing that array as only a block in a simplified diagram, FIGS. 28A and 28B are provided to assist the reader in beginning to visualize the resulting apparatus in three-dimensions. FIG. 28A shows a group of round cylindrical wells 2810 arranged in an array, while FIG. 28B shows a group of rectangular cylindrical wells 2830 arranged in an array. It will be seen that the wells are separated (isolated) from each other by the material 2840 forming the well walls. While it is certainly possible to fabricate wells of other cross-sections, in some embodiments it may not be advantageous to do so. Such an array of microwells sits over the above-discussed ISFET array, with one or more ISFETs per well. In the subsequent drawings, when the microwell array is identified, one may picture one of these arrays.

(312) Fluidic System: Apparatus and Method for Use with High Density Electronic Sensor Arrays

(313) For many uses, to complete a system for sensing chemical reactions or chemical agents using the above-explained high density electronic arrays, techniques and apparatus are required for delivery to the array elements (called pixels) fluids containing chemical or biochemical components for sensing. In this section, exemplary techniques and methods will be illustrated, which are useful for such purposes, with desirable characteristics.

(314) As high speed operation of the system may be desired, it is preferred that the fluid delivery system, insofar as possible, not limit the speed of operation of the overall system.

(315) Accordingly, needs exist not only for high-speed, high-density arrays of ISFETs or other elements sensitive to ion concentrations or other chemical attributes, or changes in chemical attributes, but also for related mechanisms and techniques for supplying to the array elements the samples to be evaluated, in sufficiently small reaction volumes as to substantially advance the speed and quality of detection of the variable to be sensed.

(316) There are two and sometimes three components or subsystems, and related methods, involved in delivery of the subject chemical samples to the array elements: (1) macrofluidic system of reagent and wash fluid supplies and appropriate valving and ancillary apparatus, (2) a flow cell and (3) in many applications, a microwell array. Each of these subsystems will be discussed, though in reverse order.

(317) Microwell Array

(318) As discussed elsewhere, for many uses, such as in DNA sequencing, it is desirable to provide over the array of semiconductor sensors a corresponding array of microwells, each microwell being small enough preferably to receive only one DNA-loaded bead, in connection with which an underlying pixel in the array will provide a corresponding output signal.

(319) The use of such a microwell array involves three stages of fabrication and preparation, each of which is discussed separately: (1) creating the array of microwells to result in a chip having a coat comprising a microwell array layer; (2) mounting of the coated chip to a fluidic interface; and in the case of DNA sequencing, (3) loading DNA-loaded bead or beads into the wells. It will be understood, of course, that in other applications, beads may be unnecessary or beads having different characteristics may be employed.

(320) The systems described herein can include an array of microfluidic reaction chambers integrated with a semiconductor comprising an array of chemFETs. In some embodiments, the invention encompasses such an array. The reaction chambers may, for example, be formed in a glass, dielectric, photodefineable or etchable material. The glass material may be silicon dioxide.

(321) Preferably, the array comprises at least 100,000 chambers. Preferably, each reaction chamber has a horizontal width and a vertical depth that has an aspect ratio of about 1:1 or less. Preferably, the pitch between the reaction chambers is no more than about 10 microns.

(322) The above-described array can also be provided in a kit for sequencing. Thus, in some embodiments, the invention encompasses a kit comprising an array of microfluidic reaction chambers integrated with an array of chemFETs, and one or more amplification reagents.

(323) In some embodiments, the invention encompasses a sequencing apparatus comprising a dielectric layer overlying a chemFET, the dielectric layer having a recess laterally centered atop the chemFET. Preferably, the dielectric layer is formed of silicon dioxide.

(324) Microwell Array Fabrication

(325) Microwell fabrication may be accomplished in a number of ways. The actual details of fabrication may require some experimentation and vary with the processing capabilities that are available.

(326) In general, fabrication of a high density array of microwells involves photo-lithographically patterning the well array configuration on a layer or layers of material such as photoresist (organic or inorganic), a dielectric, using an etching process. The patterning may be done with the material on the sensor array or it may be done separately and then transferred onto the sensor array chip, of some combination of the two. However, techniques other than photolithography are not to be excluded if they provide acceptable results.

(327) One example of a method for forming a microwell array is now discussed, starting with reference to FIG. 29. That figure diagrammatically depicts a top view of one corner (i.e., the lower left corner) of the layout of a chip showing an array 2910 of the individual ISFET sensors 2912 on the CMOS die 2914. Signal lines 2916 and 2918 are used for addressing the array and reading its output. Block 2920 represents some of the electronics for the array, as discussed above, and layer 2922 represents a portion of a wall which becomes part of a microfluidics structure, the flow cell, as more fully explained below; the flow cell is that structure which provides a fluid flow over the microwell array or over the sensor surface directly, if there is no microwell structure. On the surface of the die, a pattern such as pattern 2922 at the bottom left of FIG. 29 may be formed during the semiconductor processing to form the ISFETs and associated circuitry, for use as alignment marks for locating the wells over the sensor pixels when the dielectric has covered the die's surface.

(328) After the semiconductor structures, as shown, are formed, the microwell structure is applied to the die. That is, the microwell structure can be formed right on the die or it may be formed separately and then mounted onto the die, either approach being acceptable. To form the microwell structure on the die, various processes may be used. For example, the entire die may be spin-coated with, for example, a negative photoresist such as Microchem's SU-8 2015 or a positive resist/polyimide such as HD Microsystems HD8820, to the desired height of the microwells. The desired height of the wells (e.g., about 4-12 m in the example of one pixel per well, though not so limited as a general matter) in the photoresist layer(s) can be achieved by spinning the appropriate resist at predetermined rates (which can be found by reference to the literature and manufacturer specifications, or empirically), in one or more layers. (Well height typically may be selected in correspondence with the lateral dimension of the sensor pixel, preferably for a nominal 1:1-1.5:1 aspect ratio, height:width or diameter. Based on signal-to-noise considerations, there is a relationship between dimensions and the required data sampling rates to achieve a desired level of performance. Thus there are a number of factors that will go into selecting optimum parameters for a given application.) Alternatively, multiple layers of different photoresists may be applied or another form of dielectric material may be deposited. Various types of chemical vapor deposition may also be used to build up a layer of materials suitable for microwell formation therein.

(329) Once the photoresist layer (the singular form layer is used to encompass multiple layers in the aggregate, as well) is in place, the individual wells (typically mapped to have either one or four ISFET sensors per well) may be generated by placing a mask (e.g., of chromium) over the resist-coated die and exposing the resist to cross-linking (typically UV) radiation. All resist exposed to the radiation (i.e., where the mask does not block the radiation) becomes cross-linked and as a result will form a permanent plastic layer bonded to the surface of the chip (die). Unreacted resist (i.e., resist in areas which are not exposed, due to the mask blocking the light from reaching the resist and preventing cross-linking) is removed by washing the chip in a suitable solvent (i.e., developer) such as propyleneglycolmethylethylacetate (PGMEA) or other appropriate solvent. The resultant structure defines the walls of the microwell array.

(330) FIG. 30 shows an example of a layout for a portion of a chromium mask 3010 for a one-sensor-per-well embodiment, corresponding to the portion of the die shown in FIG. 29. The grayed areas 3012, 3014 are those that block the UV radiation. The alignment marks in the white portions 3016 on the bottom left quadrant of FIG. 30, within gray area 3012, are used to align the layout of the wells with the ISFET sensors on the chip surface. The array of circles 3014 in the upper right quadrant of the mask block radiation from reaching the well areas, to leave unreacted resist which can be dissolved in forming the wells.

(331) FIG. 31 shows a corresponding layout for the mask 3020 for a 4-sensors-per-well embodiment. Note that the alignment pattern 3016 is still used and that the individual well-masking circles 3014A in the array 2910 now have twice the diameter as the wells 3014 in FIG. 30, for accommodating four sensors per well instead of one sensor-per-well.

(332) After exposure of the die/resist to the UV radiation, a second layer of resist may be coated on the surface of the chip. This layer of resist may be relatively thick, such as about 400-450 m thick, typically. A second mask 3210 (FIG. 32), which also may be of chromium, is used to mask an area 3220 which surrounds the array, to build a collar or wall (or basin, using that term in the geological sense) 3310 of resist which surrounds the active array of sensors on substrate 3312, as shown in FIG. 33. In the particular example being described, the collar is 150 m wider than the sensor array, on each side of the array, in the x direction, and 9 m wider on each side than the sensor array, in the y direction. Alignment marks on mask 3210 (most not shown) are matched up with the alignment marks on the first layer and the CMOS chip itself.

(333) Other photolithographic approaches may be used for formation of the microwell array, of course, the foregoing being only one example.

(334) For example, contact lithography of various resolutions and with various etchants and developers may be employed. Both organic and inorganic materials may be used for the layer(s) in which the microwells are formed. The layer(s) may be etched on a chip having a dielectric layer over the pixel structures in the sensor array, such as a passivation layer, or the layer(s) may be formed separately and then applied over the sensor array. The specific choice or processes will depend on factors such as array size, well size, the fabrication facility that is available, acceptable costs, and the like.

(335) Among the various organic materials which may be used in some embodiments to form the microwell layer(s) are the above-mentioned SU-8 type of negative-acting photoresist, a conventional positive-acting photoresist and a positive-acting photodefineable polyimide. Each has its virtues and its drawbacks, well known to those familiar with the photolithographic art.

(336) Naturally, in a production environment, modifications will be appropriate.

(337) Contact lithography has its limitations and it may not be the production method of choice to produce the highest densities of wellsi.e., it may impose a higher than desired minimum pitch limit in the lateral directions. Other techniques, such as a deep UV step-and-repeat process, are capable of providing higher resolution lithography and can be used to produce small pitches and possibly smaller well diameters. Of course, for different desired specifications (e.g., numbers of sensors and wells per chip), different techniques may prove optimal. And pragmatic factors, such as the fabrication processes available to a manufacturer, may motivate the use of a specific fabrication method. While novel methods are discussed, various aspects of the invention are limited to use of these novel methods.

(338) Preferably the CMOS wafer with the ISFET array will be planarized after the final metallization process. A chemical mechanical dielectric planarization prior to the silicon nitride passivation is suitable. This will allow subsequent lithographic steps to be done on very flat surfaces which are free of back-end CMOS topography.

(339) By utilizing deep-UV step-and-repeat lithography systems, it is possible to resolve small features with superior resolution, registration, and repeatability. However, the high resolution and large numerical aperture (NA) of these systems precludes their having a large depth of focus. As such, it may be necessary, when using such a fabrication system, to use thinner photodefinable spin-on layers (i.e., resists on the order of 1-2 m rather than the thicker layers used in contact lithography) to pattern transfer and then etch microwell features to underlying layer or layers. High resolution lithography can then be used to pattern the microwell features and conventional SiO.sub.2 etch chemistries can be usedone each for the bondpad areas and then the microwell areashaving selective etch stops; the etch stops then can be on aluminum bondpads and silicon nitride passivation (or the like), respectively. Alternatively, other suitable substitute pattern transfer and etch processes can be employed to render microwells of inorganic materials.

(340) Another approach is to form the microwell structure in an organic material. For example, a dual-resist soft-mask process may be employed, whereby a thin high-resolution deep-UV resist is used on top of a thicker organic material (e.g., cured polyimide or opposite-acting resist). The top resist layer is patterned. The pattern can be transferred using an oxygen plasma reactive ion etch process. This process sequence is sometimes referred to as the portable conformable mask (PCM) technique. See B. J. Lin et al., Practicing the Novolac deep-UV portable conformable masking technique, Journal of Vacuum Science and Technology 19, No. 4, 1313-1319 (1981); and A. Cooper et al, Optimization of a photosensitive spin-on dielectric process for copper inductor coil and interconnect protection in RF SoC devices.

(341) Alternatively a drill-focusing technique may be employed, whereby several sequential step-and-repeat exposures are done at different focal depths to compensate for the limited depth of focus (DOF) of high-resolution steppers when patterning thick resist layers. This technique depends on the stepper NA and DOF as well as the contrast properties of the resist material.

(342) Another PCM technique may be adapted to these purposes, such as that shown in U.S. patent application publication no. 2006/0073422 by Edwards et al. This is a three-layer PCM process and it is illustrated in FIG. 33A. As shown there, basically six major steps are required to produce the microwell array and the result is quite similar to what contact lithography would yield.

(343) In a first step, 3320, a layer of high contrast negative-acting photoresist such as type Shipley InterVia Photodielectric Material 8021 (IV8021) 3322 is spun on the surface of a wafer, which we shall assume to be the wafer providing the substrate 3312 of FIG. 33 (in which the sensor array is fabricated), and a soft bake operation is performed. Next, in step 3324, a blocking anti-reflective coating (BARC) layer 3326, is applied and soft baked. On top of this structure, a thin resist layer 3328 is spun on and soft baked, step 3330, the thin layer of resist being suitable for fine feature definition. The resist layer 3328 is then patterned, exposed and developed, and the BARC in the exposed regions 3329, not protected any longer by the resist 3328, is removed, Step 3332. This opens up regions 3329 down to the uncured IV8021 layer. The BARC layer can now act like a conformal contact mask. A blanket exposure with a flooding exposure tool, Step 3334, cross-links the exposed IV8021, which is now shown as distinct from the uncured IV8021 at 3322. One or more developer steps 3338 are then performed, removing everything but the cross-linked IV8021 in regions 3336. Regions 3336 now constitute the walls of the microwells.

(344) Although as shown above, the wells bottom out (i.e. terminate) on the top passivation layer of the ISFETs, it is believed that an improvement in ISFET sensor performance (i.e. such as signal-to-noise ratio) can be obtained if the active bead(s) is(are) kept slightly elevated from the ISFET passivation layer. One way to do so is to place a spacer bump within the boundary of the pixel microwell. An example of how this could be rendered would be not etching away a portion of the layer-or-layers used to form the microwell structure (i.e. two lithographic steps to form the microwellsone to etch part way done, the other to pattern the bump and finish the etch to bottom out), by depositing and lithographically defining and etching a separate layer to form the bump, by using a permanent photo-definable material for the bump once the microwells are complete, or by forming the bump prior to forming the microwell. The bump feature is shown as 3350 in FIG. 33B. An alternative (or additional) non-integrated approach is to load the wells with a layer or two of very small packing beads before loading the DNA-bearing beads.

(345) Using a 6 micron thick layer of tetra-methyl-ortho-silicate (TEOS) as a SiO.sub.2-like layer for microwell formation, FIG. 33B-1 shows a scanning electron microscope (SEM) image of a cross-section of a portion 3300A of an array architecture as taught herein. Microwells 3302A are formed in the TEOS layer 3304A. The wells extend about 4 m into the 6 m thick layer. Typically, the etched well bottoms on an etch-stop material which may be, for example, an oxide, an organic material or other suitable material known in semiconductor processing for etch-stopping use. A thin layer of etch stop material may be formed on top of a thicker layer of polyimide or other suitable dielectric, such that there is about 2 m of etch stop+polyimide between the well bottom and the Metal4 (M4) layer of the chip in which the extended gate electrode 3308A is formed for each underlying ISFET in the array. As labeled on the side, the CMOS metallization layers M3, M2 and M1, which form lower level interconnects and structures, are shown, with the ISFET channels being formed in the areas indicated by arrows 3310A.

(346) In the orthogonal cross-sectional view (i.e., looking down from the top), the wells may be formed in either round or square shape. Round wells may improve bead capture and may obviate the need for packing beads at the bottom or top of the wells.

(347) The tapered slopes to the sides of the microwells also may be used to advantage. Referring to FIG. 33B-2, if the beads 3320A have a diameter larger than the bottom span across the wells, but small enough to fit into the mouths of the wells, the beads will be spaced off the bottom of the wells due to the geometric constraints. For example, FIG. 33B-2 illustrates the example of microwells that are square in cross-section as viewed from the top, 4 m on a side, with 3.8 m diameter beads 3320A loaded. Experimentally and with some calculation, one may determine suitable bead size and well dimension combinations. FIG. 33B-3 shows a portion of one 4 m well loaded with a 2.8 m diameter bead 3322A, which obviously is relatively small and falls all the way to the bottom of the well; a 4.0 m diameter bead 3324A which is stopped from reaching the bottom by the sidewall taper of the well; and an intermediate-sized bead 3326A of 3.6 m diameter which is spaced from the well bottom by packing beads 3328A. Clearly, bead size has to be carefully matched to the microwell etch taper.

(348) Thus, microwells can be fabricated by any high aspect ratio photo-definable or etchable thin-film process, that can provide requisite thickness (e.g., about 4-10 m). Among the materials believed to be suitable are photosensitive polymers, deposited silicon dioxide, non-photosensitive polymer which can be etched using, for example, plasma etching processes, etc. In the silicon dioxide family, TEOS and silane nitrous oxide (SILOX) appear suitable. The final structures are similar but the various materials present differing surface compositions that may cause the target biology or chemistry to react differently.

(349) When the microwell layer is formed, it may be necessary to provide an etch stop layer so that the etching process does not proceed further than desired. For example, there may be an underlying layer to be preserved, such as a low-K dielectric. The etch stop material should be selected according to the application. SiC and SiN materials may be suitable, but that is not meant to indicate that other materials may not be employed, instead. These etch-stop materials can also serve to enhance the surface chemistry which drives the ISFET sensor sensitivity, by choosing the etch-stop material to have an appropriate point of zero charge (PZC). Various metal oxides may be suitable addition to silicon dioxide and silicon nitride

(350) The PZCs for various metal oxides may be found in various texts, such as Metal Oxides-Chemistry and Applications by J. Fierro. We have learned that Ta.sub.2O.sub.5 may be preferred as an etch stop over Al.sub.2O.sub.3 because the PZC of Al.sub.2O.sub.3 is right at the pH being used (i.e., about 8.8) and, hence, right at the point of zero charge. In addition Ta.sub.2O.sub.5 has a higher sensitivity to pH (i.e., mV/pH), another important factor in the sensor performance Optimizing these parameters may require judicious selection of passivation surface materials.

(351) Using thin metal oxide materials for this purpose (i.e., as an etch stop layer) is difficult due to the fact of their being so thinly deposited (typically 200-500 A). A post-microwell fabrication metal oxide deposition technique may allow placement of appropriate PZC metal oxide films at the bottom of the high aspect ratio microwells.

(352) Electron-beam depositions of (a) reactively sputtered tantalum oxide, (b) non-reactive stoichiometric tantalum oxide, (c) tungsten oxide, or (d) Vanadium oxide may prove to have superior down-in-well coverage due to the superior directionality of the deposition process.

(353) The array typically comprises at least 100 microfluidic wells, each of which is coupled to one or more chemFET sensors. Preferably, the wells are formed in at least one of a glass (e.g., SiO.sub.2), a polymeric material, a photodefinable material or a reactively ion etchable thin film material. Preferably, the wells have a width to height ratio less than about 1:1. Preferably the sensor is a field effect transistor, and more preferably a chemFET. The chemFET may optionally be coupled to a PPi receptor. Preferably, each of the chemFETs occupies an area of the array that is 10.sup.2 microns or less.

(354) In some embodiments, the invention encompasses a sequencing device comprising a semiconductor wafer device coupled to a dielectric layer such as a glass (e.g., SiO.sub.2), polymeric, photodefinable or reactive ion etchable material in which reaction chambers are formed. Typically, the glass, dielectric, polymeric, photodefinable or reactive ion etchable material is integrated with the semiconductor wafer layer. In some instances, the glass, polymeric, photodefinable or reactive ion etchable layer is non-crystalline. In some instances, the glass may be SiO.sub.2. The device can optionally further comprise a fluid delivery module of a suitable material such as a polymeric material, preferably an injection moldable material. More preferably, the polymeric layer is polycarbonate.

(355) In some embodiments, the invention encompasses a method for manufacturing a sequencing device comprising: using photolithography, generating wells in a glass, dielectric, photodefinable or reactively ion etchable material on top of an array of transistors.

(356) Yet another alternative when a CMOS or similar fabrication process is used for array fabrication is to form the microwells directly using the CMOS materials. That is, the CMOS top metallization layer forming the floating gates of the ISFET array usually is coated with a passivation layer that is about 1.3 m thick. Microwells 1.3 m deep can be formed by etching away the passivation material. For example, microwells having a 1:1 aspect ratio may be formed, 1.3 m deep and 1.3 m across at their tops. Modeling indicates that as the well size is reduced, in fact, the DNA concentration, and hence the SNR, increases. So, other factors being equal, such small wells may prove desirable.

(357) Mounting the Flow Cell (Fluidic Interface) to the Sensor Chip

(358) The process of using the assembly of an array of sensors on a chip combined with an array of microwells to sequence the DNA in a sample is referred to as an experiment. Executing an experiment requires loading the wells with the DNA-bound beads and the flowing of several different fluid solutions (i.e., reagents and washes) across the wells. A fluid delivery system (e.g., valves, conduits, pressure source(s), etc.) coupled with a fluidic interface is needed which flows the various solutions across the wells in a controlled even flow with acceptably small dead volumes and small cross contamination between sequential solutions. Ideally, the fluidic interface to the chip (sometimes referred to as a flow cell) would cause the fluid to reach all microwells at the same time. To maximize array speed, it is necessary that the array outputs be available at as close to the same time as possible. The ideal clearly is not possible, but it is desirable to minimize the differentials, or skews, of the arrival times of an introduced fluid, at the various wells, in order to maximize the overall speed of acquisition of all the signals from the array.

(359) Flow cell designs of many configurations are possible; thus the system and methods presented herein are not dependent on use of a specific flow cell configuration. It is desirable, though, that a suitable flow cell substantially conform to the following set of objectives: have connections suitable for interconnecting with a fluidics delivery systeme.g., via appropriately-sized tubing; have appropriate head space above wells; minimize dead volumes encountered by fluids; minimize small spaces in contact with liquid but not quickly swept clean by flow of a wash fluid through the flow cell (to minimize cross contamination); be configured to achieve uniform transit time of the flow over the array; generate or propagate minimal bubbles in the flow over the wells; be adaptable to placement of a removable reference electrode inside or as close to the flow chamber as possible; facilitate easy loading of beads; be manufacturable at acceptable cost; and be easily assembled and attached to the chip package.

(360) Satisfaction of these criteria so far as possible will contribute to system performance positively. For example, minimization of bubbles is important so that signals from the array truly indicate the reaction in a well rather than being spurious noise.

(361) Each of several example designs will be discussed, meeting these criteria in differing ways and degrees. In each instance, one typically may choose to implement the design in one of two ways: either by attaching the flow cell to a frame and gluing the frame (or otherwise attaching it) to the chip or by integrating the frame into the flow cell structure and attaching this unified assembly to the chip. Further, designs may be categorized by the way the reference electrode is integrated into the arrangement. Depending on the design, the reference electrode may be integrated into the flow cell (e.g., form part of the ceiling of the flow chamber) or be in the flow path (typically to the outlet or downstream side of the flow path, after the sensor array).

(362) A first example of a suitable experiment apparatus 3410 incorporating such a fluidic interface is shown in FIGS. 34-37, the manufacture and construction of which will be discussed in greater detail below.

(363) The apparatus comprises a semiconductor chip 3412 (indicated generally, though hidden) on or in which the arrays of wells and sensors are formed, and a fluidics assembly 3414 on top of the chip and delivering the sample to the chip for reading. The fluidics assembly includes a portion 3416 for introducing fluid containing the sample, a portion 3418 for allowing the fluid to be piped out, and a flow chamber portion 3420 for allowing the fluid to flow from inlet to outlet and along the way interact with the material in the wells. Those three portions are unified by an interface comprising a glass slide 3422 (e.g., Erie Microarray Cat #C22-5128-M20 from Erie Scientific Company, Portsmouth, N.H., cut in thirds, each to be of size about 25 mm25 mm).

(364) Mounted on the top face of the glass slide are two fittings, 3424 and 3426, such as nanoport fittings Part #N-333 from Upchurch Scientific of Oak Harbor, Wash. One port (e.g., 3424) serves as an inlet delivering liquids from the pumping/valving system described below but not shown here. The second port (e.g., 3426) is the outlet which pipes the liquids to waste. Each port connects to a conduit 3428, 3432 such as flexible tubing of appropriate inner diameter. The nanoports are mounted such that the tubing can penetrate corresponding holes in the glass slide. The tube apertures should be flush with the bottom surface of the slide.

(365) On the bottom of the glass slide, flow chamber 3420 may comprise various structures for promoting a substantially laminar flow across the microwell array. For example, a series of microfluidic channels fanning out from the inlet pipe to the edge of the flow chamber may be patterned by contact lithography using positive photoresists such as SU-8 photoresist from MicroChem Corp. of Newton, Mass. Other structures will be discussed below.

(366) The chip 3412 will in turn be mounted to a carrier 3430, for packaging and connection to connector pins 3432.

(367) For ease of description, to discuss fabrication starting with FIG. 38 we shall now consider the glass slide 3422 to be turned upside down relative to the orientation it has in FIGS. 34-37.

(368) A layer of photoresist 3810 is applied to the top of the slide (which will become the bottom side when the slide and its additional layers is turned over and mounted to the sensor assembly of ISFET array with microwell array on it). Layer 3810 may be about 150 m thick in this example, and it will form the primary fluid carrying layer from the end of the tubing in the nanoports to the edge of the sensor array chip. Layer 3810 is patterned using a mask such as the mask 3910 of FIG. 39 (patterned meaning that a radiation source is used to expose the resist through the mask and then the non-plasticized resist is removed). The mask 3910 has radiation-transparent regions which are shown as white and radiation-blocking regions 3920, which are shown in shading. The radiation-blocking regions are at 3922-3928. The region 3926 will form a channel around the sensor assembly; it is formed about 5 mm inside the outer boundary of the mask 3920, to avoid the edge bead that is typical. The regions 3922 and 3924 will block radiation so that corresponding portions of the resist are removed to form voids shaped as shown. Each of regions 3922, 3924 has a rounded end dimensioned to receive an end of a corresponding one of the tubes 3428, 3432 passing through a corresponding nanoport 3424, 3426. From the rounded end, the regions 3922, 3924 fan out in the direction of the sensor array to allow the liquid to spread so that the flow across the array will be substantially laminar. The region 3928 is simply an alignment pattern and may be any suitable alignment pattern or be replaced by a suitable substitute alignment mechanism. Dashed lines on FIG. 38 have been provided to illustrate the formation of the voids 3822 and 3824 under mask regions 3922 and 3924.

(369) A second layer of photoresist is formed quite separately, not on the resist 3810 or slide 3422. Preferably it is formed on a flat, flexible surface (not shown), to create a peel-off, patterned plastic layer. As shown in FIG. 40, this second layer of photoresist may be formed using a mask such as mask 4010, which will leave on the flexible substrate, after patterning, the border under region 4012, two slits under regions 4014, 4016, whose use will be discussed below, and alignment marks produced by patterned regions 4018 and 4022. The second layer of photoresist is then applied to the first layer of photoresist using one alignment mark or set of alignment marks, let's say produced by pattern 4018, for alignment of these layers. Then the second layer is peeled from its flexible substrate and the latter is removed.

(370) The other alignment mark or set of marks produced by pattern 4022 is used for alignment with a subsequent layer to be discussed.

(371) The second layer is preferably about 150 m deep and it will cover the fluid-carrying channel with the exception of a slit about 150 m long at each respective edge of the sensor array chip, under slit-forming regions 4014 and 4016.

(372) Once the second layer of photoresist is disposed on the first layer, a third patterned layer of photoresist is formed over the second layer, using a mask such as mask 4110, shown in FIG. 41. The third layer provides a baffle member under region 4112 which is as wide as the collar 3310 on the sensor chip array (see FIG. 33) but about 300 m narrower to allow overlap with the fluid-carrying channel of the first layer. The third layer may be about 150 m thick and will penetrate the chip collar 3310, toward the floor of the basin formed thereby, by 150 m. This configuration will leave a headspace of about 300 m above the wells on the sensor array chip. The liquids are flowed across the wells along the entire width of the sensor array through the 150 m slits under 4014, 4016.

(373) FIG. 36 shows a partial sectional view, in perspective, of the above-described example embodiment of a microfluidics and sensor assembly, also depicted in FIGS. 34 and 35, enlarged to make more visible the fluid flow path. (A further enlarged schematic of half of the flow path is shown in FIG. 37.) Here, it will be seen that fluid enters via the inlet pipe 3428 in inlet port 3424. At the bottom of pipe 3428, the fluid flows through the flow expansion chamber 3610 formed by mask area 3922, that the fluid flows over the collar 3310 and then down into the bottom 3320 of the basin, and across the die 3412 with its microwell array. After passing over the array, the fluid then takes a vertical turn at the far wall of the collar 3310 and flows over the top of the collar to and across the flow concentration chamber 3612 formed by mask area 3924, exiting via outlet pipe 3432 in outlet port 3426. Part of this flow, from the middle of the array to the outlet, may be seen also in the enlarged diagrammatic illustration of FIG. 37, wherein the arrows indicate the flow of the fluid.

(374) The fluidics assembly may be secured to the sensor array chip assembly by applying an adhesive to parts of mating surfaces of those two assemblies, and pressing them together, in alignment.

(375) Though not illustrated in FIGS. 34-36, the reference electrode may be understood to be a metallization 3710, as shown in FIG. 37, at the ceiling of the flow chamber.

(376) Another way to introduce the reference electrode is shown in FIG. 42. There, a hole 4210 is provided in the ceiling of the flow chamber and a grommet 4212 (e.g., of silicone) is fitted into that hole, providing a central passage or bore through which a reference electrode 4220 may be inserted. Baffles or other microfeatures (not shown in FIG. 42 but discussed below in connection with FIG. 42A) may be patterned into the flow channel to promote laminar flow over the microwell array.

(377) Achieving a uniform flow front and eliminating problematic flow path areas is desirable for a number of reasons. One reason is that very fast transition of fluid interfaces within the system's flow cell is desired for many applications, particularly gene sequencing. In other words, an incoming fluid must completely displace the previous fluid in a short period of time. Uneven fluid velocities and diffusion within the flow cell, as well as problematic flow paths, can compete with this requirement. Simple flow through a conduit of rectangular cross section can exhibit considerable disparity of fluid velocity from regions near the center of the flow volume to those adjacent the sidewalls, one sidewall being the top surface of the microwell layer and the fluid in the wells. Such disparity leads to spatially and temporally large concentration gradients between the two traveling fluids. Further, bubbles are likely to be trapped or created in stagnant areas like sharp corners interior the flow cell. (The surface energy (hydrophilic vs. hydrophobic) can significantly affect bubble retention. Avoidance of surface contamination during processing and use of a surface treatment to create a more hydrophilic surface should be considered if the as-molded surface is too hydrophobic.) Of course, the physical arrangement of the flow chamber is probably the factor which most influences the degree of uniformity achievable for the flow front.

(378) One approach is to configure the flow cross section of the flow chamber to achieve flow rates that vary across the array width so that the transit times are uniform across the array. For example, the cross section of the diffuser (i.e., flow expansion chamber) section 3416, 3610 may be made as shown at 4204A in FIG. 42A, instead of simply being rectangular, as at 4204A. That is, it may have a curved (e.g., concave) wall. The non-flat wall 4206A of the diffuser can be the top or the bottom. Another approach is to configure the effective path lengths into the array so that the total path lengths from entrance to exit over the array are essentially the same. This may be achieved, for example, by placing flow-disrupting features such as cylinders or other structures oriented normal to the flow direction, in the path of the flow. If the flow chamber has as a floor the top of the microwell array and as a ceiling an opposing wall, these flow-disrupting structures may be provided either on the top of the microwell layer or on (or in) the ceiling wall. The structures must project sufficiently into the flow to have the desired effect, but even small flow disturbances can have significant impact. Turning to FIGS. 42B-42F, there are shown diagrammatically some examples of such structures. In FIG. 42B, on the surface of microwell layer 4210B there are formed a series of cylindrical flow disruptors 4214B extending vertically toward the flow chamber ceiling wall 4212B, and serving to disturb laminar flow for the fluid moving in the direction of arrow A. FIG. 42C depicts a similar arrangement except that the flow disruptors 4216C have rounded tops and appear more like bumps, perhaps hemispheres or cylinders with spherical tops. By contrast, in FIG. 42D, the flow disruptors 4218D protrude, or depend, from the ceiling wall 4212B of the flow chamber. Only one column of flow disruptors is shown but it will be appreciated that a plurality of more or less parallel columns typically would be required. For example, FIG. 42E shows several columns 4202E of such flow disruptors (projecting outwardly from ceiling wall 4212B (though the orientation is upside down relative to FIGS. 42B-42D). The spacing between the disruptors and their heights may be selected to influence the distance over which the flow profile becomes parabolic, so that transit time equilibrates.

(379) Another configuration, shown in FIGS. 42F and 42F1, involves the use of solid, beam-like projections or baffles 4220F as disruptors. This concept may be used to form a ceiling member for the flow chamber. Such an arrangement encourages more even fluid flow and significantly reduces fluid displacement times as compared with a simple rectangular cross-section without disruptor structure. Further, instead of fluid entry to the array occurring along one edge, fluid may be introduced at one corner 4242F, through a small port, and may exit from the opposite corner, 4244F, via a port in fluid communication with that corner area. The series of parallel baffles 4220F separates the flow volume between input and outlet corners into a series of channels. The lowest fluid resistant path is along the edge of the chip, perpendicular to the baffles. As incoming liquid fills this channel, the fluid is then directed between the baffles to the opposite side of the chip. The channel depth between each baffle pair preferably is graded across the chip, such that the flow is encouraged to travel toward the exit port through the farthest channel, thereby evening the flow front between the baffles. The baffles extend downwardly nearly to the chip (i.e., microwell layer) surface, but because they are quite thin, fluid can diffuse under them quickly and expose the associated area of the array assembly.

(380) FIGS. 42F2-42F8 illustrate an example of a single-piece, injection-molded (preferably of polycarbonate) flow cell member 42F200 which may be used to provide baffles 4220F, a ceiling to the flow chamber, fluid inlet and outlet ports and even the reference electrode. FIG. 42F7 shows an enlarged view of the baffles on the bottom of member 42F200 and the baffles are shown as part of the underside of member 42F200 in FIG. 42F6. As it is difficult to form rectangular features in small dimensions by injection molding, the particular instance of these baffles, shown as 4220F, are triangular in cross section.

(381) In FIG. 42F2, there is a top, isometric view of member 42F200 mounted onto a sensor array package 42F300, with a seal 42F202 formed between them and contact pins 42F204 depending from the sensor array chip package. FIGS. 42F3 and 42F4 show sections, respectively, through section lines H-H and I-I of FIG. 42F5, permitting one to see in relationship the sensor array chip 42F250, the baffles 4220F and fluid flow paths via inlet 42F260 and outlet 42F270 ports.

(382) By applying a metallization to bottom 42F280 of member 42F200, the reference electrode may be formed.

(383) Various other locations and approaches may be used for introducing fluid flow into the flow chamber, as well. In addition to embodiments in which fluid may be introduced across the width of an edge of the chip assembly 42F1, as in FIGS. 57-58, for example, or fluid may be introduced at one corner of the chip assembly, as in FIG. 42F1. Fluid also may be introduced, for example, as in FIGS. 42G and 42H, where fluid is flowed through an inlet conduit 4252G to be discharged adjacent and toward the center of the chip, as at 4254G, and flowed radially outwardly from the introduction point.

(384) FIGS. 42I and 42J in conjunction with FIGS. 42G and 42H depict in cross-section an example of such a structure and its operation. In contrast with earlier examples, this embodiment contains an additional element, a diaphragm valve, 4260I. Initially, as shown in FIG. 42H, the valve 4260I is open, providing a path via conduit 4262I to a waste reservoir (not shown). The open valve provides a low impedance flow to the waste reservoir or outlet. Air pressure is then applied to the diaphragm valve, as in FIG. 42J, closing the low impedance path and causing the fluid flow to continue downwardly through central bore 4264J in member 4266J which forms the ceiling of the flow chamber, and across the chip (sensor) assembly. The flow is collected by the channels at the edges of the sensor, as described above, and exits to the waste output via conduit 4268J.

(385) A variation on this idea is depicted in FIGS. 42K-42M, which show fluid being introduced not at the center of the chip assembly, but at one corner, 4272K, instead. It flows across the chip 3412 as symbolically indicated by lines 4274K and is removed at the diagonally opposing corner, 4276K. The advantage of this concept is that it all but eliminates any stagnation points. It also has the advantage that the sensor array can be positioned vertically so that the flow is introduced at the bottom and removed at the top to aid in the clearance of bubbles. This type of embodiment, by the way, may be considered as one quadrant of the embodiments with the flow introduced in the center of the array. An example of an implementation with a valve 4278L closed and shunting flow to the waste outlet or reservoir is shown in FIG. 42L. The main difference with respect to the embodiment of FIGS. 42I and 42J is that the fluid flow is introduced at a corner of the array rather than at its center.

(386) In all cases, attention should be given to assuring a thorough washing of the entire flow chamber, along with the microwells, between reagent cycles. Flow disturbances may exacerbate the challenge of fully cleaning out the flow chamber.

(387) Flow disturbances may also induce or multiply bubbles in the fluid. A bubble may prevent the fluid from reaching a microwell, or delay its introduction to the microwell, introducing error into the microwell reading or making the output from that microwell useless in the processing of outputs from the array. Thus, care should be taken in selecting configurations and dimensions for the flow disruptor elements to manage these potential adverse factors. For example, a tradeoff may be made between the heights of the disruptor elements and the velocity profile change that is desired.

(388) FIGS. 43-44 show another alternative flow cell design, 4310. This design relies on the molding of a single plastic piece or member 4320 to be attached to the chip to complete the flow cell. The connection to the fluidic system is made via threaded connections tapped into appropriate holes in the plastic piece at 4330 and 4340. Or, if the member 4320 is made of a material such as polydimethylsiloxane (PDMS), the connections may be made by simply inserting the tubing into an appropriately sized hole in the member 4320. A vertical cross section of this design is shown in FIGS. 43-44. This design may use an overhanging plastic collar 4350 (which may be a solid wall as shown or a series of depending, spaced apart legs forming a downwardly extending fence-like wall) to enclose the chip package and align the plastic piece with the chip package, or other suitable structure, and thereby to alignment the chip frame with the flow cell forming member 4320. Liquid is directed into the flow cell via one of apertures 4330, 4340, thence downwardly towards the flow chamber.

(389) In the illustrated embodiment, the reference electrode is introduced to the top of the flow chamber via a bore 4325 in the member 4320. The placement of the removable reference electrode is facilitated by a silicone sleeve 4360 and an epoxy stop ring 4370 (see the blow-up of FIG. 44). The silicone sleeve provides a tight seal and the epoxy stop ring prevent the electrode from being inserted too far into the flow cell. Of course, other mechanisms may be employed for the same purposes, and it may not be necessary to employ structure to stop the electrode. And if a material such as PDMS is used for member 4320, the material itself may form a watertight seal when the electrode is inserted, obviating need for the silicone sleeve.

(390) FIGS. 45 and 46 show a similar arrangement except that member 4510 lacks a bore for receiving a reference electrode. Instead, the reference electrode 4515 is formed on or affixed to the bottom of central portion 4520 and forms at least part of the flow chamber ceiling. For example, a metallization layer may be applied onto the bottom of central portion 4520 before member 4510 is mounted onto the chip package.

(391) FIGS. 47-48 show another example, which is a variant of the embodiment shown in FIGS. 43-44, but wherein the frame is manufactured as part of the flow cell rather attaching a flow port structure to a frame previously attached to the chip surface. In designs of this type, assembly is somewhat more delicate since the wirebonds to the chip are not protected by the epoxy encapsulating the chip. The success of this design is dependent on the accurate placement and secure gluing of the integrated frame to the surface of the chip. A counterpart embodiment to that of FIGS. 45-46, with the reference electrode 4910 on the ceiling of the flow chamber, and with the frame manufactured as part of the flow cell, is shown in FIGS. 49-50.

(392) Yet another alternative for a fluidics assembly, as shown in FIGS. 51-52, has a fluidics member 5110 raised by about 5.5 mm on stand-offs 5120 from the top of the chip package 5130. This allows for an operator to visually inspect the quality of the bonding between plastic piece 5140 and chip surface and reinforce the bonding externally if necessary.

(393) Some of the foregoing alternative embodiments also may be implemented in a hybrid plastic/PDMS configuration. For example, as shown in FIGS. 53-54, a plastic part 5310 may make up the frame and flow chamber, resting on a PDMS base portion 5320. The plastic part 5310 may also provides a region 5330 to the array, for expansion of the fluid flow from the inlet port; and the PDMS part may then include communicating slits 5410, 5412 through which liquids are passed from the PDMS part to and from the flow chamber below.

(394) The fluidic structure may also be made from glass as discussed above, such as photo-definable (PD) glass. Such a glass may have an enhanced etch rate in hydrofluoric acid once selectively exposed to UV light and features may thereby be micromachined on the top-side and back-side, which when glued together can form a three-dimensional low aspect ratio fluidic cell.

(395) An example is shown in FIG. 55. A first glass layer or sheet 5510 has been patterned and etched to create nanoport fluidic holes 5522 and 5524 on the top-side and fluid expansion channels 5526 and 5528 on the back-side. A second glass layer or sheet 5530 has been patterned and etched to provide downward fluid input/output channels 5532 and 5534, of about 300 m height (the thickness of the layer). The bottom surface of layer 5530 is thinned to the outside of channels 5532 and 5534, to allow the layer 5530 to rest on the chip frame and protrusion area 5542 to be at an appropriate height to form the top of the flow channel. Two glass layers, or wafers, and four lithography steps required. Both wafers should be aligned and bonded (e.g., with an appropriate glue, not shown) such that the downward fluid input/output ports are aligned properly with the fluid expansion channels. Alignment targets may be etched into the glass to facilitate the alignment process.

(396) Nanoports may be secured over the nanoport fluidic holes to facilitate connection of input and output tubing.

(397) A central bore 5550 may be etched through the glass layers for receiving a reference electrode, 5560. The electrode may be secured and sealed in place with a silicone collar 5570 or like structure; or the electrode may be equipped integrally with a suitable washer for effecting the same purpose.

(398) By using glass materials for the two-layer fluidic cell, the reference electrode may also be a conductive layer or pattern deposited on the bottom surface of the second glass layer (not shown). Or, as shown in FIG. 56, the protrusion region may be etched to form a permeable glass membrane 5610 on the top of which is coated a silver (or other material) thin-film 5620 to form an integrated reference electrode. A hole 5630 may be etched into the upper layer for accessing the electrode and if that hole is large enough, it can also serve as a reservoir for a silver chloride solution. Electrical connection to the thin-film silver electrode may be made in any suitable way, such as by using a clip-on pushpin connector or alternatively wirebonded to the ceramic ISFET package.

(399) Another alternative is to integrate the reference electrode to the sequencing chip/flow cell by using a metalized surface on the ceiling of the flow chamberi.e., on the underside of the member forming the ceiling of the fluidic cell. An electrical connection to the metalized surface may be made in any of a variety of ways, including, but not limited to, by means of applying a conductive epoxy to the ceramic package seal ring that, in turn, may be electrically connected through a via in the ceramic substrate to a spare pin at the bottom of the chip package. Doing this would allow system-level control of the reference potential in the fluid cell by means of inputs through the chip socket mount to the chip's control electronics.

(400) By contrast, an externally inserted electrode requires extra fluid tubing to the inlet port, which requires additional fluid flow between cycles.

(401) Ceramic pin grid array (PGA) packaging may be used for the ISFET array, allowing customized electrical connections between various surfaces on the front face with pins on the back.

(402) The flow cell can be thought of as a lid to the ISFET chip and its PGA. The flow cell, as stated elsewhere, may be fabricated of many different materials. Injection molded polycarbonate appears to be quite suitable. A conductive metal (e.g., gold) may be deposited using an adhesion layer (e.g., chrome) to the underside of the glow cell roof (the ceiling of the flow chamber). Appropriate low-temperature thin-film deposition techniques preferably are employed in the deposition of the metal reference electrode due to the materials (e.g., polycarbonate) and large step coverage topography at the bottom-side of the fluidic cell (i.e., the frame surround of ISFET array). One possible approach would be to use electron-beam evaporation in a planetary system.

(403) The active electrode area is confined to the central flow chamber inside the frame surround of the ISFET array, as that is the only metalized surface that would be in contact with the ionic fluid during sequencing.

(404) Once assembly is completeconductive epoxy (e.g., Epo-Tek H20E or similar) may be dispensed on the seal ring with the flow cell aligned, placed, pressed and curedthe ISFET flow cell is ready for operation with the reference potential being applied to the assigned pin of the package.

(405) The resulting fluidic system connections to the ISFET device thus incorporate shortened input and output fluidic lines, which is desirable.

(406) Still another example embodiment for a fluidic assembly is shown in FIGS. 57-58. This design is limited to a plastic piece 5710 which incorporates the frame and is attached directly to the chip surface, and to a second piece 5720 which is used to connect tubing from the fluidic system and similarly to the PDMS piece discussed above, distributes the liquids from the small bore tube to a wide flat slit. The two pieces are glued together and multiple (e.g., three) alignment markers (not shown) may be used to precisely align the two pieces during the gluing process. A hole may be provided in the bottom plate and the hole used to fill the cavity with an epoxy (for example) to protect the wirebonds to the chip and to fill in any potential gaps in the frame/chip contact. In the illustrated example, the reference electrode is external to the flow cell (downstream in the exhaust stream, through the outlet portsee below), though other configurations of reference electrode may, of course, be used.

(407) Still further examples of flow cell structures are shown in FIGS. 59-60. FIG. 59A comprises eight views (A-H) of an injection molded bottom layer, or plate, 5910, for a flow cell fluidics interface, while FIG. 59B comprises seven views (A-G) of a mating, injection molded top plate, or layer, 5950. The bottom of plate 5910 has a downwardly depending rim 5912 configured and arranged to enclose the sensor chip and an upwardly extending rim 5914 for mating with the top plate 5610 along its outer edge. To form two fluid chambers (an inlet chamber and an outlet chamber) between them. A stepped, downwardly depending portion 5960 of top plate 5950, separates the input chamber from the output chamber. An inlet tube 5970 and an outlet tube 5980 are integrally molded with the rest of top plate 5950. From inlet tube 5970, which empties at the small end of the inlet chamber formed by a depression 5920 in the top of plate 5910, to the outlet edge of inlet chamber fans out to direct fluid across the whole array.

(408) Whether glass or plastic or other material is used to form the flow cell, it may be desirable, especially with larger arrays, to include in the inlet chamber of the flow cell, between the inlet conduit and the front edge of the array, not just a gradually expanding (fanning out) space, but also some structure to facilitate the flow across the array being suitably laminar. Using the bottom layer 5990 of an injection molded flow cell as an example, one example type of structure for this purpose, shown in FIG. 59C, is a tree structure 5992 of channels from the inlet location of the flow cell to the front edge of the microwell array or sensor array, which should be understood to be under the outlet side of the structure, at 5994.

(409) The above-described systems typically utilize a laminar fluid flow system. In part, the fluid flow system preferably includes a flow chamber formed by the sensor chip and a single piece, injection molded member comprising inlet and outlet ports and mountable over the chip to establish the flow chamber. The surface of such member interior to the chamber is preferably formed to facilitate a desired expedient fluid flow, as described herein.

(410) In some embodiments, the invention encompasses an apparatus for detection of pH comprising a laminar fluid flow system. Preferably, the apparatus is used for sequencing a plurality of nucleic acid templates present in an array.

(411) The apparatus typically includes a fluidics assembly comprising a member comprising one or more apertures for non-mechanically directing a fluid to flow to an array of at least 100K (100 thousand), 500K (500 thousand), or 1M (1 million) microfluidic reaction chambers such that the fluid reaches all of the microfluidic reaction chambers at the same time or substantially the same time. Typically, the fluid flow is parallel to the sensor surface. Typically, the assembly has a Reynolds number of less than 1000, 500, 200, 100, 50, 20, or 10. Preferably, the member further comprises a first aperture for directing fluid towards the sensor array and a second aperture for directing fluid away from the sensor array.

(412) In some embodiments, the invention encompasses a method for directing a fluid to a sensor array comprising: providing a fluidics assembly comprising an aperture fluidly coupling a fluid source to the sensor array; and non-mechanically directing a fluid to the sensor array. By non-mechanically it is meant that the fluid is moved under pressure from a gaseous pressure source, as opposed to a mechanical pump.

(413) In some embodiments, the invention encompasses an array of wells, each of which is coupled to a lid having an inlet port and an outlet port and a fluid delivery system for delivering and removing fluid from said inlet and outlet ports non-mechanically.

(414) In some embodiments, the invention encompasses a method for sequencing a biological polymer such as a nucleic acid utilizing the above-described apparatus, comprising: directing a fluid comprising a monomer to an array of reaction chambers wherein the fluid has a fluid flow Reynolds number of at most 2000, 1000, 200, 100, 50, or 20. The method may optionally further comprise detecting a pH or a change in pH from each said reaction chamber. This is typically detected by ion diffusion to the sensor surface. There are various other ways of providing a fluidics assembly for delivering an appropriate fluid flow across the microwell and sensor array assembly, and the forgoing examples are thus not intended to be exhaustive.

(415) Reference Electrode

(416) Commercial flow-type fluidic electrodes, such as silver chloride proton-permeable electrodes, may be inserted in series in a fluidic line and are generally designed to provide a stable electrical potential along the fluidic line for various electrochemical purposes. In the above-discussed system, however, such a potential must be maintained at the fluidic volume in contact with the microwell ISFET chip. With conventional silver chloride electrodes, it has been found difficult, due to an electrically long fluidic path between the chip surface and the electrode (through small channels in the flow cell), to achieve a stable potential. This led to reception of noise in the chip's electronics. Additionally, the large volume within the flow cavity of the electrode tended to trap and accumulate gas bubbles that degraded the electrical connection to the fluid. With reference to FIG. 60, a solution to this problem has been found in the use of a stainless steel capillary tube electrode 6010, directly connected to the chip's flow cell outlet port 6020 and connected to a voltage source (not shown) through a shielded cable 6030. The metal capillary tube 6010 has a small inner diameter (e.g., on the order of 0.01) that does not trap gas to any appreciable degree and effectively transports fluid and gas like other microfluidic tubing. Also, because the capillary tube can be directly inserted into the flow cell port 6020, it close to the chip surface, reducing possible electrical losses through the fluid. The large inner surface area of the capillary tube (typically about 2 long) may also contribute to its high performance. The stainless steel construction is highly chemically resistant, and should not be subject to electrochemical effects due to the very low electrical current use in the system (<1 A). A fluidic fitting 6040 is attached to the end of the capillary that is not in the flow cell port, for connection to tubing to the fluid delivery and removal subsystem.

(417) Fluidics System

(418) A complete system for using the sensor array will include suitable fluid sources, valving and a controller for operating the valving to low reagents and washes over the microarray or sensor array, depending on the application. These elements are readily assembled from off-the-shelf components, with and the controller may readily be programmed to perform a desired experiment.

(419) It should be understood that the readout at the chemFET may be current or voltage (and change thereof) and that any particular reference to either readout is intended for simplicity and not to the exclusion of the other readout. Therefore any reference in the following text to either current or voltage detection at the chemFET should be understood to contemplate and apply equally to the other readout as well. In important embodiments, the readout reflects a rapid, transient change in concentration of an analyte. The concentration of more than one analyte may be detected at different times. In some instances, such measurements are to be contrasted with methods that focus on steady state concentration measurements.

(420) Biological and Chemical Reactions

(421) As already discussed, the apparatus, systems and methods of the invention can be used to detect and/or monitor interactions between various entities. These interactions include biological and chemical reactions and may involve enzymatic reactions and/or non-enzymatic interactions such as but not limited to binding events. As an example, the invention contemplates monitoring enzymatic reactions in which substrates and/or reagents are consumed and/or reaction intermediates, byproducts and/or products are generated. An example of a reaction that can be monitored according to the invention is a nucleic acid synthesis method such as one that provides information regarding nucleic acid sequence. This reaction will be discussed in greater detail herein.

(422) Nucleic Acid Sequencing

(423) In the context of a sequencing reaction, the apparatus and system provided herein is able to detect nucleotide incorporation based on changes in the chemFET current and/or voltage, as those latter parameters are interrelated. Current changes may be the result of one or more of the following events either singly or some combination thereof: generation of hydrogen (and concomitant changes in pH for example in the presence of low strength buffer or no buffer), generation of PPi, generation of Pi (e.g., in the presence of pyrophosphatase), increased charge of nucleic acids attached to the chemFET surface, and the like.

(424) As discussed herein, the invention contemplates methods for determining the nucleotide sequence of a nucleic acid. Such methods involve the synthesis of a new nucleic acid (e.g., using a primer that is hybridized to a template nucleic acid or a self-priming template, as will be appreciated by those of ordinary skill), based on the sequence of a template nucleic acid. That is, the sequence of the newly synthesized nucleic acid is complimentary to the sequence of the template nucleic acid and therefore knowledge of sequence of the newly synthesized nucleic acid yields information about the sequence of the template nucleic acid.

(425) More specifically, knowledge of the sequence of the newly synthesized nucleic acid is obtained by determining whether a known nucleotide has been incorporated into the newly synthesized nucleic acid and, if so, how many of such known nucleotides have been incorporated. Importantly, the order in which the known nucleotides are added to the reaction mixture is known and thus the order of incorporated nucleotides (if any) is also known. In an illustrative embodiment, a template hybridized to a primer is contacted with a first pool of identical known nucleotides (e.g., dATP) in the presence of polymerase. If the next available position on the template is a thymidine residue, then the dATP is incorporated into the primed nucleic acid strand and a signal is detected for example based on hydrogen release. If the next available position is not a thymidine residue, then the dATP will not incorporate and no signal will be detected because no hydrogen will be released. If the next available position and one or more contiguous positions thereafter are thymidine residues, then a corresponding number of dATP will be incorporated and a signal commensurate with the number of nucleotides incorporated will be detected. The reaction well or chamber is then washed to remove unincorporated nucleotides and released hydrogen, following which another pool of identical known nucleotides (e.g., dCTP) is added. The process is repeated until all four nucleotides are separately added to the reaction well (i.e., one cycle), and then the cycles are repeated. The cycles may be repeated for 50 times, 100 times, 200 times, 300 times, 400 times, 500 times, 750 times, or more, depending on the length of sequence information desired.

(426) Nucleotide incorporation can be monitored in a number of ways, including the production of products such as PPi, Pi and/or H.sup.+. The incorporation of a dNTP into the nucleic acid strand releases PPi which can then be hydrolyzed to two orthophosphates (Pi) and one hydrogen ion (FIG. 61A). The generation of the hydrogen ion therefore can be detected as an indicator of nucleotide incorporation. Alternatively, Pi may be detected directly or indirectly.

(427) Alternatively, when templates or primers are attached to the sensor surface, nucleotide incorporation is detected based on an increase in charge (typically, negative charge) of the template, primer or template/primer complex. Templates may be bound to the chemFET surface or they may be hybridized to primers that are bound to the chemFET surface. Primers hybridized to the templates can be extended in the presence of polymerase and one or a combination of known nucleotides. Nucleotide incorporation is detected by increases in charge at the chemFET surface that result from the addition of phosphodiester backbone linkages that carry negative charges. Thus, with each successive addition of a nucleotide, the negative charge of the immobilized nucleic acid increases, and this increase can be detected by the chemFET. The number of nucleotide incorporations that can be detected in this manner may be at least 10, at least 20, at least 30, at least 40, at least 50, at least 60, at least 70, at least 80, at least 90, at least 100, or more. The invention contemplates that in this instance nucleotide incorporation can be detected by measuring change in charge at the chemFET surface as well as released hydrogen ions that come into contact with the chemFET.

(428) Any and all of these events (and more as described herein) may be detected at the chemFET thereby causing a current change that correlates with nucleotide incorporation.

(429) The systems described herein can be used for sequencing nucleic acids without optical detection. Preferably, at least 10.sup.6 base pairs are sequenced per hour, more preferably at least 10.sup.7 base pairs are sequenced per hour, and most preferably at least 10.sup.8 base pairs are sequenced per hour using the above-described method. Thus, the method may be used to sequence an entire human genome within about 24 hours, more preferably within about 20 hours, even more preferably within about 15 hours, even more preferably within about 10 hours, even more preferably within about 5 hours, and most preferably within about 1 hour. These rates may be achieved using multiple ISFET arrays as shown herein, and processing their outputs in parallel.

(430) pH Based Nucleic Acid Sequencing

(431) Reduced Buffering

(432) Certain aspects of the invention therefore relate to detecting hydrogen ions released as a function of nucleotide incorporation and in some embodiments as a function of nucleotide excision. It is important in these and various other aspects to detect as many released hydrogen ions as possible in order to achieve as high a signal (and/or a signal to noise ratio) as possible. Strategies for increasing the number of released protons that are ultimately detected by the chemFET surface include without limitation limiting interaction of released protons with reactive groups in the well, choosing a material from which to manufacture the well in the first instance that is relatively inert to protons, preventing released protons from exiting the well prior to detection at the chemFET, and increasing the copy number of templates per well (in order to amplify the signal from each nucleotide incorporation), among others.

(433) Some instances of the invention employ an environment, including a reaction solution, that is minimally buffered, if at all. Buffering can be contributed by the components of the solution or by the solid supports in contact with such solution. A solution having no or low buffering capacity (or activity) is one in which changes in hydrogen ion concentration on the order of at least about +/0.005 pH units, at least about +/0.01, at least about +/0.015, at least about +/0.02, at least about +/0.03, at least about +/0.04, at least about +/0.05, at least about +/0.10, at least about +/0.15, at least about +/0.20, at least about +/0.25, at least about +/0.30, at least about +/0.35, at least about +/0.45, at least about +/0.50, or more are detectable (e.g., using the chemFET sensors described herein). In some embodiments, the pH change per nucleotide incorporation is on the order of about 0.005. In some embodiments, the pH change per nucleotide incorporation is a decrease in pH. Reaction solutions that have no or low buffering capacity may contain no or very low concentrations of buffer, or may use weak buffers.

(434) A buffer is an ionic molecule (or a solution comprising an ionic molecule) that resists, to varying extents, changes in pH. Buffers include without limitation Tris, tricine, phosphate, boric acid, borate, acetate, morpholine, citric acid, carbonic acid, and phosphoric acid. The strength of a buffer is a relative term since it depends on the nature, strength and concentration of the acid or base added to or generated in the solution of interest. A weak buffer is a buffer that allows detection (and therefore is not able to control or mask) pH changes on the order of those listed above.

(435) The reaction solution may have a buffer concentration equal to or less than 1 mM, equal to or less than 0.9 mM, equal to or less than 0.8 mM, equal to or less than 0.7 mM, equal to or less than 0.6 mM, equal to or less than 0.5 mM, equal to or less than 0.4 mM, equal to or less than 0.3 mM, equal to or less than 0.2 mM, equal to or less than 0.1 mM, or less including zero. The buffer concentration may be 50-100 M. A non-limiting example of a weak buffer suitable for the sequencing reactions described herein wherein pH change is the readout is 0.1 mM Tris or Tricine.

(436) In some aspects, in addition to or instead of using reduced buffering solutions, nucleotide incorporation (and optionally excision) is carried out in the presence of additional agents which serve to shield potential buffering events that may occur in solution. These agents are referred to herein as buffering inhibitors since they inhibit the ability of components within a solution or a solid support in contact with the solution to sequester and/or otherwise interfere with released hydrogen ions prior to their detection by the chemFET surface. In the absence of such inhibitors, released hydrogen ions may interact with or be sequestered by reactive groups in the solution or on solid supports in contact with the solution. These hydrogen ions are less likely to reach and be detected by the chemFET surface, leading to a weaker signal than is otherwise possible. In the presence of such inhibitors however there will be fewer reactive groups available for interaction with or sequestration of hydrogen ions. As a result, a greater proportion of released hydrogen ions will reach and be detected by the chemFET surface, leading to stronger signals. Reactive groups that can interfere with released hydrogen ions include without limitation reactive groups such as free bases on single stranded nucleic acids and SiOH groups that may be present in the passivation layer. Some suitable buffering inhibitors demonstrate little or no buffering capacity in the pH range of 5-9, meaning that pH changes on the order of 0.005, 0.01, 0.02, 0.03, 0.04, 0.05, 0.1, 0.2, 0.3, 0.4, 0.5 or more pH units are detectable (e.g., by using an ISFET) in the presence of such inhibitors.

(437) There are various types of buffering inhibitors. One example of a buffering agent is an agent that binds to single stranded nucleic acids (or single stranded nucleic acid regions, as may occur in a template nucleic acid) thereby shielding reactive groups such as free bases. These agents may be RNA oligonucleotides (or RNA oligomers, or oligoribonucleotides, as they are referred to herein interchangeably) having complementary sequences to the afore-mentioned single stranded regions of template nucleic acids. RNA oligonucleotides are useful because they are not able to serve as primers for a sequencing reaction as compared to DNA oligonucleotides. In order to bind to (or shield the effects of) as much of a single stranded nucleic acid as possible, a plurality (or set, or mixture) of RNA oligonucleotides can be used. As an example, a set of RNA oligonucleotides that are 2, 3, 4, 5, 6, or more nucleotides in length can be used together with single stranded templates. The short length of these RNA oligonucleotides allows them to be displaced by the polymerase as it progresses along with the length of the nucleic acid template. Such displacement does not require exonuclease activity from the polymerase. Typically, the RNA oligonucleotides are of random sequence. In some embodiments, this is preferred as no prior knowledge of the sequence of the single stranded region of the template is required. FIGS. 61B and 61C illustrate the difference in ion detection at an ISFET in the presence or absence of a RNA hexamer bound to a single stranded template.

(438) Another example of a class of buffering inhibitors is phospholipids. The phospholipids may be naturally occurring or non-naturally occurring phospholipids. Examples of phospholipids that may be used as buffering inhibitors include but are not limited to phosphatidylcholine, phosphatidylethanolamine, phosphatidylglycerol, and phosphatidylserine.

(439) Another example of a buffering inhibitor is sulfonic acid based surfactants such as poly(ethylene glycol) 4-nonylphenyl 3-sulfopropyl ether (PNSE), the potassium salt of which is shown in FIG. 61D. In addition to shielding reactive groups that would otherwise interfere with released protons, PNSE has also been reported to enhance polymerase activity.

(440) Another example of a buffering inhibitor is polyanionic electrolytes such as poly(styrenesulfonic acid), the sodium salt of which is shown in FIG. 61E.

(441) Another example of a buffering inhibitor is polycationic electrolytes such as poly(diallydimethylammonium), the chloride salt of which is shown in FIG. 61F. These compounds are known to bind to DNA.

(442) Another example of a buffering inhibitor is tetramethyl ammonium, the chloride salt of which is shown in FIG. 61G.

(443) These various inhibitors may be present throughout a reaction by being included in nucleotide solutions, wash solutions, and the like. Alternatively, they may be flowed through the chamber at set times relative to the flow through of nucleotides and/or other reaction reagents. In still other embodiments, they may be coated on the chemFET surface (or reaction chamber surface). Such coating may be covalent or non-covalent.

(444) Another way of reducing the buffering capacity in the reaction well is to covalently attach nucleic acids to capture beads, in embodiments in which capture beads are used. Such covalent attachment is in contrast to non-covalent methods described herein that include for example biotin, streptavidin interactions. In these latter embodiments, biotinylated primers can be attached to streptavidin coated beads, followed by hybridization to template. However, streptavidin, like other proteins, is capable of buffering, and therefore its presence would interfere with the detection of hydrogen ions released as a consequence of nucleotide incorporation. Thus, the invention also contemplates in some instances approaches that do not rely on streptavidin in the attachment mechanism. One such alternative involves covalently coupling primers to beads (and/or other solid supports such as the chemFET surface). Covalently coupling primers to such solid supports serves at least two purposes. First, it eliminates the need for proteins, such as streptavidin, that comprise functional side groups (such as primary, secondary or tertiary amines and carboxylic acids) that can buffer pH changes in the range of pH 5-9. Second, it serves to increase the number of templates that can be conjugated to the solid support, such as a single bead, by reducing steric hindrance effects that may exist when using bulky proteins such as streptavidin. In still other embodiments, templates may be directly conjugated covalently to solid supports such as beads.

(445) Primers can be covalently coupled to beads in any number of ways, several of which are shown in FIGS. 61H and 61I or described in Steinberg et al. Biopolymers 73:597-605, 2004, as an example. Reactive groups that can be used to conjugate primers to beads include epoxide, tosyl, amino and carboxyl groups. In addition, beads having a silica surface, as discussed below, can be used with chlorophyl, azide, and alkyne reactive groups. In some embodiments, the preferred combination is a polymer core bead with a polymer surface using tosyl reactive groups.

(446) Increasing the number of templates or primers (i.e., copy number) results in a greater number of nucleotide incorporations per sensor and/or per reaction chamber, thereby leading to a higher signal and thus signal to noise ratio. Copy number can be increased for example by using templates that are concatemers (i.e., nucleic acids comprising multiple, tandemly arranged, copies of the nucleic acid to be sequenced), by increasing the number of nucleic acids on or in beads up to and including saturating such beads, and by attaching templates or primers to beads or to the sensor surface in ways that reduce steric hindrance and/or ensure template attachment (e.g., by covalently attaching templates), among other things. Concatemer templates may be immobilized on or in beads or on other solid supports such as the sensor surface, although in some embodiments concatemers templates may be present in a reaction chamber without immobilization. For example, the templates (or complexes comprising templates and primers) may be covalently or non-covalently attached to the chemFET surface and their sequencing may involve detection of released hydrogen ions and/or addition of negative charge to the chemFET surface upon a nucleotide incorporation event. The latter detection scheme may be performed in a buffered environment or solution (i.e., any changes in pH will not be detected by the chemFET and thus such changes will not interfere with detection of negative charge addition to the chemFET surface).

(447) For some aspects described herein, it is important that buffering capacity not be affected in the process of increasing copy number. Thus, various methods are provided for increasing copy number using strategies and/or linkers that do not impact the buffering capacity of the environment. In some instances, the functional groups, linkers and/or polymers themselves have no or limited buffering capacity, and their use does not obscure the detection of hydrogen ions released as a result of nucleotide incorporation or excision, as the case may be.

(448) Increasing copy number may also be accomplished by increasing the number of attachment points for primers (or templates). Some of these methodologies are described below.

(449) In one embodiment, the solid support is coated with a polymer such as polyethylene glycol (PEG) which does not comprise functional groups that interact with the primer and its functional groups, except as provided below for initially attaching primer. PEG linkers of varying lengths can be used so that primers can be attached at varying distances from the solid support surface, thereby decreasing the amount of steric hindrance that may otherwise exist between primers and the complexes they ultimately form (e.g., primer/template hybrids). The solid supports can be coated one or more times with a mixture of 2, 3, 4, or more PEG linkers of differing lengths. The end result is an increased distance between ends of PEG linkers attached to the solid support. Attachment of primers to the PEG linkers can be accomplished using any reactive groups known in the art. As an example, click chemistry can be used between azide groups on the ends of PEG linkers and alkyde groups on the primers.

(450) In another embodiment, polymers having preferably more than one functional (or reactive) group are used. Each of the functional groups is available for conjugation with a separate primer. Useful polymers in this regard include those having hydroxyl groups, amine groups, thiol groups, and the like. Examples of suitable polymers include dextran and chitosan. Linear or branched forms of these polymers may be used. An example of a branched polymer with multiple functionalities is branched dextran. It will be apparent to those of ordinary skill in the art than any chimeric polymer or copolymer may also be used provided it has a sufficient number of functional groups for primer attachment.

(451) Yet another embodiment involves the use of dendrimers and preferably higher order dendrimers to bind primer. Dendrimers are three-dimensional complexes that can be made having any functional group. Examples of dendrimers include the PAMAM dendrimers, an example of which is CAS No. 163442-69-1 which has 256 amine groups. Dendrimers are commercially available from sources such as Sigma-Aldrich and Dendritic Nanotechnologies Inc. It will be understood that dendrimers with other functional groups also can be used.

(452) The invention further contemplates the use of any combination of the above embodiments for maximizing the number of primers attached to a solid support. Thus for example the solid support surface may be coated one or more times (e.g., once or twice) with the PEG linkers of varying lengths, and to such linkers may be attached multifunctionality polymers such as dextran or chitosan (in either linear or branched form), followed by attachment of primers. As another example, dendrimers may be attached to the PEG linkers, followed by primer attachment to the dendrimers.

(453) In still another embodiment, the invention contemplates coating the solid support surface with a population of self-assembling monomers some proportion of which are bound to primers. As an example, the monomers may be acrylamide monomers some of which are attached to primers. The end result is a solid support having a polyacrylamide coating with interspersed primers. The density of primers bound to the solid support can be manipulated by changing the ratio of monomers that have primers and monomers that lack primers. This strategy has been reported by Rehman et al. Nucleic Acids Research, 1999, 27(2):649-655.

(454) Still other methods for attaching nucleic acids to beads are taught by Lund et al., Nucleic Acids Research, 1988, 16(22):10861-10880, Joos et al. Anal Biochem, 1997, 247:96-101, Steinberg et al. Biopolymers, 2004, 73:597-605, and Steinberg-Tatman et al. Bioconjugate Chem 2006 17:841-848.

(455) Beads can be made of any material including but not limited to cellulose, cellulose derivatives, gelatin, acrylic resins, glass, silica gels, polyvinyl pyrrolidine (PVP), co-polymers of vinyl and acrylamide, polystyrene, polystyrene cross-linked with divinylbenzene or the like (see, Merrifield Biochemistry 1964, 3, 1385-1390), polyacrylamides, latex gels, dextran, crosslinked dextrans (e.g., Sephadex), rubber, silicon, plastics, nitrocellulose, natural sponges, metal, and agarose gel (Sepharose). In one embodiment, the beads are streptavidin-coated beads.

(456) Beads suitable for covalent attachment may be magnetic or non-magnetic in nature. They may have a polymer core with a polymer surface, a polymer core with a silica surface, and a silica core with a silica surface. The bead core may be hollow, porous, or solid, as described below.

(457) The bead diameter will depend on the density of the chemFET and microwell arrays used, with larger arrays (and thus smaller sized wells) requiring smaller beads. Generally the bead size may be about 1-10 microns, and more preferably 2-6 microns. In some embodiments, the beads are about 5.9 microns while in other embodiments the beads are about 2.8 microns. In still other embodiments, the beads are about 1.5 microns, or about 1 micron in diameter. In some embodiments, beads having a diameter that ranges from about 3.3 to 3.5 microns may be used for reaction well arrays having a pitch on the order of about 5.1 microns. In other embodiments, beads having a diameter that ranges from about 5 to 6.5 microns may be used for reaction well arrays having a pitch on the order to about 9 microns. It is to be understood that the beads may or may not be perfectly spherical in shape. It is also to be understood that other beads may be used and other mechanisms for attaching the nucleic acid to the beads may be used. In some instances the capture beads (i.e., the beads on which the sequencing reaction occurs) are the same as the template preparation beads including the amplification beads. In some instances, even where non-covalent attachment is contemplated, a spacer is used to distance the template nucleic acid (and in particular the target nucleic acid sequence comprised therein) from a solid support such as a bead. This facilitates sequencing of the end of the target closest to the bead, for instance. Examples of suitable linkers are known in the art (see Diehl et al. Nature Methods, 2006, 3(7):551-559) and include but are not limited to carbon-carbon linkers such as but not limited to iSp18. Beads can be purchased from commercial suppliers such as Bangs, Dynal and Micromod. Additional spacers and nucleic acid attachment mechanisms are discussed above.

(458) As stated above, some beads may be solid while others may be porous or hollow. These beads will have a porous surface such that reagents from the reaction solution may move into and out of the bead These may have empty channels or hollow cores that comprise at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90% of the bead volume. These beads will be referred to herein as porous beads, porous microparticles, or capsules in view of their non-solid cores, and these terms are intended to embrace porous as well as hollow beads regardless of diameter or volume. They may or may not be spherical.

(459) The invention contemplates the use of such porous beads in the various sequencing methods described herein. More specifically, the invention contemplates sequencing nucleic acids that are present in porous beads. Porous beads may be generated by methods known in the art. See for example Mak et al. Adv. Funct. Mater. 2008 18:2930-2937; Morimoto et al. MEMS 2008 Tucson Ariz. USA Jan. 13-17, 2008 Poster Abstract 304-307; Lee et al. Adv. Mater. 2008 20:3498-3503; Martin-Banderas et al. Small. 2005 1(7):688-92; and published PCT application WO03/078659.

(460) Porous microparticles may be initially generated to contain a single template nucleic acid which is later amplified with all amplified copies of the nucleic acid being retained in the microparticle. Amplification may occur before or while the bead is in contact with a chemFET array, and/or optionally in a reaction chamber. If performed before contact with the chemFET array, beads that have successfully undergone amplification can be selected and thereby enriched. As an example, beads having amplified nucleic acids can be separated from other beads based on density. Amplification may be isothermal or PCR amplification, or other means of amplification, as the invention is not to be limited in this regard. The beads may contain at least two types of enzymes such as two types of polymerases. For example, the beads may contain one type of polymerase that is suitable for amplification of the nucleic acid and a second type of polymerase that is suitable for sequencing the amplified nucleic acids. The beads preferably contain a plurality of both types of polymerases and preferably the number of each polymerase will be in excess of a saturating amount so as not to create a polymerase-limited environment. Once amplification is completed, the amplification polymerase may be inactivated, while maintaining the activity of the sequencing polymerase. Typically, the enzymes and nucleic acids will be retained in the bead while smaller compounds, such as dNTPs and other nucleic acid synthesis reagents and cofactors, are allowed to diffuse into and out of the bead. Importantly for the invention, synthesis byproducts such as PPi and hydrogen ions will also diffuse out of the beads, in order to be detected by the chemFET.

(461) Nick Translation

(462) The invention provides, in various other aspects, other modes for analyzing, including for example sequencing, nucleic acids using reactions that involve interdependent nucleotide incorporation and nucleotide excision. As used herein, interdependent nucleotide incorporation and nucleotide excision means that both reactions occur on the same nucleic molecule at contiguous sites on the nucleic acid, and one reaction facilitates the other.

(463) An example of such a reaction is a nick translation reaction. A nick translation reaction, as used herein, refers to a reaction catalyzed by a polymerase enzyme having 5 to 3 exonuclease activity, that involves incorporation of a nucleotide onto the free 3 end of a nicked region of double stranded DNA and excision of a nucleotide located at the free 5 end of the nicked region of the double stranded DNA. Nick translation therefore refers to the movement of the nicked site along the length of the nicked strand of DNA in a 5 to 3 direction. As will be recognized by those of ordinary skill in the art, the nick translation reaction includes a sequencing-by-synthesis reaction based on the intact strand of the double stranded DNA. This strand acts as the template from which the new strand is synthesized. The method does not require the use of a primer because the double stranded DNA can prime the reaction independently. These aspects of the invention will refer specifically to nick translation for the sake of brevity, but it is to be understood that any other combined reaction of nucleotide excision and incorporation will be equally and fully intended in the following discussion.

(464) The nick translation approach has two features that make it well suited to the detection methods provided herein. First, the nick translation reaction results in the release of two hydrogen ions for each combined excision/incorporation step, thereby providing a more robust signal at the chemFET each time a nucleotide is incorporated into a newly synthesized strand. A sequencing-by-synthesis method, in the absence of nucleotide excision, releases one hydrogen ion per nucleotide incorporation. In contrast, nick translation releases a first hydrogen ion upon incorporation of a nucleotide and a second hydrogen ion upon excision of another nucleotide. This increases the signal that can be sensed at the chemFET, thereby increasing signal to noise ratio and providing a more definitive readout of nucleotide incorporation.

(465) Second, the use of a double stranded DNA template (rather than a single stranded DNA template) results in less interference of the template with released ions and a better signal at the chemFET. A single stranded DNA has exposed groups that are able to interfere with (for example, sequester) hydrogen ions. These reactive groups are shielded in a double stranded DNA where they are hydrogen bonded to complementary groups. By being so shielded, these groups do not substantially impact hydrogen ion level or concentration. As a result, signal resulting from hydrogen ion release is greater in the presence of double stranded as compared to single stranded templates, as will be signal to noise ratio, thereby further contributing to a more definitive readout of nucleotide incorporation.

(466) Templates suitable for nick translation typically are completely or partially double stranded. Such templates comprise an opening (or a nick) which acts as an entry point for a polymerase. Such openings can be introduced into the template in a controlled manner as described below and known in the art.

(467) As will be appreciated by one of ordinary skill in the art, it is preferable that these openings be present in each of the plurality of identical templates at the same location in the template sequence. Typical molecular biology techniques involving nick translation use randomly created nicks along the double stranded DNA because their aim is to produce a detectably labeled nucleic acid. These prior art methods generate nicks through the use of sequence-independent nicking enzymes such as DNase I. In the methods of the invention however the nick location must be known, non-random and uniform for all templates of identical sequence. There are various ways of achieving this, and some of these are discussed below.

(468) One way of achieving this is to create a population of identical double stranded nucleic acid templates that comprise a uracil residue in a defined location on one strand. The uracil may be present in a primer that is used to generate the double stranded nucleic acid or a probe that is hybridized to a single stranded region of a predominantly double stranded nucleic acid. The population of identical template nucleic acids can be generated by an amplification reaction, for example a PCR reaction. The PCR reaction can be performed using a primer pair, one of which comprises a uracil residue. Alternatively, the PCR reaction can be performed with non-uracil containing primers, followed by denaturation of the double stranded amplified products, and hybridization of one strand to a uracil-containing primer. This latter embodiment requires that the single stranded, primed templates be made double stranded prior to the nick translation reaction. These reactions may be carried out while the nucleic acids are bound to a solid support such as a bead. Alternatively, the double stranded nucleic acid templates may be first generated and then attached to a solid support.

(469) The uracil-containing double stranded nucleic acids are then contacted with uracil DNA glycosylase (UDG). UDG is an enzyme that removes uracil from DNA by cleaving the N-glycosylic bond. In some instances, the nucleic acid is contacted with a second enzyme that removes uracil. The second enzyme may be an AP endonuclease, or a lyase or another enzyme having similar nuclease activity. The nucleic acids may be in the reaction chamber (or well) discussed herein during exposure to these enzymes, or they may be added to the reaction chamber (or well) following enzyme contact. Following contact with one (in some instances) or both enzymes, the double stranded nucleic acid comprises a nick at a specific location. More importantly, all nucleic acids of the same sequence and treated in an identical manner will be nicked at the same location. These nicked nucleic acids can then be used as templates for nucleic acid sequencing or other analysis.

(470) Another way in which double stranded nucleic acids can be uniformly nicked is similar to the method just described with the exception that a nucleotide sequence recognized by a nickase or nicking enzyme is incorporated into the nucleic acid. The nickase cuts on only one strand of the double stranded DNA. Some nickases cut their recognition sequence while others cut at a distance from their recognition sequence (e.g., type II nickases). Nickases with longer recognition sites are preferred because such sites are more infrequent and thus less likely to be present in the target nucleic acid (e.g., the genomic fragment) included in the template nucleic acid. Examples of single stranded sequence specific nucleases (and their respective sequences) include without limitation Nb.BbvCI (CCTCAGC), Nt.BbvCI (CCTCAGC), Nb.Bsml (GAATGC), Nt.Sapl (GCTCTTCN), Nb.BsrDI (GCAATG), and Nb.BtsI (GCAGTG), wherein the arrow indicates the site of nicking. Nickases are commercially available from a number of suppliers including NEB. Accordingly, the nucleic acids are prepared having a copy of the nickase recognition sequence in a region of known sequence (e.g., a primer or other artificial sequence in the template nucleic acid). These nucleic acids are then contacted with the corresponding nickase to nick the nucleic acid. As with the uracil embodiment, contact with the nickase can occur before or after the nucleic acids are attached to solid support such as beads, and before or after the nucleic acids are loaded in reaction wells.

(471) Still another way in which double stranded nucleic acids may be uniformly nicked is by incorporating ribonucleotides (rather than deoxyribonucleotides) into one strand of the double stranded nucleic acids. This can be accomplished in a manner similar to that described for the generation of uracil-containing nucleic acids. In other words, a double stranded nucleic acid can be generated using primers that contain one or more ribonucleotides at predetermined and thus known positions. The resultant nucleic acids are then contacted with RNase H or other enzyme that degrades the RNA portion of DNA-RNA hybrids. RNase H in particular hydrolyses phosphodiester bonds of RNA in RNA:DNA heteroduplexes, thereby producing 3 OH groups and 5 phosphate groups. If the double stranded nucleic acid is generated with only a single ribonucleotide then only a single abasic site will result, whereas if the double stranded nucleic acid is generated with multiple ribonucleotides then multiple abasic sites will result. In either case, identical nucleic acids can still be analyzed using a nick translation reaction once all but one of the abasic sites are filled by the polymerase. Taq polymerase is preferred in some embodiments involving these RNA-DNA hybrids. Again, as with the other methods described above, contact with RNase H or other similar enzyme can occur before or after the nucleic acids are attached to a solid support such as beads, and before or after the nucleic acids are loaded in reaction wells.

(472) Still another way to prepare double stranded nucleic acids suitable as templates for nucleotide incorporation and excision events is to generate a double stranded nucleic acid having a 3 overhang on one end, and then subsequently hybridize to the 3 overhang a nucleic acid that is shorter than the overhang by at least one nucleotide. Preferably, after hybridization of the two nucleic acids to each other, there will be one unpaired internal nucleotide in the overhang and this will be the site from which nick translation will begin. Again, the sequence of the 3 overhang and the hybridizing nucleic acid will be known and therefore the location of the abasic site will also be known and will be identical for all template nucleic acids. The hybridization can occur before or after the nucleic acids are attached to a solid support such as beads, and before or after the nucleic acids are loaded into reaction wells.

(473) Another example of a suitable nick translation template is a self-priming nucleic acid. The self priming nucleic acid may comprise a double stranded and a single stranded region that is capable of self-annealing in order to prime a nucleic acid synthesis reaction. The single stranded region is typically a known synthetic sequence ligated to a nucleic acid of interest. Its length can be predetermined and engineered to create an opening following self-annealing, and such opening can act as an entry point for a polymerase.

(474) It is to be understood that, as the term is used herein, a nicked nucleic acid, such as a nicked double stranded nucleic acid, is a nucleic acid having an opening (e.g., a break in its backbone, or having abasic sites, etc.) from which a polymerase can incorporate and optionally excise nucleotides. The term is not limited to nucleic acids that have been acted upon by an enzyme such as a nicking enzyme, nor is it limited simply to breaks in a nucleic acid backbone, as will be clear based on the exemplary methods described herein for creating such nucleic acids.

(475) Once the nicked double stranded nucleic acids are generated, they are then subjected to a nick translation reaction. If the nick translation reaction is performed to sequence the template nucleic acid, the nick translation can be carried out in a manner that parallels the sequencing-by-synthesis methods described herein. More specifically, in some embodiments each of the four nucleotides is separately contacted with the nicked templates in the presence of a polymerase having 5 to 3 exonuclease activity. In other embodiments, known combinations of nucleotides are used. Examples of suitable enzymes include DNA polymerase I from E. coli, Bst DNA polymerase, and Taq DNA polymerase. The order of the nucleotides is not important as long as it is known and preferably remains the same throughout a run. After each nucleotide is contacted with the nicked templates, it is washed out followed by the introduction of another nucleotide, just as described herein. In the nick translation embodiments, the wash will also carry the excised nucleotide away from the chemFET.

(476) It should be appreciated that just as with other aspects and embodiments described herein the nucleotides that are incorporated into the nicked region need not be extrinsically labeled since it is a byproduct of their incorporation that is detected as a readout rather than the incorporated nucleotide itself. Thus, the nick translation methods may be referred to as label-free methods, or fluorescence-free methods, since incorporation detection is not dependent on an extrinsic label on the incorporated nucleotide. The nucleotides are typically naturally occurring nucleotides. It should also be recognized that since the methods benefit from the consecutive incorporation of as many nucleotides as possible, the nucleotides are not for example modified versions that lead to premature chain termination, such as those used in some sequencing methods.

(477) Target and Template Nucleic Acids

(478) The nucleic acid being sequenced is referred to herein as the target nucleic acid. Target nucleic acids include but are not limited to DNA such as but not limited to genomic DNA, mitochondrial DNA, cDNA and the like, and RNA such as but not limited to mRNA, miRNA, and other interfering RNA species, and the like. The nucleic acids may be naturally or non-naturally occurring. They may be obtained from any source including naturally occurring sources such as any bodily fluid or tissue that contains DNA, including, but not limited to, blood, saliva, cerebrospinal fluid (CSF), skin, hair, urine, stool, and mucus, or synthetic sources. The nucleic acids may be PCR products, cosmids, plasmids, naturally occurring or synthetic libraries, and the like. The invention is not intended to be limited in this regard. It should therefore be understood that the invention contemplates analysis, including sequencing, of DNA as well as RNA.

(479) With respect to RNA, amplification methods such as the SMART system and NASBA are known in the art and have been reported by van Gelder et al. PNAS, 1990, 87:1663-1667, Chadwick et al. BioTechniques, 1998, 25:818-822, Brink et al. J Clin Microbiol, 1998, 36(11):3164-3169, Voisset et al. BioTechniques, 2000,29:236-240, and Zhu et al. BioTechniques, 2001, 30:892-897. The amplification methods described in these references are incorporated by reference herein.

(480) The starting amounts of nucleic acids to be sequenced determine the minimum sample requirements. Considering the following bead sizes, with an average of 450 bases in the single stranded region of a template, with an average molecular weight of 325 g/mol per base, Table 2 shows the following:

(481) TABLE-US-00002 TABLE 2 Bead Size (um) femto gram of DNA 0.2 0.124 0.3 0.279 0.7 1.52 1.05 3.42 2.8 24.3 5.9 108

(482) Given the number of beads and microwells contemplated for use in an array, in some embodiments of the invention, it will be apparent that a sample taken from a subject to be tested need only be on the order of 3 g. Thus, the systems and methods described herein can be utilized to sequence an entire genome of an organism from about 3 g of DNA or less. As discussed herein, such sequences can be obtained without the use of optics or extrinsic labels.

(483) Target nucleic acids are prepared using any manner known in the art. As an example, genomic DNA may be harvested from a sample according to techniques known in the art (see for example Sambrook et al. Maniatis). Following harvest, the DNA may be fragmented to yield nucleic acids of smaller length. The resulting fragments may be on the order of hundreds, thousands, or tens of thousands nucleotides in length. In some embodiments, the fragments are 200-1000 base pairs in size, or 300-800 base pairs in size, about 200, about 300, about 400, about 500, about 600, about 700, about 800, about 900, or about 1000 base pairs in length, although they are not so limited.

(484) Nucleic acids may be fragmented by any means including but not limited to mechanical, enzymatic or chemical means. Examples include shearing, sonication, nebulization, endonuclease (e.g., DNase I) digestion, amplification such as PCR amplification, or any other technique known in the art to produce nucleic acid fragments, preferably of a desired length. As used herein, fragmentation also embraces the use of amplification to generate a population of smaller sized fragments of the target nucleic acid. That is, the target nucleic acids may be melted and then annealed to two (and preferably more) amplification primers and then amplified using for example a thermostable polymerase (such as Taq). An example is a massively parallel PCR-based amplification. Fragmentation can be followed by size selection techniques to enrich or isolate fragments of a particular length or size. Such techniques are also known in the art and include but are not limited to gel electrophoresis or SPRI.

(485) Alternatively, target nucleic acids that are already of sufficiently small size (or length) may be used. Such target nucleic acids include those derived from an exon enrichment process. Thus, rather than fragmenting (randomly or non-randomly) longer target nucleic acids, the targets may be nucleic acids that naturally exist or can be isolated in shorter, useable lengths such as mRNAs, cDNAs, exons, PCR products (as described above), and the like. See Albert et al. Nature Methods 2007 4(11):903-905 (microarray hybridization of exons and locus-specific regions), Porreca et al. Nature Methods 2007 4(11):931-936, and Okou et al. Nature Methods 2007 4(11):907-909 for methods of isolating and/or enriching sequences such as exons prior to sequencing.

(486) The target nucleic acids are typically ligated to adaptor sequences on both the 5 and 3 ends. The resulting nucleic acid is referred to herein as a template nucleic acid. The template nucleic acid therefore comprises at least the target nucleic acid and usually comprises nucleotide sequences in addition to the target at both the 5 and 3 ends. The template nucleic acids may be engineered such that different templates have identical 5 ends and identical 3 ends. The 5 and 3 ends in each individual template are preferably different in sequence.

(487) Adaptor sequences may comprise sequences complementary to amplification primer sequences, to be used in amplifying the target nucleic acids. One adaptor sequence may also comprise a sequence complementary to the sequencing primer (i.e., the primer from which sequencing occurs). The opposite adaptor sequence may comprise a moiety that facilitates binding of the nucleic acid to a solid support such as but not limited to a bead. An example of such a moiety is a biotin molecule (or a double biotin moiety, as described by Diehl et al. Nature Methods, 2006, 3(7):551-559) and such a labeled nucleic acid can therefore be bound to a solid support having avidin or streptavidin groups. Another moiety that can be used is the NHS-ester and amine affinity pair. It is to be understood that the invention is not limited in this regard and one of ordinary skill is able to substitute these affinity pairs with other binding pairs. In some embodiments, the solid support is a bead and in others it is a wall of the reaction chamber (or well) such as a bottom wall or a side wall, or both.

(488) In some embodiments, the invention contemplates the use of a plurality of template populations, wherein each member of a given plurality shares the same 3 end but different template populations differ from each other based on their 3 end sequences. As an example, the invention contemplates in some instances sequencing nucleic acids from more than one subject or source. Nucleic acids from a first source may have a first 3 sequence, nucleic acids from a second source may have a second 3 sequence, and so on, provided that the first, second, and any additional 3 sequences are different from each other. In this respect, the 3 end, which is typically a unique sequence, can be used as a barcode or identifier to label (or identify) the source of the particular nucleic acid in a given well. Reference can be made to Meyer et al. Nucleic Acids Research 2007 35(15):e97 for a discussion of labeling nucleic acid with barcodes followed by sequencing.

(489) Templates disposed onto a chemFET array (and thus over more than one sensor in the array) may share identical primer binding sequences. This facilitates the use of an identical primer across microwells and also ensures that a similar (or identical) degree of primer hybridization occurs across microwells. Once annealed to complementary primers such as sequencing primers, the templates are in a complex referred to herein as a template/primer hybrid. In this hybrid, at least one region of the template is double stranded (i.e., where it is bound to its complementary primer) and in some instances the remaining region of the template is single stranded. It is this single stranded region that acts as the template for the incorporation of nucleotides to the end of the primer and thus it is also this single stranded region which is ultimately sequenced according to the invention. As discussed herein, this single stranded region may be bound by short RNA oligomers, of known or unknown (i.e., random) sequence, and still capable of being sequenced.

(490) In some embodiments, the template nucleic acid is able to self-anneal thereby creating a 3 end from which to incorporate nucleotide triphosphates. Thus in such instances, there is no need for a separate sequencing primer since the template acts as both template and primer. See Eriksson et al. Electrophoresis 25:20-27, 2004 for a discussion of the use of self-annealing template in a pyrosequencing reaction. In other instances, sequencing primers are hybridized (or annealed, as the terms are used interchangeably herein) to the templates prior to introduction or contact with the chemFET or reaction chamber.

(491) The plurality of templates in each microwell may be introduced into the microwells (e.g., via a nucleic acid loaded bead), or it may be generated in the microwell itself. A plurality is defined herein as at least two, and in the context of template nucleic acids in a microwell or on a nucleic acid loaded bead includes tens, hundreds, thousands, ten thousands, hundred thousands, millions, or more copies of the template nucleic acid. The limit on the number of copies will depend on a number of variables including the number of binding sites for template nucleic acids (e.g., on the beads or on the walls of the microwells), the size of the beads, the length of the template nucleic acid, the extent of the amplification reaction used to generate the plurality, and the like. It is generally preferred to have as many copies of a given template per well in order to increase signal to noise ratio as much as possible, as discussed herein. In some embodiments, the amplification is a representative amplification. A representative amplification is an amplification that does not alter the relative representation of any nucleic acid species.

(492) Thus, the template nucleic acid may be amplified prior to or after placement in the well and/or contact with the sensor. Amplification and conjugation of nucleic acids to solid supports such as beads may be accomplished in a number of ways. For example, in one aspect once a template nucleic acid is loaded into a well of the flow cell 200, amplification may be performed in the well, the resulting amplified product denatured, and sequencing-by-synthesis then performed. In one embodiment, the template is amplified in solution and then hybridized to a single primer that is immobilized on the chemFET surface. The use of only one primer type on the surface ensures that only one of the amplified strands is eventually bound to the surface, and the other strand is removed through wash.

(493) Amplification methods include but are not limited to emulsion PCR (i.e., water in oil emulsion amplification) as described by Margulies et al. Nature 2005 437(15):376-380 and accompanying supplemental materials, bridge amplification, rolling circle amplification (RCA), concatemer chain reaction (CCR), or other strategies using isothermal or non-isothermal amplification techniques.

(494) Bridge amplification can be used to produce a solid support (such as a reaction chamber wall or a bead) having amplified copies of the same template. The method involves contacting template nucleic acids with the chemFET/reaction chamber array at a limiting dilution in order to ensure that reaction chambers contain only a single template. The chemFET surface will typically be coated with two populations of primers. In one embodiment, the chemFET surface is coated with both forward and reverse primers that are complementary to the engineered 5 and 3 sequences of the template. The template is bound to the chemFET surface directly and then allowed to hybridize at its free end with a complementary primer on the surface. The primer is extended using unlabeled nucleotides, and the resultant double stranded nucleic acid is then denatured. This results in immobilized copies of the template nucleic acid and its complement in close proximity on the surface. This process is repeated by allowing the template and its complement to hybridize at their free ends to other primers on the surface. The net result is a population of immobilized template and a population of immobilized complement that are interspersed amongst each other. The sequencing-by-synthesis reaction is then carried out using a sequencing primer that binds to one but not both immobilized strands. This effectively selects for one of the strands and ensures that only one strand is sequenced. Either strand can be sequenced since they are complements of each other.

(495) In a related embodiment, the solid support is a bead and the bead is coated with the two primer populations and only a single stranded template nucleic acid, at least initially. This amplification method is described in U.S. Pat. No. 5,641,658 to Adams et al.

(496) In still another embodiment, each solid support surface (whether bead or reaction chamber wall) has bound thereto a specific and unique primer pair that may be but is not limited to a gene specific primer pair. One or both of the primers in the pair select for templates in a library that is applied to the solid support. Due to the unique sequence of the primers, it is expected that only the desired template will hybridize and then be amplified and sequenced, as described above.

(497) RCA or CCR amplification methods generate concatemers of template nucleic acids that comprise tens, hundreds, thousands or more tandemly arranged copies of the template. Such concatemers may still be referred to herein as template nucleic acids, although they may contain multiple copies of starting template nucleic acids. In some embodiments, they may also be referred to as amplified template nucleic acids. Alternatively, they may be referred to herein as comprising multiple copies of target nucleic acid fragment. Concatemers may contain 2, 3, 4, 5, 6, 7, 8, 9, 10, 20, 30, 40, 50, 60, 70, 80, 90, 100, 500, 1000, or more copies of the starting nucleic acid. They may contain 10-10.sup.2, 10.sup.2-10.sup.3, 10.sup.3-10.sup.4, 10.sup.3-10.sup.5, or more copies of the starting nucleic acid. Concatemers generated using these or other methods (such as for example DNA nanoballs) can be used in the sequencing-by-synthesis methods described herein. The concatemers may be generated in vitro apart from the array and then placed into reaction chambers of the array or they may be generated in the reaction chambers. One or more inside walls of the reaction chamber may be treated to enhance attachment and retention of the concatemers, although this is not required. In some embodiments of the invention, if the concatemers are attached to an inside wall of the reaction chamber, such as the chemFET surface, then nucleotide incorporation at least in the context of a sequencing-by-synthesis reaction may be detected by a change in charge at the chemFET surface, as an alternative to or in addition to the detection of released hydrogen ions as discussed herein. If the concatemers are deposited onto a chemFET surface and/or into a reaction chamber, sequencing-by-synthesis can occur through detection of released hydrogen ions as discussed herein. The invention embraces the use of other approaches for generating concatemerized templates. One such approach is a PCR described by Stemmer et al. in U.S. Pat. No. 5,834,252, and the description of this approach is incorporated by reference herein.

(498) The ability to use template nucleic acids independently of beads and that can be deposited into reaction chambers or onto chemFET surfaces facilitates the use of dense chemFET arrays. As will be understood, denser arrays will typically incorporate more chemFETs and optionally more reaction chambers (where they are used) per array (or chip). In order to accommodate the increased number of chemFETs and optionally reaction chambers, the size of the chemFETs and optionally reaction chambers is reduced. Accordingly, in some instances, it may be preferable to use nucleic acids that are concatemers of the nucleic acid to be sequenced, independently of beads. Such nucleic acids may be allowed to self-assemble onto a treated chemFET surface, or they may settle into the well (for example, by gravity), or they may be pulled in by magnetic or other force. Thus, the invention contemplates the use of such concatemerized template nucleic acids in the pH based sequencing-by-synthesis methods described herein.

(499) As discussed herein, one approach for generating nucleic acids that comprise multiple copies of a nucleic acid to be sequenced involves amplification of a circular template. The resultant amplified product forms a three dimensional structure that may occupy a spherical volume or other three dimensional volume and shape. The occupied volume may vary, depending on the size of the resultant nucleic acid. For example, in some instances the spherical volume may have an average diameter on the order of about 100-300 nm. The generation of these three dimensional structures is described further in published US patent applications US20070072208A1 and US20070099208A1, both to Drmanac et al.

(500) Such nucleic acids may be generated in solution (i.e., amplification occurs in solution) and therefore emulsion based techniques or reaction chambers or wells are not necessary in some instances. As each resultant nucleic acid consists of a clonal amplified population of a starting nucleic acid, there will be no cross contamination of nucleic acids and nor does there have to be any physical separation between individual amplification reactions. Thus, in some aspects, it is contemplated that nucleic acids (such as DNA nanoballs or amplicons) are generated in solution and then deposited onto chemFET surfaces and/or into reaction chambers. Further references that describe amplifications methods suitable for the synthesis of these nucleic acids include U.S. Pat. Nos. 4,683,195, 4,965,188, 4,683,202, 4,800,159, 5,210,015, 6,174,670, 5,399,491, 6,287,824, 5,854,033 and published US patent application US20060024 711. Linear rolling circle amplification, multiple displacement amplification, and padlock probe rolling circle amplification can all be used to generate clonal amplicons without the need for limiting dilution in order to avoid cross-contamination of nucleic acid templates by each other.

(501) The chemFET surfaces may be treated (or patterned) or untreated (or unpatterned). In some instances, treated (or patterned) surfaces are preferred in order to maximize nucleic acid deposition and/or retention onto a surface. It is further known in the art that these nucleic acids may self-assemble onto the chemFET surface provided the chemFET array surface comprises regions to which the nucleic acids bind and optionally regions to which they do not bind. Additionally, the binding of a nucleic acid to one region on the surface will repel the binding of another nucleic acid, thereby precluding the possibility that two or more nucleic acids of different sequence could co-exist at the same chemFET surface. The chemFET array may have an occupancy on the order of greater than 50%, greater than 60%, greater than 70%, greater than 80%, or 90% or greater (i.e., the number of individual chemFET surfaces onto which a single nucleic acid is deposited). It will be understood that, as used herein, the term deposited refers simply to the placement of the nucleic acid in close proximity and potentially in contact with a chemFET surface (and optionally reaction chamber), but it does not require any particular interaction, whether covalent or non-covalent, between the nucleic acid and the chemFET surface.

(502) The amplified nucleic acids discussed herein may be attached to the chemFET surface through functionalities incorporated into (e.g., during amplification) or added post-synthesis to the nucleic acid. Such functionalities may be located at adaptor regions within the nucleic acid which are not intended for sequencing according to the methods provided herein. For example, a concatemer may be generated from a circular template having two or more adaptor sequences (or nucleic acids) located upstream and downstream of the nucleic acids being sequenced. Alternatively, the starting (or initial) nucleic acid may consist of a single adaptor sequence and a single nucleic acid to be sequenced and in the process of amplification (such as, for example, RCA) the adaptor sequence is used to separate the copies of the nucleic acid to be sequenced from each other. Whether in this embodiment or others described herein, functionalities present in the adaptor sequences may be used to attach and/or retain the resultant amplified nucleic acids on a chemFET surface and optionally a reaction chamber. Exemplary functionalities include but are not limited to amino groups, sulfhydryl groups, carbonyl groups, biotin, streptavidin, avidin, amine allyl labeled nucleotides, NHS-ester interaction, thioether linkages, and the like.

(503) Attachment may be via non-covalent bonds between capture nucleic acids present on the chemFET surface and complementary sequences in the adapter regions, or adsorption to the surface via Van der Waals forces, hydrogen bonding, static charge interactions, ionic and hydrophobic interactions, and the like. Techniques used to attach DNAs to microarrays may also be used to attach the amplified products to the chemFET surface. These techniques include but are not limited to those described by Smirnov, Genes, Chrom & Cancer 40:72-77, 2004 and Beaucage Curr Med Chem 8:1213-1244, 2001.

(504) Deposition and/or retention may also be accomplished using magnetic forces. In these embodiments, magnetic particles may be incorporated into and/or attached post-synthesis to the amplified nucleic acids (e.g., at regions not intended for sequencing). Once the nucleic acids are distributed on a chemFET array and optionally a reaction chamber array, the array is placed in proximity to a magnet in order to move the nucleic acids towards the chemFET surface and optionally into a reaction chamber.

(505) It should also be understood that the methods described herein contemplate the synthesis of the amplified nucleic acids on or in proximity to the chemFET and optionally in a reaction chamber in addition to synthesis in solution followed by deposition onto the chemFET surface. It is expected however that the latter approach will result in a greater degree of occupancy of chemFET surfaces in the array.

(506) Accordingly, provided herein is an array of nucleic acids comprising a plurality of chemFETs each having a surface, and a plurality of nucleic acids, each nucleic acid deposited onto (or attached to) individual chemFET surfaces, wherein each nucleic acid comprises multiple identical copies of an initial nucleic acid to be sequenced. In some instances, the nucleic acid has a random coil state.

(507) Also provided herein is a method for sequencing a nucleic acid present in a reaction chamber of a reaction chamber array, comprising synthesizing a concatemer of a starting nucleic acid, wherein the concatemer has a cross-sectional diameter greater than the diameter of the reaction well, optionally immobilizing (whether covalently or non-covalently) the concatemer in the reaction chamber, and sequencing the concatemer, preferably by sequencing-by-synthesis methods provided herein (e.g., pH based sequencing-by-synthesis methods). It will be understood that if the reaction chamber has a non-circular cross-section then one or more or an average of cross-sectional dimensions can be used (as can a cross-sectional area) in comparing the concatemer and the reaction chamber sizes or dimensions. It should also be understood that the size of the concatemer relative to the reaction chamber will preclude the presence of more than one concatemer per reaction chamber.

(508) Solid Supports and Capture Beads

(509) The solid support to which the template nucleic acids or primers are bound is referred to herein as the capture solid support. The solid support may be a wall of the reaction chamber (or well) including the surface of the chemFET, or a bottom or side wall of the reaction chamber provided such wall is capacitively coupled to the chemFET. If the solid support is a bead, then such bead may be referred to herein as a capture bead. Such beads are generally referred to herein as loaded with or bearing nucleic acid if they have nucleic acids attached to their surface (whether covalently or non-covalently) and/or present in their interior core. Some capture beads comprise a porous surface that allows entry and exit of small compounds such as amplification or sequencing reagents (e.g., dNTPs, co-factors, etc.). This class of beads typically will comprise nucleic acids internally and in this way they function to localize the nucleic acids, optionally without the need to attach the nucleic acids to a solid support. In embodiments in which capture beads are used, preferably each reaction well comprises only a single capture bead.

(510) The degree of saturation of any capture (i.e., sequencing) bead with template nucleic acid to be sequenced may not be 100%. In some embodiments, a saturation level of 10%-100% exists. As used herein, the degree of saturation of a capture bead with a template refers to the proportion of sites on the bead that are conjugated to template. In some instances this may be at least 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 55%, 60%, 65%, 70%, 75%, 80%, 85%, 90%, 95%, or it may be 100%.

(511) Microwell Arrays

(512) Important aspects of the invention contemplate sequencing a plurality of different template nucleic acids simultaneously. This may be accomplished using the sensor arrays described herein. In one embodiment, the sensor arrays are overlayed (and/or integral with) an array of microwells (or reaction chambers or wells, as those terms are used interchangeably herein), with the proviso that there be at least one sensor per microwell. Present in a plurality of microwells is a population of identical copies of a template nucleic acid. There is no requirement that any two microwells carry identical template nucleic acids, although in some instances such templates may share overlapping sequence. Thus, each microwell comprises a plurality of identical copies of a template nucleic acid, and the templates between microwells may be different.

(513) The microwells may vary in size between arrays. The size of these microwells may be described in terms of a width (or diameter) to height ratio. In some embodiments, this ratio is 1:1 to 1:1.5. The bead to well size (e.g., the bead diameter to well width, diameter, or height) is preferably in the range of 0.6-0.8.

(514) The microwell size may be described in terms of cross section. The cross section may refer to a slice parallel to the depth (or height) of the well, or it may be a slice perpendicular to the depth (or height) of the well. The microwells may be square in cross-section, but they are not so limited. The dimensions at the bottom of a microwell (i.e., in a cross section that is perpendicular to the depth of the well) may be 1.5 m by 1.5 m, or it may be 1.5 m by 2 m. Suitable diameters include but are not limited to at or about 100 m, 95 m, 90 m, 85 m, 80 m, 75 m, 70 m, 65 m, 60 m, 55 m, 50 m, 45 m, 40 m, 35 m, 30 m, 25 m, 20 m, 15 m, 10 m, 9 m, 8 m, 7 m, 6 m, 5 m, 4 m, 3 m, 2 m, 1 m or less. In some particular embodiments, the diameters may be at or about 44 m, 32 m, 8 m, 4 m, or 1.5 m. Suitable heights include but are not limited to at or about 100 m, 95 m, 90 m, 85 m, 80 m, 75 m, 70 m, 65 m, 60 m, 55 m, 50 m, 45 m, 40 m, 35 m, 30 m, 25 m, 20 m, 15 m, 10 m, 9 m, 8 m, 7 m, 6 m, 5 m, 4 m, 3 m, 2 m, 1 m or less. In some particular embodiments, the heights may be at or about 55 m, 48 m, 32 m, 12 m, 8 m, 6 m, 4 m, 2.25 m, 1.5 m, or less. Various embodiments of the invention contemplate the combination of any of these diameters with any of these heights. In still other embodiments, the reaction well dimensions may be (diameter in m by height in m) 44 by 55, 32 by 32, 32 by 48, 8 by 8, 8 by 12, 4 by 4, 4 by 6, 1.5 by 1.5, or 1.5 by 2.25.

(515) The reaction well volume may range (between arrays, and preferably not within a single array) based on the well dimensions. This volume may be at or about 100 picoliter (pL), 90, 80, 70, 60, 50, 40, 30, 20, 10, or fewer pL. In important embodiments, the well volume is less than 1 pL, including equal to or less than 0.5 pL, equal to or less than 0.1 pL, equal to or less than 0.05 pL, equal to or less than 0.01 pL, equal to or less than 0.005 pL, or equal to or less than 0.001 pL. The volume may be 0.001 to 0.9 pL, 0.001 to 0.5 pL, 0.001 to 0.1 pL, 0.001 to 0.05 pL, or 0.005 to 0.05 pL. In particular embodiments, the well volume is 75 pL, 34 pL, 23 pL, 0.54 pL, 0.36 pL, 0.07 pL, 0.045 pL, 0.0024 pL, or 0.004 pL. In some embodiments, each reaction chamber is no greater than about 0.39 pL in volume and about 49 m.sup.2 surface aperture, and more preferably has an aperture no greater than about 16 m.sup.2 and volume no greater than about 0.064 pL.

(516) It is to be understood therefore that the invention contemplates a sequencing apparatus for sequencing unlabeled nucleic acid acids, optionally using unlabeled nucleotides, without optical detection and comprising an array of at least 100 reaction chambers. In some embodiments, the array comprises 10.sup.3, 10.sup.4, 10.sup.5, 10.sup.6, 10.sup.7 or more reaction chambers. The pitch (or center-to-center distance between adjacent reaction chambers) is on the order of about 1-10 microns, including 1-9 microns, 1-8 microns, 1-7 microns, 1-6 microns, 1-5 microns, 1-4 microns, 1-3 microns, or 1-2 microns.

(517) In various aspects and embodiments of the invention, the nucleic acid loaded beads, of which there may be tens, hundreds, thousands, or more, first enter the flow cell and then individual beads enter individual wells. The beads may enter the wells passively or otherwise. For example, the beads may enter the wells through gravity without any applied external force. The beads may enter the wells through an applied external force including but not limited to a magnetic force or a centrifugal force. In some embodiments, if an external force is applied, it is applied in a direction that is parallel to the well height/depth rather than transverse to the well height/depth, with the aim being to capture as many beads as possible. Preferably, the wells (or well arrays) are not agitated, as for example may occur through an applied external force that is perpendicular to the well height/depth. Moreover, once the wells are so loaded, they are not subjected to any other force that could dislodge the beads from the wells.

(518) The Examples provide a brief description of an exemplary bead loading protocol in the context of magnetic beads. It is to be understood that a similar approach could be used to load other bead types. The protocol has been demonstrated to reduce the likelihood and incidence of trapped air in the wells of the flow chamber, uniformly distribute nucleic acid loaded beads in the totality of wells of the flow chamber, and avoid the presence and/or accumulation of excess beads in the flow chamber.

(519) In various instances, the invention contemplates that each well in the flow chamber contain only one nucleic acid loaded bead. This is because the presence of two beads per well will yield unusable sequencing information derived from two different template nucleic acids.

(520) In some embodiments, the microwell array may be analyzed to determine the degree of loading of beads into the microwells, and in some instances to identify those microwells having beads and those lacking beads. The ability to know which microwells lack beads provides another internal control for the sequencing reaction. The presence or absence of a bead in a well can be determined by standard microscopy or by the sensor itself. FIGS. 61J and K are images captured from an optical microscope inspection of a microwell array (J) and from the sensor array underlying the microwell array (K). The white spots in both images each represent a bead in a well. Such microwell observation usually is only made once per run particularly since the beads once disposed in a microwell are unlikely to move to another well.

(521) It has also been found that in the absence of flow the background signal (i.e., noise) is less than or equal to about 0.25 mV, but that in the presence of DNA-loaded capture beads that signal increases to about 1.0 mV+/0.5 mV. This increase is sufficient to allow one to determine wells with beads.

(522) The percentage of occupied wells in the well array may vary depending on the methods being performed. If the method is aimed at extracting maximum sequence data in the shortest time possible, then higher occupancy is desirable. If speed and throughout is not as critical, then lower occupancy may be tolerated. Therefore depending on the embodiment, suitable occupancy percentages may be at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, at least 90%, at least 91%, at least 92%, at least 93%, at least 94%, at least 95%, at least 96%, at least 97%, at least 98%, at least 99%, or 100% of the wells. As used herein, occupancy refers to the presence of one nucleic acid loaded bead in a well and the percentage occupancy refers to the proportion of total wells in an array that are occupied by a single bead. Wells that are occupied by more than one bead typically cannot be used in the analyses contemplated by the invention.

(523) Simultaneous Sequencing Reactions

(524) The invention therefore contemplates performing a plurality of different sequencing reactions simultaneously. A plurality of identical sequencing reactions is occurring in each occupied well simultaneously. It is this simultaneous and identical incorporation of dNTP within each well that increases the signal to noise ratio. By performing sequencing reactions in a plurality of wells simultaneously, a plurality of different nucleic acids are simultaneously sequenced. The methods aim to maximize complete incorporation across all microwells for any given dNTP, reduce or decrease the number of unincorporated dNTPs that remain in the wells after signal detection is complete, and achieve as a high a signal to noise ratio as possible.

(525) Before and/or while in the wells, the template nucleic acids are incubated with a sequencing primer that binds to its complementary sequence located on the 3 end of the template nucleic acid (i.e., either in the amplification primer sequence or in another adaptor sequence ligated to the 3 end of the target nucleic acid) and with a polymerase for a time and under conditions that promote hybridization of the primer to its complementary sequence and that promote binding of the polymerase to the template nucleic acid. The primer can be of virtually any sequence provided it is long enough to be unique. The hybridization conditions are such that the primer will hybridize to only its true complement on the 3 end of the template. Suitable conditions are disclosed in Margulies et al. Nature 2005 437(15):376-380 and accompanying supplemental materials.

(526) It will be understood that the amount of sequencing primers and polymerases may be saturating, above saturating level, or in some instances below saturating levels. As used herein, a saturating level of a sequencing primer or a polymerase is a level at which every template nucleic acid is hybridized to a sequencing primer or bound by a polymerase, respectively. Thus the saturating amount is the number of polymerases or primers that is equal to the number of templates on a single bead. In some embodiments, the level is greater than this, including at least 2 fold, 3 fold, 4 fold, 5 fold, 10 fold, or more than the level of the template nucleic acid. In other embodiments, the number of polymerases and/or primers may be 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, or up to 100% of the number of templates on a single bead in a single well.

(527) Suitable polymerases include but are not limited to DNA polymerase, RNA polymerase, or a subunit thereof, provided it is capable of synthesizing a new nucleic acid strand based on the template and starting from the hybridized primer. An example of a suitable polymerase subunit for some but not all embodiments of the invention is the exo-minus (exo.sup.) version of the Klenow fragment of E. coli DNA polymerase I which lacks 3 to 5 exonuclease activity. Other polymerases include T4 exo, Therminator, and Bst polymerases. In still other embodiments that require excision of nucleotides (e.g., in the process of a nick translation reaction), polymerases with exonuclease activity are preferred. The polymerase may be free in solution (and may be present in wash and dNTP solutions) or it may be bound for example to the beads (or corresponding solid support) or to the walls of the chemFET but preferably not to the ISFET surface itself. The polymerase may be one that is modified to comprise accessory factors including without limitation single or double stranded DNA binding proteins.

(528) Some embodiments of the invention require that the polymerase have sufficient processivity. As used herein, processivity is the ability of a polymerase to remain bound to a single primer/template hybrid. As used herein, it is measured by the number of nucleotides that a polymerase incorporates into a nucleic acid (such as a sequencing primer) prior to dissociation of the polymerase from the primer/template hybrid. In some embodiments, the polymerase has a processivity of at least 100 nucleotides, although in other embodiments it has a processivity of at least 200 nucleotides, at least 300 nucleotides, at least 400 nucleotides, or at least 500 nucleotides. It will be understood by those of ordinary skill in the art that the higher the processivity of the polymerase, the more nucleotides that can be incorporated prior to dissociation, and therefore the longer the sequence that can be obtained. In other words, polymerases having low processivity will provide shorter read-lengths than will polymerases having higher processivity. As an example, a polymerase that dissociates from the hybrid after five incorporations will only provide a sequence of 5 nucleotides in length, while a polymerase that dissociates on average from the hybrid after 500 incorporations will provide sequence of about 500 nucleotides.

(529) The rate at which a polymerase incorporates nucleotides will vary depending on the particular application, although generally faster rates of incorporation are preferable. The rate of sequencing will depend on the number of arrays on chip, the size of the wells, the temperature and conditions at which the reactions are run, etc.

(530) In some embodiments of the invention, the time for a 4 nucleotide cycle may be 50-100 seconds, 60-90 seconds, or about 70 seconds. In other embodiments, this cycle time can be equal to or less than 70 seconds, including equal to or less than 60 seconds, equal to or less than 50 seconds, equal to or less than 40 seconds, or equal to or less than 30 seconds. A read length of about 400 bases may take on the order of 30 minutes, 60 minutes, 1.5 hours, 2 hours, 2.5 hours, 3 hours, 3.5 hours, 4 hours, 4.5 hours, or in some instance 5 or more hours. These times are sufficient for the sequencing of megabases, and more preferably gigabases of sequence, with greater amounts of sequence being attainable through the use of denser arrays (i.e., arrays with greater numbers of reaction wells and FETs) and/or the simultaneous use of multiple arrays.

(531) Table 3 provides estimates for the rates of sequencing based on various array, chip and system configurations contemplated herein. It is to be understood that the invention contemplates even denser arrays than those shown in Table 3. These denser arrays can be characterized as 90 nm CMOS with a pitch of 1.4 m and a well size of 1 m which may be used with 0.7 m beads, or 65 nm CMOS with a pitch of 1 m and a well size of 0.5 m which may be used with 0.3 m beads, or 45 m CMOS with a pitch of 0.7 m and a well size of 0.3 m which can be used with 0.2 m beads.

(532) TABLE-US-00003 TABLE 3 Reaction Parameters and Read Rates. chip type A B C D E pixel/CMOS 2.8 m/0.18 m 5.1 m/0.35 m 5.1 m/0.35 m 9 m/3.5 m 9 m/0.35 m chip size 17.5 17.5 17.5 17.5 12 12 17.5 17.5 12 12 # possible reads 27,800,000 7,220,000 2,950,000 2,320,000 1,060,000 read length (assumption) 400 400 400 400 400 # chips/board 4 4 4 4 4 bead load efficiency 0.80 0.80 0.80 0.80 0.80 # yielded Gbp* per run 35.6 9.2 3.8 3.0 1.4 # times HG** (3 Gbp/HG) 11.86 3.08 1.26 0.99 0.45 *Gbp is gigabases **HG is human genome

(533) The template nucleic acid is also contacted with other reagents and/or cofactors including but not limited to buffer, detergent, reducing agents such as dithiothrietol (DTT, Cleland's reagent), single stranded binding proteins, and the like before and/or while in the well. In one embodiment, the polymerase comprises one or more single stranded binding proteins (e.g., the polymerase may be one that is engineered to include one or more single stranded binding proteins). In one embodiment, the template nucleic acid is contacted with the primer and the polymerase prior to its introduction into the flow chamber and wells thereof.

(534) The primers may be DNA in nature or they may be modified moieties such as PNA or LNA, or they may comprise some other modification such as those described herein, or some combination of the foregoing. It has been found according to the invention that LNA-containing primers bind efficiently to DNA templates under stringent conditions and are still able to mediate a polymerase-mediated extension.

(535) Some reactions may be carried out at a pH equal to or greater than 7.5, equal to or greater than 8, equal to or greater than 8.5, equal to or greater than 9, equal to or greater than 9.5, equal to or greater than 10, or equal to or greater than 11. The polymerase may be one that incorporates nucleotides into a nucleic acid at a pH of 7-11, 7.5-10.5, 8-10, 8.5-9.5, or at about 9.

(536) In some embodiments, the enzyme has high activity in low concentrations of dNTPs. In some embodiments, the dNTP concentration is 50 M, 40 M, 30 M, 20 M, 10 M, 5 M, and preferably 20 M or less.

(537) Apyrase is an enzyme that degrades residual unincorporated nucleotides converting them into monophosphate and releasing inorganic phosphate in the process. It is useful for degrading dNTPs that are not incorporated and/or that are in excess. It is important that excess and/or unincorporated dNTP be washed away from all wells after measurements are complete and before introduction of the subsequent dNTP. Accordingly, addition of apyrase between the introduction of different dNTPs is useful to remove unincorporated dNTPs that would otherwise obscure the sequencing data.

(538) Thus, according to some aspects of the invention, a homogeneous population of (or a plurality of identical) template nucleic acids is placed into each of a plurality of wells, each well situated over and thus corresponding to at least one sensor. As discussed above, preferably the well contains at least 10, at least 100, at least 1000, at least 10.sup.4, at least 10.sup.5, at least 10.sup.6, or more copies of an identical template nucleic acid. Identical template nucleic acids means that the templates are identical in sequence. Most and preferably all the template nucleic acids within a well are uniformly hybridized to a primer. Uniform hybridization of the template nucleic acids to the primers means that the primer hybridizes to the template at the same location (i.e., the sequence along the template that is complementary to the primer) as every other template/primer hybrid in the well. The uniform positioning of the primer on every template allows the co-ordinated synthesis of all new nucleic acid strands within a well, thereby resulting in a greater signal-to-noise ratio.

(539) In some embodiments, nucleotides are then added in flow, or by any other suitable method, in sequential order to the flow chamber and thus the wells. The nucleotides can be added in any order provided it is known and for the sake of simplicity kept constant throughout a run.

(540) In some embodiments, the method involves adding ATP to the wash buffer so that dNTPs flowing into a well displace ATP from the well. The ATP matches the ionic strength of the dNTPs entering the wells and it also has a similar diffusion profile as dNTPs. In this way, influx and efflux of dNTPs during the sequencing reaction do not interfere with measurements at the chemFET. The concentration of ATP used is on the order of the concentration of dNTP used.

(541) In some embodiments, the dNTP and/or the polymerase may be pre-incubated with divalent cation such as but not limited to Mg.sup.2+ (for example in the form of MgCl.sub.2) or Mn.sup.2+ (for example in the form of MnCl.sub.2). Other divalent cations can also be used including but not limited to Ca.sup.2+, Co.sup.2+. This pre-incubation (and thus pre-loading of the dNTP and/or the polymerase can ensure that the polymerase is exposed to a sufficient amount of divalent cation for proper and necessary functioning even if it is present in a low ionic strength environment. Pre-incubation may occur for 1-60 minutes, 5-45 minutes, or 10-30 minutes, depending on the embodiment, although the invention is not limited to these time ranges.

(542) A sequencing cycle may therefore proceed as follows washing of the flow chamber (and wells) with wash buffer (optionally containing ATP), introduction of a first dNTP species (e.g., dATP) into the flow chamber (and wells), release and detection of PPi and then unincorporated nucleotides (if incorporation occurred) or detection of solely unincorporated nucleotides (if incorporation did not occur) (by any of the mechanisms described herein), washing of the flow chamber (and wells) with wash buffer, washing of the flow chamber (and wells) with wash buffer containing apyrase (to remove as many of the unincorporated nucleotides as possible prior to the flow through of the next dNTP, washing of the flow chamber (and wells) with wash buffer, and introduction of a second dNTP species. This process is continued until all 4 dNTP (i.e., dATP, dCTP, dGTP and dTTP) have been flowed through the chamber and allowed to incorporate into the newly synthesized strands. This 4-nucleotide cycle may be repeated any number of times including but not limited to 10, 25, 50, 100, 200 or more times. The number of cycles will be governed by the length of the template being sequenced and the need to replenish reaction reagents, in particular the dNTP stocks and wash buffers.

(543) As part of the sequencing reaction, a dNTP will be ligated to (or incorporated into as used herein) the 3 of the newly synthesized strand (or the 3 end of the sequencing primer in the case of the first incorporated dNTP) if its complementary nucleotide is present at that same location on the template nucleic acid. Incorporation of the introduced dNTP (and concomitant release of PPi) therefore indicates the identity of the corresponding nucleotide in the template nucleic acid. If no dNTP has been incorporated, no hydrogens are released and no signal is detected at the chemFET surface. One can therefore conclude that the complementary nucleotide was not present in the template at that location. If the introduced dNTP has been incorporated into the newly synthesized strand, then the chemFET will detect a signal. The signal intensity and/or area under the curve is a function of the number of nucleotides incorporated (for example, as may occur in a homopolymer stretch in the template. The result is that no sequence information is lost through the sequencing of a homopolymer stretch (e.g., poly A, poly T, poly C, or poly G) in the template.

(544) The sequencing reaction can be run at a range of temperatures. Typically, the reaction is run in the range of 30 C. to 70 C., 30 C. to 65 C., 30-60 C., 35-55 C., 40-50 C., or 40-45 C. It is preferable to run the reaction at temperatures that prevent formation of secondary structure in the nucleic acid. However this must be balanced with the binding of the primer (and the newly synthesized strand) to the template nucleic acid and the reduced half-life of apyrase at higher temperatures. The optimum temperature for the polymerase is also important as the closer the reaction is run to that temperature, the higher the nucleotide incorporation rate will be. Bst polymerase has a optimum temperature of about 65 C., while T4 polymerase has an optimum temperature of about 37 C. Thus, the optimum temperature will depend upon the polymerase being used. Some embodiments use a temperature of about 41 C. Other embodiments use a temperature that is higher including for example about 45 C., about 50 C. or about 65 C. The solutions, including the wash buffers and the dNTP solutions, are generally warmed to these temperatures in order not to alter the temperature in the wells. The wash buffer containing apyrase however is preferably maintained at a lower temperature in order to extend the half-life of the enzyme. Typically, this solution is maintained at about 4-15 C., and more preferably 4-10 C.

(545) As will be appreciated all of the foregoing methods may be automated such that the various biological and/or chemical reactions are performed via robotics. In addition, the information obtained via the signal from the chemFET (or chemFET array) may be provided to a personal computer, a personal digital assistant, a cellular phone, a video game system, or a television so that a user can monitor the progress of the sequencing reactions remotely. This process is illustrated, for example, in FIG. 71.

(546) Diffusion Control

(547) The nucleotide incorporation reaction can occur very rapidly. As a result, it may be desirable in some instances to slow the reaction down or to slow the diffusion of analytes in the well in order to ensure maximal data capture during the reaction. The diffusion of reagents and/or byproducts can be slowed down in a number of ways including but not limited to addition of packing beads in the wells, and/or the use of polymers such as polyethylene glycol in the wells (e.g., PEG attached to the capture beads and/or to packing beads). The packing beads also tend to increase the concentration of reagents and/or byproducts at the chemFET surface, thereby increasing the potential for signal. The presence of packing beads generally allows a greater time to sample (e.g., by 2- or 4-fold).

(548) Data capture rates can vary and be for example anywhere from 10-100 frames per second and the choice of which rate to use will be dictated at least in part by the well size and the presence of packing beads or other diffusion limiting techniques. Smaller well sizes generally require faster data capture rates.

(549) In some aspects of the invention that are flow-based and where the top face of the well is open and in communication with fluid over the entirety of the chip, it is important to detect the released hydrogen ion prior to its diffusion out of the well. Diffusion of reaction byproducts out of the well will lead to false negatives (because the byproduct is not detected in that well) and potential false positives in adjacent or downstream wells (where the byproduct may be detected), and thus should be avoided. Packing beads and/or polymers such as PEG may also help reduce the degree of diffusion and/or cross-talk between wells.

(550) In addition to the nucleic acid loaded beads, each well may also comprise a plurality of smaller beads, referred to herein as packing beads. The packing beads may be composed of any inert material that does not interact or interfere with analytes, reagents, reaction parameters, and the like, present in the wells. The packing beads may be magnetic (including superparamagnetic) but they are not so limited. In some embodiments the packing beads and the capture beads are made of the same material (e.g., both are magnetic, both are polystyrene, etc.), while in other embodiments they are made of different materials (e.g., the packing beads are polystyrene and the capture beads are magnetic).

(551) The packing beads are generally smaller than the capture beads. The difference in size may vary and may be 5-fold, 10-fold, 15-fold, 20-fold or more. As an example, 0.35 m diameter packing beads can be used with 5.91 m capture beads. Such packing beads are commercially available from sources such as Bang Labs.

(552) The placement of the packing beads relative to the capture bead may vary. Packing beads may be positioned between the chemFET surface and the nucleic acid loaded bead, in which case they may be introduced into the wells before the nucleic acid loaded beads. In this way, the packing beads prevent contact and thus interference of the chemFET surface with the template nucleic acids bound to the capture beads. A layer of packing beads that is 0.1-0.5 m in depth or height would preclude this interaction. The presence of packing beads between the capture bead and the chemFET surface may also slow the diffusion of the sequencing byproducts such as hydrogen ions, thereby facilitating data capture in some embodiments. Alternatively, the packing beads may be positioned all around the nucleic acid loaded beads, in which case they may be added to the wells before, during and/or after the nucleic acid loaded beads. In still other embodiments, the majority of the packing beads may be positioned on top of the nucleic acid loaded beads, in which case they may be added to the wells after the nucleic acid loaded beads. If placed above the nucleic acid loaded beads, the packing beads may act to minimize or prevent altogether dislodgement of nucleic acid loaded beads from wells. In still other embodiments, the reaction wells may comprise packing beads even if nucleic acid loaded beads are not used. It is to be understood that in other embodiments however packing beads are not required as there is no need to slow the diffusion of reaction byproducts such as hydrogen ions.

(553) In some embodiments, diffusion may also be impacted by including in the reaction chambers viscosity increasing agents. An example of such an agent is a polymer that is not a nucleic acid (i.e., a non-nucleic acid polymer). The polymer may be naturally or non-naturally occurring, and it may be of any nature provided it does not interfere with nucleotide incorporation and/or excision and detection thereof except for slowing the diffusion of polymerase, released hydrogen ions, PPi, unincorporated nucleotides, and/or other reaction byproducts or reagents. An example of a suitable polymer is polyethylene glycol (PEG). Other examples include PEO, PEA, dextrans, acrylamides, celluloses (e.g. methyl cellulose), and the like. The polymer may be free in solution (e.g., PEG, DMSO, glycerol, and the like) or it may be immobilized (covalently or non-covalently) to one or more sides of the reaction chamber, to the capture bead (e.g., PEG, PEO, dextrans, and the like), and/or to any packing beads that may be present. Non-covalent attachment may be accomplished via a biotin-avidin interaction.

(554) The invention further contemplates in some embodiments the use of soluble counterions that bind to released hydrogen ions and prevent their exit from the well. Counterions having a pKa that is close to the pH of the reaction are preferred. Examples of counterions with diffusion rates that are slower than that of protons (at both 25 C. and 37 C.) include without limitation Cl.sup., H.sub.2P04.sup., HCO3.sup., acetate, butyrate, histidyl, formate, lactate, and the like. In some embodiments, the counterions are free in solution while in others they are immobilized on a solid support including without limitation reaction chamber walls. One of ordinary skill in the art will be able to select the most appropriate counterion and concentration based on its pKa and the pH at which the reaction is conducted, and the mobility of the counterion. It will be understood that various embodiments of the invention do not require the use of counterions.

(555) Kits

(556) The invention further contemplates kits comprising the various reagents necessary to perform a sequencing reaction and instructions of use according to the methods set forth herein.

(557) One preferred kit comprises one or more containers housing wash buffer, one or more containers each containing one of the following reagents: dATP buffer, dCTP buffer, dGTP buffer or dTTP buffer, dATP, dCTP, dGTP and dTTP stocks, apyrase, SSB, polymerase, packing beads, and optionally pyrophosphatase. Importantly the kits may comprise only naturally occurring dNTPs. The kits may also comprise one or more wash buffers comprising components as described in the Examples, but are not so limited. The kits may also comprise instructions for use including diagrams that demonstrate the methods of the invention.

(558) The following Examples are included for purposes of illustration and are not intended to limit the scope of the invention.

EXAMPLES

(559) The Examples provide a proof of principle demonstration of the sequencing of four templates of known sequence. This artificial model is intended to show that embodiments of the apparatuses and systems described herein are able to readout nucleotide incorporation that correlates to the known sequence of the templates. This is not intended to represent typical use of the method or system in the field. The following is a brief description of these methods.

Example 1. Bead Preparation

(560) Binding of Single-Stranded Oligonucleotides to Streptavidin-Coated Magnetic Beads. Single-stranded DNA oligonucleotide templates with a 5 Dual Biotin tag (HPLC purified), and a 20-base universal primer were ordered from IDT (Integrated DNA Technologies, Coralville, Ind.). Templates were 60 bases in length, and were designed to include 20 bases at the 3 end that were complementary to the 20-base primer (Table 4, italics). The lyophilized and biotinylated templates and primer were re-suspended in TE buffer (10 mM Tris-HCl, 1 mM EDTA, pH 8) as 40 M stock solutions and as a 400 M stock solution, respectively, and stored at 20 C. until use.

(561) For each template, 60 l of magnetic 5.91 m (Bangs Laboratories, Inc. Fishers, Ind.) streptavidin-coated beads, stored as an aqueous, buffered suspension (8.5710.sup.4 beads/L), at 4 C., were prepared by washing with 120 l bead wash buffer three times and then incubating with templates 1, 2, 3 and 4 (T1, T2, T3, T4: Table 4) with biotin on the 5 end, respectively.

(562) Due to the strong covalent binding affinity of streptavidin for biotin (Kd10-15), these magnetic beads are used to immobilize the templates on a solid support, as described below. The reported binding capacity of these beads for free biotin is 0.650 pmol/L of bead stock solution. For a small (<100 bases) biotinylated ssDNA template, it was conservatively calculated that 9.110.sup.5 templates could be bound per bead. The beads are easily concentrated using simple magnets, as with the Dynal Magnetic Particle Concentrator or MPC-s (Invitrogen, Carlsbad, Calif.). The MPC-s was used in the described experiments.

(563) An MPC-s was used to concentrate the beads for 1 minute between each wash, buffer was then added and the beads were resuspended. Following the third wash the beads were resuspended in 120 L bead wash buffer plus 1 l of each template (40 M). Beads were incubated for 30 minutes with rotation (Labquake Tube Rotator, Barnstead, Dubuque, Iowa). Following the incubation, beads were then washed three times in 120 L Annealing Buffer (20 mM Tris-HCl, 5 mM magnesium acetate, pH 7.5), and re-suspended in 60 L of the same buffer.

(564) TABLE-US-00004 TABLE4 SequencesforTemplates1,2,3,and4 T1:5/52Bio/GCAAGTGCCCTTAGGCTTCAGTTCAAAAGTCCTAAC TGGGCAAGGCACACAGGGGATAGG-3 (SEQIDNO:1) T2:5/52Bio/CCATGTCCCCTTAAGCCCCCCCCATTCCCCCCTGAACCC CCAAGGCACACAGGGGATAGG-3 (SEQIDNO:2) T3:5/52Bio/AAGCTCAAAAACGGTAAAAAAAAGCCAAAAAACTGG AAAACAAGGCACACAGGGGATAGG-3 (SEQIDNO:3) T4:5/52Bio/TTCGAGTTTTTGCCATTTTTTTTCGGTTTTTTGACCTTT TCAAGGCACACAGGGGATAGG-3 (SEQIDNO:4)

(565) Annealing of Sequencing Primer. The immobilized templates, bound at the 5 end to 5.91 m magnetic beads, are then annealed to a 20-base primer complementary to the 3 end of the templates (Table 4). A 1.0 L, aliquot of the 400 M primer stock solution, representing a 20-fold excess of primer to immobilized template, is then added and then the beads plus template are incubated with primer for 15 minutes at 95 C. and the temperature was then slowly lowered to room temperature. The beads were then washed 3 times in 120 L of 25 mM Tricine buffer (25 mM Tricine, 0.4 mg/ml PVP, 0.1% Tween 20, 8.8 mM Magnesium Acetate; ph 7.8) as described above using the MPC-s. Beads were resuspended in 25 mM Tricine buffer.

(566) Incubation of Hybridized Templates/Primer with DNA Polymerase.

(567) Template and primer hybrids are incubated with polymerase essentially as described by Margulies et al. Nature 2005 437(15):376-380 and accompanying supplemental materials.

(568) Loading of Prepared Test Samples onto the ISFET Sensor Array.

(569) The dimensions and density of the ISFET array and the microfluidics positioned thereon may vary depending on the application. A non-limiting example is a 512512 array. Each grid of such an array (of which there would be 262144) has a single ISFET. Each grid also has a well (or as they may be interchangeably referred to herein as a microwell) positioned above it. The well (or microwell) may have any shape including columnar, conical, square, rectangular, and the like. In one exemplary conformation, the wells are square wells having dimensions of 7710 m. The center-to-center distance between wells is referred to herein as the pitch. The pitch may be any distance although it is preferably to have shorter pitches in order to accommodate as large of an array as possible. The pitch may be less than 50 m, less than 40 m, less than 30 m, less than 20 m, or less than 10 m. In one embodiment, the pitch is about 9 m. The entire chamber above the array (within which the wells are situated) may have a volume of equal to or less than about 30 L, equal to or less than about 20 L, equal to or less than about 15 L, or equal to or less than 10 L. These volumes therefore correspond to the volume of solution within the chamber as well.

(570) Loading of Beads in an Open System.

(571) Beads with templates 1-4 were loaded on the chip (10 L, of each template). Briefly, an aliquot of each template was added onto the chip using an Eppendorf pipette. A magnet was then used to pull the beads into the wells.

(572) Loading of Beads in a Closed System.

(573) Both the capture beads the packing beads are loaded using flow. Microliter precision of bead solution volume, as well as positioning of the bead solution through the fluidics connections, is achieved as shown in FIGS. 62-70 using the bead loading fitting, which includes a major reservoir (approx. 1 mL in volume), minor reservoir (approx. 10 L in volume), and a microfluidic channel for handling small volumes of bead solution. This method also leverages the microliter precision of fluid application allowed by precision pipettes.

(574) The chip comprising the ISFET array and flow cell is seated in the ZIF (zero insertion force) socket of the loading fixture, then attaching a stainless steel capillary to one port of the flow cell and flexible nylon tubing on the other port. Both materials are microfluidic-type fluid paths (e.g., on the order of <0.01 inner diameter). The bead loading fitting, consisting of the major and minor reservoirs, it attached to the end of the capillary. A common plastic syringe is filled with buffer solution, then connected to the free end of the nylon tubing. The electrical leads protruding from the bottom of the chip are inserted into a socket on the top of a fixture unit (not shown).

(575) The chip comprising the ISFET array and flow cell is seated in a socket such as a ZIF (zero insertion force) socket of the loading fixture, then a stainless steel capillary may be attached to one port of the flow cell and flexible nylon tubing on the other port. Both materials are microfluidic-type fluid paths (e.g., on the order of <0.01 inner diameter). The bead loading fitting, consisting of the major and minor reservoirs, it attached to the end of the capillary. A common plastic syringe is filled with buffer solution, then connected to the free end of the nylon tubing. The electrical leads protruding from the bottom of the chip are inserted into a socket on the top of a fixture unit (not shown).

(576) It will be appreciated that there will be other ways of drawing the beads into the wells of the flow chamber, including centrifugation or gravity. The invention is not limited in this respect.

(577) DNA Sequencing Using the ISFET Sensor Array in an Open System.

(578) A illustrative sequencing reaction can be performed in an open system (i.e., the ISFET chip is placed on the platform of the ISFET apparatus and then each nucleotide (5 L resulting in 6.5 M each) is manually added in the following order: dATP, dCTP, dGTP and dTTP (100 mM stock solutions, Pierce, Milwaukee, Wis.), by pipetting the given nucleotide into the liquid already on the surface of the chip and collecting data from the chip at a rate of 2.5 MHz. This can result in data collection over 7.5 seconds at approximately 18 frames/second. Data may then analyzed using Lab View.

(579) Given the sequences of the templates, it is expected that addition of dATP will result in a 4 base extension for template 4. Addition of dCTP will result in a 4 base extension in template 1. Addition of dGTP will cause template 1, 2 and 4 to extend as indicated in Table 5 and addition of dTTP will result in a run-off (extension of all templates as indicated).

(580) Preferably when the method is performed in a non-automated manner (i.e., in the absence of automated flow and reagent introduction), each well contains apyrase in order to degrade the unincorporated dNTPs, or alternatively apyrase is added into each well following the addition and incorporation of each dNTP (e.g., dATP) and prior to the addition of another dNTP (e.g., dTTP). It is to be understood that apyrase can be substituted, in this embodiment or in any other embodiment discussed herein, with another compound (or enzyme) capable of degrading dNTPs.

(581) TABLE-US-00005 TABLE 5 Set-up of experiment and order of nucleotide addition. dATP dCTP dGTP dTTP T1 0 (3:C; 1:A)4 1 Run-off (25) T2 0 0 4 Run-off (26) T3 0 0 0 Run-off (30) T4 4 0 2 Run-off (24)

(582) DNA Sequencing Using Microfluidics on Sensor Chip.

(583) Sequencing in the flow regime is an extension of open application of nucleotide reagents for incorporation into DNA. Rather than add the reagents into a bulk solution on the ISFET chip, the reagents are flowed in a sequential manner across the chip surface, extending a single DNA base(s) at a time. The dNTPs are flowed sequentially, beginning with dTTP, then dATP, dCTP, and dGTP. Due to the laminar flow nature of the fluid movement over the chip, diffusion of the nucleotide into the microwells and finally around the nucleic acid loaded bead is the main mechanism for delivery. The flow regime also ensures that the vast majority of nucleotide solution is washed away between applications. This involves rinsing the chip with buffer solution and apyrase solution following every nucleotide flow. The nucleotides and wash solutions are stored in chemical bottles in the system, and are flowed over the chip using a system of fluidic tubing and automated valves. The ISFET chip is activated for sensing chemical products of the DNA extension during nucleotide flow.

Example 2. On-Chip Polymerase Extension Detected by pH Shift on an ISFET Array

(584) Streptavidin-coated 2.8 micron beads carrying biotinylated synthetic template to which sequencing primers and T4 DNA polymerase are bound were subjected to three sequential flows of each of the four nucleotides. The template sequence downstream of the sequencing primer was a G(C)10(A) 10 (SEQ ID N0:5). Each nucleotide cycle consisted of flows of dATP, dCTP, dGTP and dTTP, each interspersed with a wash flow of buffer only. Flows from the first cycle are shown in blue, flows from the second cycle in red, and the third cycle in yellow. As shown in FIG. 72A, signal generated for both of the two dATP flows were very similar. FIG. 72B shows that the first (blue) trace of dCTP is higher than the dCTP flows from subsequent cycles, corresponding to the flow in which the polymerase should incorporate a single nucleotide per template molecule. FIG. 72C shows that the first (blue) trace of dGTP is approximately 6 counts higher (peak-to-peak) than the dGTP flows from subsequent cycles, corresponding to the flow in which the polymerase should incorporate a string of 10 nucleotides per template molecule. FIG. 72D shows that the first (blue) trace of dTTP is also approximately 6 counts higher (peak-to-peak) than the dTTP flows from subsequent cycles, corresponding to the flow in which the polymerase should incorporate 10 nucleotides per template molecule.

Example 3. Sequencing in a Closed System and Data Manipulation

(585) Sequence has been obtained from a 23-mer synthetic oligonucleotide and a 25-mer PCR product oligonucleotide. The oligonucleotides were attached to beads which were then loaded into individual wells on a chip having 1.55 million sensors in a 13481152 array having a 5.1 micron pitch (38400 sensors per mm.sup.2) About 1 million copies of the synthetic oligonucleotide were loaded per bead, and about 300000 to 600000 copies of the PCR product were loaded per bead. A cycle of 4 nucleotides through and over the array was 2 minutes long. Nucleotides were used at a concentration of 50 micromolar each. Polymerase was the only enzyme used in the process. Data were collected at 32 frames per second.

(586) FIG. 73A depicts the raw data measured directly from an ISFET for the synthetic oligonucleotide (SE ID NO:6). One millivolt is equivalent to 68 counts. The data are sampled at each sensor on the chip (1550200 sensors on a 314 chip) many times per second. The Figure is color-coded for each nucleotide flow. With each nucleotide flow, several seconds of imaging occur. The graph depicts the concatenation of those individual measurements taken during each flow. The Y axis is in raw counts, and the X axis is in seconds. Superimposed just above the X axis are the expected incorporations at each flow.

(587) FIG. 73B depicts the integrated value for each nucleotide flow, normalized to the template being sequenced. The integrated value is taken from the raw trace measurements shown in FIG. 73A, and the integral bounds have been chosen to maximize signal to noise ratio. The results have been normalized to the signal per base incorporation, and graphed per nucleotide flow. The Y axis is incorporation count, and the X axis is nucleotide flow number, alternating through TACG.

(588) FIGS. 74A and 74B represent the same type of measurements taken and shown in FIGS. 73A and 73B, with the exception that the signal being detected here is from a PCR product (the 25-mer oligonucleotide, SEQ ID NO:7), rather than a synthetic oligonucleotide.

(589) Improving Pixel and Array Signal-to-Noise Ratio

(590) The reliability of signal decoding from each ISFET and from the ISFET array as a whole is dependent on the amplitude of the signal output by each ISFET, and its respective signal-to-noise ratio. Some changes to the foregoing fabrication methods, judicious materials selection, and changes to pixel and array design can be employed to increase considerably the output of the ISFETs in the array and decrease various noise sources. That is, these changes result in a more sensitive and more accurate sensor array. The improvements can be implemented individually or in various combinations, and can result in significant performance gains to the signal-to-noise ratio (SNR).

(591) As more fully discussed below, the improvements involve: (1) over-coating (i.e., passivating) the sidewalls (typically formed of TEOS-oxide or another suitable material, as above-described) and sensor surface at the bottom of the microwells with various metal oxide or like materials, to improve their surface chemistry (i.e., make the sidewalls less reactive) and electrical properties; (2) thinning out the coating (deposition material) on the floating gate; (3) increasing the surface area for charge collection at the floating gate; (4) and modified array and pixels designs to reduce charge injection into the electrolyte and other noise sources.

(592) Floating Gate Deposition Layer Material and Thickness

(593) As illustrated in FIG. 75A, it is now appreciated that if a dielectric layer is added over the floating gate structure of the ISFET sensor arrangement, the path from the analyte to the ISFET gate may be modeled as a series connection of three capacitances: (1) the capacitance attributable to the above-described charge double layer at the analyte dielectric layer interface (labeled C.sub.DL), (2) the capacitance due to the floating gate dielectric layer (C.sub.FGD), and (3) the gate oxide capacitance (C.sub.ox). (Note that in the text above, the floating gate dielectric layer is sometimes referred to as a passivation layer. Here, we refer more specifically to the layer as a floating gate dielectric layer in order to avoid any suggestion that the material composition of the layer is necessarily related to the so-called passivation material(s) often used in CMOS processing (e.g., PECVD silicon nitride) to coat and protect circuit elements.) The series capacitance string extends between the liquid analyte 75-1 in the wells and the ISFET gate 75-2.

(594) It is well known that capacitances in series form a capacitive voltage divider. Consequently, only a fraction of the signal voltage, V.sub.S, generated by or in the analyte, is applied to the gate oxide as the voltage V.sub.G that drives the ISFET. If we define the gate gain as V.sub.G/V.sub.S, one would ideally like to have unity gaini.e., no signal loss across any of the three capacitances. Of course, unity gain is not achievable, but the actual gate gain can be optimized. The value of C.sub.DL is a function of material properties and is typically on the order of about 10-40 g/cm.sup.2. The gate oxide capacitance is typically a very small value by comparison. Thus, by making C.sub.FGD much greater than the series combination of C.sub.OX and C.sub.DL (for short, C.sub.FGD>>C.sub.OX), the gate gain can be made to approach unity as closely as is practical.

(595) To achieve the relationship C.sub.FGD>>C.sub.OX, one can minimize C.sub.OX, maximize C.sub.FGD, or both. There is not a lot that can be done to alter the gate oxide capacitance much when using standard CMOS foundry techniques to fabricate the ISFETs. That is, for practical reasons one must typically accept the gate oxide capacitance value as a given. Thus, emphasis may be placed on maximizing C.sub.FGD. Such maximization can be achieved by using a thin layer of high dielectric constant material, or by increasing the area of the floating gate metallization. Since increasing floating gate area conflicts with a goal of having a high density sensor array, attention has been focused on the dielectric layer.

(596) Materials exist and may be used that have higher dielectric constants than the customary CMOS gate oxide material, silicon dioxide. So, if in the course of fabrication such a gate oxide material has been deposited onto the floating gate metallization, one may etch away that material, essentially eliminating it, and deposit a suitable high dielectric constant floating gate dielectric layer directly onto the floating gate metallization. Or, one may simply deposit such a floating gate dielectric layer directly onto the floating gate metallization without having to etch first. In either situation, there are then only two series capacitances that matter between the analyte and the ISFET gate, C.sub.DL and C.sub.FGD. Gate gain can then be maximized by making C.sub.FGD>>C.sub.DL. Thus, achieving a large value for C.sub.FGD is desirable, while also satisfying other requirements (e.g., reliable manufacture).

(597) The capacitance C.sub.FGD is essentially formed by a parallel plate capacitor having the floating gate dielectric layer as its dielectric. Consequently, for a given plate (i.e., floating gate metallization) area, the parameters principally available for increasing the value of C.sub.FGD are (1) the thickness of the dielectric layer and (2) the selection of the dielectric material and, hence, its dielectric constant. The capacitance of the floating gate dielectric layer varies directly with its dielectric constant and inversely with its thickness. Thus, a thin, high-dielectric-constant layer would be preferred, to satisfy the objective of obtaining maximum gate gain.

(598) One candidate for the floating gate dielectric layer material is the passivation material used by standard CMOS foundry processes. The standard (typically, PECVD nitride or, to be more precise, silicon nitride over silicon oxynitride) passivation layer is relatively thick when formed (e.g., about 1.3 m), and typical passivation materials have a limited dielectric constant. A first improvement can be achieved by thinning the passivation layer after formation. This can be accomplished by etching back the CMOS passivation layer, such as by using an over-etch step during microwell formation, to etch into and consume much of the nitride passivation layer, leaving a thinner layer, such as a layer only about 200-600 Angstroms thick. While simple, this approach is prone to wafer-to-wafer etch variations, resulting in variability in the final passivation layer thickness and capacitance.

(599) Two approaches have been at least partially evaluated for etching a standard CMOS passivation layer of silicon nitride deposited over silicon oxynitride. We call the first approach the partial etch technique. It involves etching away the silicon nitride layer plus approximately half of the silicon oxynitride layer before depositing the thin-film metal oxide sensing layer. The second approach we call the etch-to-metal technique. It involves etching away all of the silicon nitride and silicon oxynitride layers before depositing the thin-film metal oxide sensing layer. Theoretical modeling indicates that the partial etch approach should lead to an ISFET gate gain of about 0.42. This corresponds to an increase of signal level by about 50% compared with a non-etched passivation layer. With an ALD Ta.sub.2O.sub.5 thin-film sensing layer deposited over a partial etch, ISFET gains from about 0.37 to about 0.43 have been obtained empirically, with sensor sensitivities of about 15.02-17.08 mV/pH.

(600) Theoretical modeling indicates that in the etch-to-metal approach with the same sensing layer, an ISFET gate gain of about 0.94 should be possible. This would correspond to a greater than three-fold increase in signal. With an imperfect etch process that does not produce a uniform etch across the surface of the floating gate, the empirically obtained gain has only been about 0.6, corresponding to a little more than doubling of the signal. With improved etch chemistry/process to obtain a more uniform and flat surface at the bottom of the well, a gain close to the model 0.94 gain should be possible.

(601) One promising approach for improving the uniformity and flatness of the etch process is to perform two or more separate etches in seriesi.e., use a multi-step etch process. A first etch step may be performed and the progress of that etch step may be monitored optically, at one or multiple wavelengths. When it is detected that the first step etch has exposed a part of the underlying metal surface, the first etch process can be stopped and a second process or step may be begun, using conditions that will remove the dielectric material without removing (much of) the metal.

(602) An alternative to use of the foregoing etch processes is to simply deposit a thinner layer of dielectric (passivation) material in the first place, such as the indicated 200-600 Angstroms instead of the 1.3 m of the conventional CMOS passivation process. Even better performance can be achieved with the use of other materials and deposition techniques to form a thin dielectric layer, preferably one of relatively higher dielectric constant. Among the materials believed useful for the floating gate dielectric layer are metal oxides such as tantalum oxide, tungsten oxide, aluminum oxide, and hafnium oxide, though other materials of dielectric constant greater than that of the usual silicon nitride passivation material may be substituted, provided that such material is sensitive to the ion of interest. The etch-to-metal approach is preferred, with the CMOS process' passivation oxide on the floating gate being etched completely away prior to depositing the floating gate dielectric material layer. That dielectric layer may be applied directly on the metal extended ISFET floating gate electrode. This will help maximize the value of the capacitance C.sub.FGD.

(603) The etch-to-metal approach is preferred, with the CMOS process' passivation oxide on the floating gate being etched completely away prior to depositing the floating gate dielectric material layer. That dielectric layer may be applied directly on the metal extended ISFET floating gate electrode. This will help maximize the value of the capacitance C.sub.FGD.

(604) Among the processes which may be used for depositing a thin layer of floating gate dielectric material are reactive or non-reactive sputtering, electron cyclotron resonance (ECR), e-beam evaporation, and atomic layer deposition (ALD), though any suitable technique may be employed. Each of the foregoing processes has well known characteristics. Importantly, however, these processes differ in their abilities to provide conformal and uniform films, which are qualities that may be important for some applications. Thus, all are usable, but they are not necessarily equally desirable. Of the four enumerated techniques, ALD appears to be superior with respect to the particular desired qualities. It is good for depositing layers whose thickness can be controlled precisely so that wafer-to-wafer repeatability is not a problem. Also, it is a low-temperature process that does not threaten the aluminum interconnects that typically already will have been formed on the wafer by the time the floating gate dielectric material layer is applied. ALD, moreover, promises to enable conformal, pinhole-free and crack-free film coverage on the well bottom, which is required; and it is compatible with extending the deposition from the well bottoms onto the high aspect ratio (i.e., steep) well sidewalls. Covering the sidewalls with a passivation or buffering layer will render them more inert to the analyte.

(605) To create such structures, a layer of microwells should be formed on top of the ISFETs wherein the microwells are open at their bottoms. If the structure is to be formed without a floating gate dielectric layer other than a conventional passivation material over the floating gate, then the passivation material preferably should be partially etched down to the desired thinness. This alone increases the floating gate dielectric capacitance C.sub.FGD relative to C.sub.OL, improving gate gain. Optionally, a thin, higher-dielectric constant layer may be deposited or otherwise formed over such passivation material.

(606) The deposited layer should preferably be relatively thine.g., only about 200-600 Angstroms thick, possibly even less. As the thin layer of floating gate dielectric material is deposited over the well bottom onto the floating gate or its immediate coating layer, it also may be allowed to deposit conformally over the well sidewalls using, for example, the aforementioned ALD process.

(607) The potential for improvement is considerable. As a starting point, consider one standard CMOS foundry passivation material, silicon nitride, Si.sub.3N.sub.4. This particular material has a sub-Nernstian response to pH. Consequently, the best response we have been able to measure is about 40 mV/pH for an ISFET sensor with a silicon nitride floating gate deposition layer (though some improvement might be obtainable with improved nitride deposition). This is considerably less than the ideal Nernstian response of 59 mV/pH at 25 C. Thus, about one-third of the signal voltage at the interface between the analyte and the floating gate deposition layer is lost due to use of materials with so great a sub-Nernstian response. Indeed, in one example, simulations indicated that a three-fold improvement in gate gain is possible with changes in both floating gate deposition material and floating gate deposition layer thickness, for the gate geometries studied. This was then corroborated empirically with electrical test results on a 400 Angstrom aluminum oxide (Al.sub.2O.sub.3) floating gate deposition material.

(608) From available literature or experimentation, one can determine that in addition to Al.sub.2O.sub.3, there are other metal oxides that can be substituted for silicon nitride at the well bottom, to obtain a closer to Nernstian response. For example, Table 6 compares the pH response of ISFETs with various floating gate deposition oxides (specifically, SiO.sub.2, Si.sub.3N.sub.4, Al.sub.2O.sub.3 and Ta.sub.2O.sub.5, using published data.

(609) TABLE-US-00006 TABLE 6 Characteristic SiO.sub.2 Si.sub.3N.sub.4 Al.sub.2O.sub.3 Ta.sub.2O.sub.5 pH range 4-10 1-13 1-13 1-13 Sensitivity (mV/pH) 23-35 (pH > 7) 46-56 53-57 56-57 37-48 (pH < 7) Sensitivity (mV/pX) Na+ 30-50 5-20 2 <1 K+ 20-30 5-25 2 <1 Response time (95%) (s) 1 <0.1 <0.1 <0.1 (98%) (min) Undefined 4-10 2 1 Drift (mV/hr, pH 1-7) Unstable 1.0 0.1-0.2 0.1-0.2

(610) Of the four materials compared in Table 6, SiO.sub.2 had the lowest sensitivity to pH and no linear dependence on pH. The literature indicated that Si.sub.3N.sub.4 had higher sensitivities (46-56 mV/pH) but experiments have shown its performance to be dependent on the type of deposition technique and oxygen content. The best reported materials were Al.sub.2O.sub.3 and Ta.sub.2O.sub.5, which exhibited higher sensitivity in the ranges of 53-57 and 56-57 mV/pH, respectively. One other study has indicated that tungsten oxide, WO.sub.3, a material with a high dielectric constant (about 300), has a sensitivity of 50 mV/pH.

(611) Consequently, the data indicates that using a floating gate deposition material such as Ta.sub.2O.sub.5, Al.sub.2O.sub.3, HfO.sub.3 or WO.sub.3 will result in a larger signal in response to pH changes. In other words, if it is assumed that the sensitivity of Ta.sub.2O.sub.5 is 56 mV/pH and that the Nernstian gain is defined as the material sensitivity divided by the ideal Nernstian response of 59 mV/pH at 25 C., then the Nernstian gain increases from 0.67 for Si.sub.3N.sub.4 to about 0.95-0.96 for Ta.sub.2O.sub.5. Thus, with Ta.sub.2O.sub.5, only about 4-5% of the signal voltage is lost across the floating gate deposition layer.

(612) The deposition of a thin film floating gate deposition layer over the side walls of the microwells provides a further benefit. By coating the walls with a material whose pKa value is more conducive to analyte pH conditions than the TEOS oxide sidewall above mentioned, the floating gate deposition material buffers the sidewalls so that surface reactions there capture fewer of the protons that otherwise would be available as signal generators once they reach the gate region.

(613) Thus, the above-taught thin-film floating gate deposition layers provide a three-fold benefit: First, they enhance sensor performance at the sensor surface by providing a more reactive interface between the analyte and the ISFET gate (or, in other words, they are more Nernstian). Second, they serve as a replacement, thinner dielectric between the analyte and the metal ISFET gate (if directly applied to the metal) or between the analyte and the gate oxide (if applied over a gate oxide layer), thereby increasing the coupling capacitance and gate gain. Third, if also used to cover the microwell sidewalls, as would be typical for most deposition processes, they provide buffering by coating the TEOS-oxide sidewalls with a material whose pKa differs more substantially from the analyte pH than that of the sidewall material itself.

(614) There are also materials such as Iridium oxide which provide super-Nernstian responses, which can provide a still further improvement in SNR if used as the thin film floating gate deposition layer. See, e.g., D. O. Wipf et al, Microscopic Measurement of pH with Iridium Oxide Microelectrodes, Anal. Chem. 2000, 72, 4921-4927, and Y. J. Kim et al, Configuration for Micro pH Sensor, Electronics Letters, Vol. 39, No. 21 (Oct. 16, 2003).

(615) FIGS. 75B-D model the dependence of gate gain on floating gate deposition layer thickness and material, assuming use of a conventional gate oxide, under differing conditions. The conditions for FIG. 75B are given in Table 7, below:

(616) TABLE-US-00007 TABLE 7 Gate oxide thickness (m) 7.70E09, typ. ISFET gate length (m) 6.00E07 ISFET gate width (m) 1.20E06 ISFET gate area (m2) 7.20E13 ISFET gate capacitance (F) 3.23E15 ISFET sensor plate side length (m) 6.00E06 ISFET sensor plate area (m2) 3.60E11 ISFET sensor plate capacitance (F) 1.84E15

(617) The conditions for FIG. 75C are given in Table 8, below:

(618) TABLE-US-00008 TABLE 8 Gate oxide thickness (m) 7.70E09, typ. ISFET gate length (m) 5.00E07 ISFET gate width (m) 1.20E06 ISFET gate area (m2) 6.00E13 ISFET gate capacitance (F) 2.69E15 ISFET sensor plate side length (m) 3.50E06 ISFET sensor plate area (m2) 1.23E11 ISFET sensor plate capacitance (F) 6.25E16

(619) The conditions for FIG. 75D are given in Table 9, below:

(620) TABLE-US-00009 TABLE 9 Gate oxide thickness (m) 3.80E09 ISFET gate length (m) 4.00E07 ISFET gate width (m) 7.00E07 ISFET gate area (m2) 2.80E13 ISFET gate capacitance (F) 2.54E15 ISFET sensor plate side length (m) 1.60E06 ISFET sensor plate area (m2) 2.56E12 ISFET sensor plate capacitance (F) 9.71E17

(621) The deposited ALD thin film layers discussed above, like all deposited thin-films, have an intrinsic stress and stress gradient resulting from material properties and/or deposition conditions. These properties can affect the adhesion of the deposited film to the underlying substrate (the floating gate metallization and microwell sidewalls). In the fabrication examples above, various metal-oxide ceramic materials are to be deposited onto silicon dioxide (i.e., the TEOS material of the microwells), silicon nitride (i.e., the remaining CMOS passivation material that has been etched through but which is still present on the bottom of the sidewalls) and aluminum (i.e., the metal ISFET floating gate electrode).

(622) Some ALD processes involve depositing materials at temperatures below 400 C.; others, at temperatures above 400 C. As described above, an end-of-line forming gas anneal above 400 C. may be employed as part of the CMOS trapped charge neutralization process. The ALD layers deposited at temperatures less than this tend to delaminate or spall off the silicon dioxide sidewalls. It has been found empirically that Ta.sub.2O.sub.5 (deposited at 325 C.) spalls off the well sidewalls and Al.sub.2O.sub.3 (deposited at 460 C.) does not.

(623) Two methods are proposed to correct this problem, as applied to fabricating an optimum microwell passivation/floating gate dielectric (protection) material into a microwell and onto an ISFET sensor gate. In a first method, a laminated film may be used to relieve the stress in the as-deposited metal oxide ceramic. In a second method, a glue layer is first deposited, having superior adhesion onto which a microwell passivation/floating gate dielectric (protection) material of optimum surface chemistry is deposited.

(624) As an example, the laminate layer may be an approximately 400 Angstrom thick structure of alternating layers of Ta.sub.2O.sub.5, and Al.sub.2O.sub.3, (for instance, but not limited to, each about 10-20 Angstroms thick, or of different thicknesses). It is believed to be preferable to start with Al.sub.2O.sub.3 (as it exhibits better adhesion to oxide) and terminate with Ta.sub.2O.sub.5, (for its superior surface chemistry). The ALD process is ideally suited to this as film thicknesses can be controlled down to the atomic layer (i.e., a few Angstroms) and can be switched easily from one material to another simply by switching the precursor gasses introduced into the reactor system.

(625) The overall stress of such a laminate layer would be a combination of the intrinsic stressescompressive and tensileof the individual layers. More than two materials could be used if, say, a tertiary laminate were required.

(626) The glue layer idea is a more straight-forward implantation. First, a very thin (e.g., 50 Angstrom) layer of good adherent material (e.g., high temperature Al.sub.2O.sub.3) may be deposited and then immediately following that, a thicker (e.g., 400 Angstrom) layer of Ta.sub.2O.sub.5.

(627) Increasing Floating Gate Surface Area

(628) The various metal oxide materials discussed above for improving the surface properties both of the well surface and/or of the sensor surface at the bottom of the well are not electrically conductive. However, one can create an extended floating gate electrode underneath such material, extending the electrically conductive properties of the ISFET gate electrode, by first depositing and planarize-etching a thin conformal metal coating prior to the passivation layer deposition. The removal via CMP (chemical-mechanical polishing) or other etch techniques of the thin-metal from the tops of the microwells would realize discrete electrically isolated wells having passivated gates consisting of substantially the entire interior surface area of the microwell sidewalls. This would increase the available surface area of the ISFET gate several fold. Doing so would virtually eliminate lost protons at microwell walls (i.e., those protons emanating from the sequencing reaction on the bead and otherwise hitting the non-sensing microwell wall).

(629) The extended floating gate dielectric capacitor would be formed (by, e.g., ALD) after microwell etch. Adjustments to the microwell lateral dimensions could be necessary, depending on the thickness of the thin-metal plus passivation layers being deposited, and the bead size.

(630) FIG. 75E depicts diagrammatically two microwells 75E1 and 75E2 being formed with such an extended floating gate structure. As will become clear in a moment, the structures of FIG. 75E are in a partial state of completion. With reference to FIG. 75E, one possible sequence for fabricating the microwell structure with an extended gate electrode could be as follow: After forming the layer 75E3 of material (e.g., TEOS) which will provide the microwell walls, on top of a CMOS wafer wherein the ISFET structures have been formed, the areas that will become the wells are etched down to the metal layer, labeled M4, constituting the floating gate of the ISFETs. (Or, alternatively, if as stated above the microwells are formed directly in the CMOS passivation layer, layer 75E3 can be omitted and this and other passages referring to such a layer can be understood to refer instead to the passivation layer and formation of the microwells in the passivation layer, instead.) Next, using a process such as sputtering or ALD, a thin layer of metal (e.g., about 0.25-0.50 m of aluminum, titanium, tantalum or other suitable material) is deposited to form a layer 74E4 in contact with the M4 layer, running over the bottom of the well and up the sidewalls. The thin metal layer will also cover the tops of the (e.g., TEOS) material between the microwells, forming an electrical short circuit between the wells, which will have to be removed. Next, one may optionally fill the wells with a suitable material such as various organic fill materials that are readily available, to prevent the next step from leaving unwanted debris in the microwells. The next step is to employ CMP or another suitable technique to planarize the top of the structure down to a level that exposes the tops of the microwells and the material layer 75E4 on the top of the sidewalls. Having thus exposed the metal layer 75E4, that metal is removed from the tops of the microwell array (especially the tops of the sidewalls and TEOS between the sidewalls) in any satisfactory way). For example, the metal 75E4 at the top of the microwell structure (i.e., on the exterior top of the sidewalls) may be etched away or removed using metal CMP to further planarize the tops of the wells. Having removed the short circuit between the wells, the filler material, if used, is then removed. The extended gate metallization is then covered by application of the thin dielectric layer discussed above, 75E5, such as a tantalum pentoxide (Ta.sub.2O.sub.5) ALD passivation, using ALD, for example. The dielectric/passivation must cover all edges of layer 75E5 to avoid electrically short-circuiting wells via the analyte fluid.

(631) As an alternate fabrication process, the removal of material 75E4 could be done by patterning an inverse of the microwell pattern as a mask (i.e., opening the areas between the wells) and then using a standard metal etch.

(632) The collection of all charge that reaches the microwell sidewalls, as well as its bottom, renders the pixels more sensitive to the reaction in the wells.

(633) Another way to improve charge collection and sensitivity is to employ for the surfaces contacting the electrolyte a material that has a point of zero charge that matches the operating pH of the analyte.

(634) Improved On-Chip Electronics

(635) There are two key areas where the on-chip electronics can potentially be improved to increase the voltage signal gain and to reduce noise: the pixel circuit and the readout circuit.

(636) Pixel Circuit

(637) In a basic pixel circuit such as is illustrated above in FIG. 9, for example, the bulk potential of the ISFET 150 is taken to the highest circuit potential. Unfortunately, the threshold voltage V.sub.T of the device is affected by the potential difference between the source and bulk, VSB. This phenomenon is known as the body effect and is modeled as:
V.sub.T=V.sub.T0+({square root over ((2|.sub.F|+V.sub.SB))}{square root over (2|.sub.F|)}

(638) where V.sub.T0 is the threshold voltage when the source voltage is equal to the bulk potential, 2 is the surface potential at threshold, and is the body effect coefficient. Consequently, the threshold voltage will vary due to the body effect; and the ISFET source gain, defined as the ratio VS/VG, will be less than the ideal value of unity. Although it cannot be measured directly, it is thought that the ISFET source gain is in the neighborhood of 0.9. In other words, up to 10% of the maximum voltage signal that could be measured may be lost due to the body effect.

(639) If each ISFET is placed in its own n-well, and the source and bulk terminals are connected together, then the body effect can be eliminated and an ISFET source gain of unity can be realized. Furthermore, if each ISFET is isolated from the rest of the chip by a reverse-biased diode between the n-well and the substrate, then the device will be less susceptible to substrate noise. In other words, the total ISFET noise should be lower if the device is located in its own n-well.

(640) Reducing Injection of Noise into Electrolyte

(641) A second aspect to improving the SNR is that of reducing noise. A major component of such noise is noise that is coupled into the analyte fluid by the pixels in every column of the array, due to the circuit dynamics. Two noise injection mechanisms have been identified: the drain side column buffer injects noise through each pixel and each row selection pumps charge into the fluid. These mechanisms are focused on the ISFET drain and on the ISFET source.

(642) The ISFET Drain Problem

(643) When a row is selected in the array, the drain terminal voltage shared between all of the ISFETs in a column moves up or down (as a necessary requirement of the source-and-drain follower). This changes the gate-to-drain capacitances of all of the unselected ISFETs in the column. In turn, this change in capacitance couples from the gate of every unselected ISFET into the fluid, ultimately manifesting itself as noise in the fluid (i.e., an incorrect charge, one not due to the chemical reaction being monitored). That is, any change in the shared drain terminal voltage can be regarded as injecting noise into the fluid by each and every unselected ISFET in the column. Hence, if the shared drain terminal voltage of the unselected ISFETs can be kept constant when selecting a row in the array, this mechanism of coupling noise into the fluid can be reduced or even effectively eliminated.

(644) The ISFET Source Problem

(645) When a row is selected in the array, the source terminal voltage of all of the unselected ISFETs in the column also changes. In turn, that changes the gate-to-source capacitance of all of these ISFETs in the column. This change in capacitance couples from the gate of every unselected ISFET into the fluid, again ultimately manifesting itself as noise in the fluid. That is, any change in the source terminal voltage of an unselected ISFET in the column can be regarded as an injection of noise into the fluid. Hence, if the source terminal voltage of the unselected ISFETs can be kept when selecting a row in the array, this mechanism of coupling noise into the fluid via can be reduced or even effectively eliminated.

(646) A column buffer may be used with some passive pixel designs to alleviate the ISFET drain problem but not the ISFET source problem. Thus, a column buffer most likely is preferable to the above-illustrated source-and-drain follower. With the illustrated three-transistor passive pixels employing a source-and-drain follower arrangement, there are essentially two sense nodes, the ISFET source and drain terminals. By connecting the pixel to a column buffer and grounding the drain terminal of the ISFET, there will be only one sense node: the ISFET source terminal. So the drain problem is eliminated.

(647) Active Pixel Design

(648) All of the above-discussed passive pixels circuits present noise and scalability challenges. That is, increasing the size of the array typically leads to increased bus capacitance and a non-linear increase in power needs. Increasing readout speed comes at the expense of increased readout noise. Replacing passive ISFET pixels with active pixels, each having an active amplifier transistor as an integral element, can reduce noise coupled into the fluid, along with reducing readout noise, low frequency noise and fixed pattern noise. This approach, moreover, appears to provide a low-noise ISFET pixel that successfully eliminates both the ISFET drain problem and the ISFET source problem, the latter because the sense node (i.e., ISFET source terminal) is decoupled from the column bus.

(649) Note that, to make a measurement, the sense node has to be connected to a current source, with current flowing. However, switching the current source off and on introduces a disturbance at its own to the sense node, and thus couples noise into the fluid. To avoid this problem and further improve the signal-to-noise ratio, a single transistor current source can be introduced into each active ISFET pixel. Current then would be flowing through every pixel in every column of the array all of the time. Of course, there are obvious implications for power consumption and it would be advisable to operate this current source transistor in sub-threshold mode to minimize power consumption.

(650) Turning to FIG. 75F, there is shown a first example 75F1 of such an active pixel. The active pixel 75F1 has four transistors, 75F2-75F5, of which 75F2 is the ISFET, its floating gate being shown diagrammatically at 75F6. While the column bus 75F7 is decoupled from the sense node by source follower transistors 75F4 and 75F5 to reduce readout noise, switching the current source (not shown) on and off with transistor 75F3 introduces a disturbance at the sense node (the source of ISFET 75F2) which couples noise into the fluid.

(651) A second example of a four-transistor active pixel 75G1 is shown in FIG. 75G. This pixel uses a single-MOSFET current source 75G3 to avoid introducing a disturbance at the sense node. The current source transistor can be operated as a reverse-biased diode (cutoff) or in sub-threshold mode to minimize power consumption.

(652) By sharing some transistors between pixels, the average number of transistors per pixel, and hence pixel size, can be reduced. For example, see the arrangement of FIG. 75H, wherein transistors 75H1 and 75H2 are shared between four pixels 75H3-74H6, resulting in an average of 3.5 transistors per pixel.

(653) An example of a six-transistor active pixel 75I0 is shown in FIG. 75I. In operation, the reset input 75I1 is enabled, transistor 75I3 is turned on and the resultant voltage from ISFET 75I2 is measured by the source follower transistors 75I4-75I5. The difference between the reset level and the signal level from ISFET 75I2 is the output of the sensor.

(654) By taking two samples per pixel (i.e., using correlated double sampling (CDS), the six transistor pixel 75I0 can suppress 1/f noise, and fixed pattern noise due to threshold voltage variations.

(655) As shown in FIG. 75J, the concept of sharing transistors among a group of pixels also can be applied to the six-transistor pixel example of FIG. 75I. By sharing three transistors 75I1, 75I4 and 75I5, four pixels 75J1-75J4 can have an average of 3.75 transistors each. The two sharing examples use four pixels but there is no reason transistors cannot be shared among a different number of pixels.

(656) Moving from a passive pixel design to an active amplified pixel design thus improves the scalability of the design and reduces the readout noise. A single-MOSFET current source is required in each ISFET pixel to avoid coupling noise into the fluid. By increasing the number of transistors per pixel, correlated double sampling can be used at the pixel level to reduce flicker noise and fixed pattern noise. Further, the shared pixel concept can be used to reduce the effective number of transistors per pixel to achieve a smaller pixel size.

(657) To reduce power consumption, the FETs (or selected ones of them) can be operated in the so-called weak inversion or sub-threshold mode.

(658) Readout Circuit

(659) The above-described readout circuit, which comprises both sample-and-hold and multiplexer blocks, also has a gain that is less than the ideal value of unity. Furthermore, the sample-and-hold block contributes a significant percentage of the overall chip noise, perhaps more than 25%. From switched-capacitor theory, the sample-and-hold kT/C noise is inversely proportional to capacitance. Hence, by choosing a larger capacitor, the sample-and-hold noise can be reduced. Another approach to reducing noise is to employ Correlated Double Sampling (CDS), where a second sample-and-hold and difference circuit is used to cancel out correlated noise. This approach is discussed at greater length, below.

(660) Correlated Double Sampling

(661) Correlated Double Sampling (CDS) is a known technique for measuring electrical values such as voltages or currents that allows for removal of an undesired offset. The output of the sensor is measured twice: once in a known condition and once in an unknown condition. The value measured from the known condition is then subtracted from the unknown condition to generate a value with a known relation to the physical quantity being measured. The challenge here is how to be efficient in implementing CDS and how to address both correlated noise and the minimization of noise injection into the analyte fluid.

(662) A starting point is the sensor pixel and its readout configuration as expressed in earlier parts of this application. Referring to FIG. 77A, the basic passive sensor pixel 77A1 is a three-transistor arrangement of an ISFET 77A2 and a pair of row select transistors, 77A3 and 77A4 connected to the ISFET source. Transistor 77A3 is connected in turn to a current source or sink 77A5. A readout is obtained via transistor 77A4 which is connected to the input of sense amplifier 77A6. A diode-connected transistor 77A7 in series with another amplifier, 77A8, connects in a feedback loop from the output of the sense amplifier to the drain of the ISFET. The sense amplifier output is captured by a sample-and-hold circuit 77A9, which feeds an output amplifier 77A10.

(663) As discussed above, the voltage changes on the ISFET source and drain inject noise into the analyte, causing errors in the sensed values. Two constructive modifications can reduce the noise level appreciably, as shown in FIG. 77B.

(664) The first change is to alter the signals on the ISFET. The feedback loop to the drain of the ISFET is eliminated and the drain is connected to a stable voltage, such as ground. A column buffer 77B is connected to the emitter of transistor.

(665) The second change is to include a circuit to perform CDS on the output of the column buffer. As mentioned above, CDS requires a first, reference value. This is obtained by connecting the input of column buffer 77B1 to a reference voltage via switch 77B2, during a first, or reference phase of a clock, indicated as the SH phase. A combined CDS and sample-and-hold circuit then double samples the output of the column buffer, obtaining a reference sample and a sensed value, performs a subtraction, and supplies a resulting noise-reduced output value, since the same correlated noise appears in the reference sample and in the sensor output.

(666) The operation of the CDS and sample-and-hold circuit is straightforward. The circuit operates on a two-phase clock, the first phase being the SH phase and the second phase being the SHb phase. Typically, the phases will be symmetrical and thus inverted values of each other. The reference sample is obtained in the SH phase and places a charge (and thus a voltage) on capacitor Cin, which is subtracted from the output of the column buffer when the clock phase changes.

(667) An alternative embodiment, still with a passive sensor pixel, is shown in FIG. 77C. The sensor pixel in this embodiment is a two-transistor circuit comprising ISFET whose drain is connected to a fixed supply voltage, VSSA. There is no transistor comparable to 77A4, and the pixel output is taken from the emitter of transistor 77A3, instead. The CDS and sample-and-hold circuit has been simplified slightly, by the elimination of a feedback loop, but it serves the same function, in conjunction with the charge (voltage) stored on capacitor Cbt, of subtracting a reference value on capacitor Cin from the signal supplied by the sensor pixel.

(668) Digital Pixels and Readouts

(669) As signal-to-noise ratios often can be improved by moving from the analog domain into the digital domain, we have also begun to explore the possibilities for creating digital ISFRT pixels and digital pixel readouts.

(670) Consider first the architecture shown in FIG. 75K. There, a single analog-to-digital converter (ADC) 75K1 converts the analog output of a column addressing circuit 75K2, supplying output from pixel array 75K3, to digital form. Low fixed pattern noise is achievable but the operation of this architecture is low, the single ADC being a bottleneck. The frame rate is limited by the number of pixels and the time required for the ADC to complete one conversion. Thus, this architecture is not suitable for high resolutions.

(671) To achieve higher throughput (i.e., frame rate), one ADC 75L11-75L1n may be used for each column of the array 75K3, as illustrated in FIG. 75L. Indeed, the frame rate can be nearly n times faster. Instead of the ADC being a speed-limiting factor, frame rate can be limited by the output transfer capabilities of the array. The down-side, of course, is that power consumption is increased.

(672) In either of these two cases, parallelism and frame rate can be increased by dividing the array into two groups (75M1, 75M2 in FIGS. 75M and 75N1, 75N2 in FIG. 75N), and reading out each group separately. Again, however, there is a power consumption penalty to be paid. Not illustrated in FIGS. 75M and 75N is a multiplexer which may be used, if desired to provide a single output stream (e.g., interleaving outputs of the first, or top, group with outputs of the second, or bottom, group).

(673) To go more directly into the digital domain, one has to move from converting an analog array output into generating a digital output directly at each pixel. In general, this requires providing at each pixel some form of analog-to-digital conversion, and memory (at least 1-bit, for each). Converting the analog sensor signal to digital on an in-pixel basis creates an opportunity to achieve the largest possible signal-to-noise ratio (SNR). It also is inherently scalable, allowing high speed, massively parallel readout of digital sensor data, with the frame rate limitations being dominated by array input/output (I/O) transfer speed, owing to the fact that all pixels are converting sensed values to digital form in parallel.

(674) A basic digital pixel architecture 75O1 is as shown in FIG. 75O. It includes an ISFET 75O2, a current source 75O3, an ADC 75O4 and memory 75O5, whose operation is as discussed above. As with the above-discussed active ISFET pixels, the circuitry around the sense node (not shown in detail here, for clarity) preferably is chosen to avoid coupling noise into the fluid.

(675) The concept of sharing circuitry between multiple pixels, to reduce the average chip area per pixel and to reduce the average and total power consumption, can be extended to digital pixel architectures, as well. For example, FIG. 75P depicts an ADC 75P1 and memory 75P2 being shared by four ISFET cells 75P3-75P6 or pixels (here using that term even though the ADC and memory are shared and not part of the cells within the dotted lines).

(676) With such digital pixels formed into an array, from a readout perspective the array resembles a memory array. Thus, as shown in FIG. 75Q, when the individual pixels provide digital output values, row addressing circuitry 75Q1 and column sense amplifiers 75Q2 can provide the readout functionality from pixel array 75Q3, as they would in a memory array.

(677) The approaches of FIGS. 75M and 75Ni.e., subdividing or segmenting the array and processing separately the subdivisions/segmentsmay be implemented with any suitable pixel architecture, such as those of FIGS. 77B and 77C, with digital or analog pixel output. For example, the output of the column mux 77B4 or 77C4 of each segment can be an input to a further multiplexer, not shown for selecting between segments to supply a common output.

(678) Thus, a row and column addressing scheme allows selection of a variably sized sub-region within the array. This facilitates a trade-off of the size of the array being interrogated with the readout speed (i.e. frames per second). A faster sample rate can have a number of potential advantages:

(679) 1.) A faster sample rate when combined with a digital filter can produce better signal-to-noise measurements for the pixels within the sub-region. For example, selecting a sub-region of one-fourth the array size would allow sample rates approximately four times higher for the pixels within the sub-region. A simple filter that averages four consecutive samples together would reduce the final sample rate back down to the nominal whole-array frame rate, but each measurement would only have approximately half the noise content.

(680) 2.) The faster sample rate can be used to examine higher-frequency signals than would otherwise be possible at the nominal whole-array frame rate of the device. For example, selecting a sub-region of one-fourth the array size would allow sample rates approximately four times higher and the bandwidth limit for measured signals would be increased by a factor of four.

(681) 3.) Both cases can be combined to provide both high-frequency response and higher SNR. For example, selecting a sub-region one-sixteenth the whole-array size would allow for both a two-fold increase in SNR and a four-fold increase in bandwidth.

(682) In some applications, sensitivity and/or signal bandwidth may be more important than the number of active pixels. The availability of variable frame size (which might also be called flexible bandwidth allocation, or perhaps dynamic bandwidth allocation) is valuable in these situations.

(683) With an appropriately segmented array, it would also be possible to perform a rolling sequencing reaction across a large array. One would *slowly* flow dNTP across a large chip. As the wave of dNTP flows across the chip slowly, the sequencing reaction would only be occurring in a small region along the front of the dNTP flow. In theory, it would be possible to synchronize sub-region oversampling with the dNTP front to get very accurate measurements of the entire array.

(684) Protection Diodes

(685) To reduce possible gate oxide degradation during plasma processing (e.g., plasma etch, sputtering, PECVD, etc.), a well diode and/or a substrate diode may be employed, as illustrated in FIGS. 75R-75T.

(686) In FIG. 75R, diode 75R1 between the gate 75R2 of ISFET 75R3 and the well 75R4 limits the voltage that can build up on the gate relative to the well. The overhead added in the form of real estate occupied is quite small A typical ISFET, for example, might be 1.20.5 m, and the diode might have a perimeter of about 2.8 m and occupy only 0.49 m.sup.2.

(687) In FIG. 75S, diode 75S1 between the gate 75R1 of ISFET 75R3 and the substrate 75S2 limits the voltage that can build up on the gate relative to the substrate. The overhead added in the form of real estate occupied is quite small A typical ISFET, for example, might be 1.20.5 m, and the diode might have a perimeter of about 2.8 m and occupy only 0.49 m.sup.2.

(688) As shown in FIG. 75T, both diodes can be used together and their total area might typically be only about 0.98 m.sup.2.

(689) Reference Electrode Alternatives: The Fluid-Fluid Interface

(690) Performance of the instrument, over all, also can be enhanced with further attention to the reference electrode. With the above-described simple electrodes involving a metal tube, wire, etc. inserted into the flow cell, it has been observed that the reference potential introduced into the flow cell by such electrodes is not stable. It is sensitive to variations in fluid composition and pH. Accordingly, attention also has been given to devising an improved electrode arrangement, which can introduce a more stable reference potential.

(691) With the simple electrode designs discussed above, the fluid-electrode interface influences the way the reference potential is transmitted into the fluid. That is, the interface potential between the fluid and the electrode fluctuates with the composition of the fluid (which may be somewhat turbulent and inhomogeneous), introducing a voltage offset to the potential of the bulk fluid which varies with time and possibly location, as well.

(692) Considerably greater reference potential stability may be achieved by moving the location of the reference electrode so that it is substantially isolated from changes in fluid composition. This may be accomplished by introducing a conductive solution of a consistent composition over at least part of the surface of the electrode (hereafter the electrode solution), arranging the electrode to avoid it coming into direct contact with the fluid in the flow cell and, instead, arranging the electrode solution (not the electrode) to come into electrical contact with the fluid in the flow cell. The result is a transfer of the reference potential to the flow cell solution (be it a reagent or wash or other solution) that is considerably more stable than is obtained by direct insertion of an electrode into the flow cell solution. We refer to this arrangement as a liquid-liquid or fluid-fluid reference electrode interface.

(693) The fluid-fluid interface may be created downstream from the flow cell, upstream from the flow cell, or in the flow cell. Examples of such alternative embodiments are shown in FIGS. 76A-76D.

(694) Turning first to FIG. 76A, there is shown a diagrammatic illustration of an embodiment in which the fluid-fluid interface is created downstream from the flow cell. In this example, the flow cell apparatus 76A1 is, as above, mounted on a chip 76A2 which contains the sensor array (not shown). The flow cell apparatus includes an inlet port 76A3 and an outlet port 76A4. That is, the reagent fluids are introduced into port 76A3 via conduit 76A4 and they exit via port 76A4. A first port 76A6 of a fluid Tee connector 76A7 is coupled onto flow cell outlet port 76A4 via conventional couplings to receive the fluid exiting from the flow cell. A reference electrode such as a hollow electrically conductive tube 76A8 is fed into another port of the Tee connector via a fluid-tight coupling 79A9. The reference electrode is connected to a reference potential source 76A10 and a suitable electrode solution 76A11 is flowed into the center bore of the electrode tube.

(695) Two modes of operation are possible. According to a first mode, the electrode solution may be flowed at a rate that is high enough to avoid backflow or diffusion from the fluid flowing out of the flow cell. According to a second mode, once the electrode solution has filled the electrode and come into contact with the outlet flow from the flow cell, a valve (not shown) may be closed to block further flow of the electrode solution into the electrode and, as the electrode solution is an incompressible liquid, there will be substantially no flow into or out of the electrode, yet the fluid-fluid interface will remain intact. This presumes, of course an absence of bubbles and other compressible components. For a fluid-fluid interface to take the place of a metal-fluid interface, the tip 76A12 of the electrode 76A8 is positioned to stop within the Tee connector short of the fluid flow out of the flow cell, so that it is the electrode solution, not the electrode itself, that meets the outlet flow from the flow cell, indicated at 76A13, and carries the reference potential from the electrode to the reagent solution exiting the flow cell. The two fluid streams interact in the Tee connector at 76A13 and if the electrode solution is flowing, it flows out the third port 76A14 of the Tee connector with the reagent flow, as a waste fluid flow, for disposal.

(696) This approach eliminates interfacial potential changes at the electrode surface.

(697) Using a fluid-fluid interface to convey a stable reference potential from a reference electrode to a flow cell, various alternative embodiments are possible.

(698) In one alternative, illustrated in FIG. 76B, the referencing junction (i.e., the fluid-fluid interface) can be moved into the structure of the members forming the flow cell or even into the sensor chip itself, but with the electrode solution never entering the flow cell. For example, a manifold 76B1 may be formed in the flow cell assembly outside the flow chamber itself, having an inlet 76B2 for receiving electrode solution and an outlet 76B3 in fluid communication with the flow cell's outlet conduit 76A4. The electrode may be a separate element disposed in the manifold or it may be a metallization applied to an interior surface of the manifold.

(699) Alternatively, the manifold can be formed in the substrate of the chip itself by fabricating in the substrate a hollow region which can serve as a conduit allowing fluid passage from an inlet end to an outlet end. An electrode may be inserted therein via a separate inlet port 76B2 or part of the (interior or exterior, as appropriate) surface of the conduit may be metalized during fabrication, to serve as the electrode. The flow path for reagent fluid to exit the flow chamber may include a conduit portion and the electrode conduit/manifold may deliver electrode solution to the reagent fluid outlet conduit, wherein the two fluids come into contact to provide the fluid-fluid interface that applies the reference electrode voltage to the flow cell.

(700) In each instance, the electrode may be hollow and have the electrode solution delivered through its interior, or the electrode solution may be delivered over the exterior of the electrode. For example, as shown in FIG. 76B, the electrode may be hollow, such as being the interior surface of the manifold 76B1, and it may have an exterior that is insulated from the flow cell using any suitable structure and material (not shown, to avoid obfuscation of the basic idea).

(701) The electrode assembly thus may be built into the sensor chip itself or into the flow cell or its housing, coupled with a fluid inlet through which electrode solution may be introduced. The flow path for reagent fluid to exit the flow chamber may include a conduit portion 76A4 into which the electrode solution is presented, and wherein the two fluid flows come into contact to provide the fluid-fluid interface. The electrode solution may flow or be static.

(702) As a further alternative embodiment, depicted in FIG. 76C, the electrode structure may be integrated into or disposed within the flow cell itself. This may be done in two distinctly different ways. First, the electrode solution may be introduced into the flow chamber and flowed from an inlet 76B4 into the flow cell (provided for that purpose) to an outlet port 76A4 through which both the electrode solution and the reagent flow exit the flow chamber. If both fluids are arranged to move through the chamber in a laminar flow, they will not intermix (or there will be little mixing and interaction) until they reach the outlet. So there need not be a barrier between the two fluids. Their entire region of contact will be the locus of fluid-fluid interfacing, which may provide considerably more surface for that interface than the other illustrated alternatives. Second, a fluid conduit may be provided adjacent to the flow chamber or even fully or partly within the flow chamber, with a non-conductive exterior. The electrode may extend along the interior of the conduit, between an electrode fluid inlet and a fluid outlet that permits the electrode solution to interface with the reagent flow, such as in a common outlet conduit 76A4.

(703) In the foregoing examples, the reference potential is introduced either in or downstream of the flow cell. However, the same approach is possible with the electrode provided upstream of the flow cell, as shown diagrammatically in FIG. 76D. There, 76A3 is the inlet port to the flow cell and 76A4 is the outlet port, as in FIG. 76A. A cross-connector 76D1 having four ports has a first port 76D2 coupled onto the inlet port. A second port, 76D3, receives the solution to be reacted or measured (e.g., a reagent) via inlet conduit 76A5. A third port, 76D4, is used as a waste outlet port. The fourth port, 76D5, receives the electrode in the same manner as previously shown in FIG. 76A. Within the cross-connector, the electrode solution and the solution to be reacted/measured interact to transmit the reference potential into the flow cell. In contrast with some of the other alternative embodiments, however, at least some implementations of this embodiment may require that the solution to be measured/reacted must have a sufficiently high flow rate as to prevent flow of the electrode solution into the flow chamber. However, with judicious configuring of the cross-connector, it may still be possible to avoid the need to flow electrode solution continuously.

(704) Further Developments in Fluidics

(705) The delivery of multiple reagent solutions (and wash solutions) in sequence to a common volume (i.e., flow cell or flow chamber) requires selective switching (i.e., multiplexing) the fluid flows. The multiplexing of fluid flows typically introduces characteristics that are undesirable in that they produce less than ideal results, including potential contamination of reagents, for example, and intervals during which sensor response is unusable or unreliable, reducing potential throughput. The volume of interest, specifically where various reagents must commonly flow to reach the flow cell, is relatively large. This competes with the requirement of cleanliness, as a previously flowing reagent must be completely washed out of the common volume before the next reagent can flow through it to the flow cell. This takes time and consumes wash solution. The characteristic of high volume usually stems from the bulk of valve mechanics that is used to operate the multiplexing action. The presence of valve mechanisms in or near the common volume also competes with the requirement of cleanliness directly, as the valves often present high surface area and/or crevice-type volumes that can retain unwanted reagents. Hence, it would be desirable to provide an improved switching mechanism for reagent flow, to reduce the time required for switching fluids and to minimize cross-contamination.

(706) As exemplified in the embodiment illustrated in FIGS. 78A-78E, instead of multiplexing multiple reagents right at the location of valves used to control their flow, the reagents may be multiplexed downstream of the valving, within a passive micro-fluidic multiplexer circuit that acts as a kind of union. The challenge of presenting a union to multiple reagents is to deliver only a single selected reagent to the chip (i.e., flow cell) input, while having no diffusion-transported effluent from any other reagent input. A simple nodal junction would not satisfy this requirement, as all incoming reagent lines, not being shuttered by valves directly at the junction, could freely diffuse into one another. The disclosed fluidic circuits overcome this difficulty by employing laminar flow or fluid resistance networks to discard diffuse effluent to a waste location.

(707) The multiplexer circuit comprises a (optional) housing 778A1 supporting a fluid multiplexer member 78A2 and having reagent input ports 78A3-78A6, a wash input port 78A7, a waste output port 78A8, a chip (flow cell) output port 78A9, a wash solution inlet port 78A10, a multi-use central port 78A11 and a multi-purpose outlet supply port 778A12. (Each reagent is treated in like fashion and the structure of the multiplexer member is the same for each reagent and for the wash solution, so the pertinent structure will be discussed in detail only for one reagent, it being understood that such discussion applies as well to the structures for the other solutions.) Each reagent input feeds into the underside of a corresponding curved (e.g., semi-circular) laminar channel such as channel 78B3, in FIG. 78B. Channel 78B3 may, for example, be on the order of 0.5 mm on a cross-sectional side and a curvature 5 mm in diameter. The ends of the laminar channel feed into two restriction channels (e.g., 78B3-a and 78B3-b), with reduced cross sectional area and length of approximately 1 cm. A first one of the restriction channels, 78B3-a, connects to an outer, circular channel, 78B10, which feeds the fluid flow to the waste outlet 78A8. The second of the restriction channels, 78B3-b, leads to directly to a port 78A11 in the center of the structure, extending downwardly in the drawing. Referring to FIGS. 78C and 78D (which show the multiplexer in reflection relative to FIGS. 78A and 78B), port 78A11 connects to a first leg 78B14 of a T-shaped conduit structure 78B16, which has a second leg 78B18 that receives the wash solution input and a third leg 78B20 that supplies solutions to the flow cell fluid input.

(708) On each of the solution feeds, a two-way valve is employed (not shown), upstream of the multiplexer member.

(709) There are two modes of operation for the multiplexer circuit. In a first mode, a reagent is introduced via the multiplexer to the chip. In a second mode, a wash solution clears the multiplexer and the chip.

(710) In the first mode, the upstream valve on the wash solution input is turned off and no wash solution flows into conduit leg 78B18. Selection of a particular reagent is performed by opening its associated upstream valve. Downstream valves (also not shown, to avoid obfuscation) for both the chip and waste outlets are also opened. Two basic processes commence: a) referring to FIGS. 78C and 78E, the selected reagent entering via 78B3 is driven to the waste output in the multiplexer circuit, traveling in opposing directions from its point of entry and through both restriction channels 78B3-a and 78B3-b, and b) some typically smaller percentage of the reagent flows downward into port 78A11 into conduit 78B14 and thence upward into port 78A12 and through the chip output port 78A9 toward the chip. The restriction channels are intended to dominate the resistance of the system, albeit quite small, such that the reagent flow to waste is balanced between the two paths. While reagent traverses the laminar channel, it is possible for effluent from the other reagent inputs to diffuse into the reagent stream. However, as illustrated in FIG. 79, this diffuse effluent 79-2 remains in the lower lamina of the stream and continues on to the waste output along with the flow occurring via channel 78B3-b. That is, with no flows entering the other fluid inlet ports, the solution entering port 78A3, into channel 78B3, flows from channel 78B3-b to the waste port via the semicircular channels associated with each of the other inlet ports, sweeping out solutions that otherwise might diffuse into the incoming fluid. At the same time, a portion of the incoming reagent is directed toward the chip from the upper lamina, 79-4, where the concentration of effluent is close to zero, via aperture 78B25 into port 78A11 and thence as above described. A side view of this phenomenon is illustrated in FIG. 79.

(711) Between reagent flows, wash solution is fed into the circuit, in the second mode. FIG. 78D illustrates the wash flow. Wash solution flows both to the chip via ports 78A10 and 78A9, and through the laminar channel structure to waste via port 78A8. In this way, both the chip and laminar channel structure are cleaned of the previous reagent material before a subsequent reagent is introduced. There is also a short priming period prior to reagent flow to the chip, where the reagent flows to waste while the chip is again washed. This brings the multiplexer to a state of stable concentration of the new reagent, while preventing reagent from immediately entering the chip.

(712) The parameters indicated are merely suggested values, and may be adjusted through a large range.

(713) When the reference electrode is placed upstream of the flow cell, the port 78A9 provides a convenient location for its introduction.

(714) The need for only two-way valves is advantageous from a simplicity point of view. Also, the valves can be located very remotely upstream of the multiplexer, and therefore can be placed in almost any location within the supporting instrument. The small physical size of the multiplexer, having no integrated valves or other bulky structures, suggests that it can be located directly at the chip location, greatly reducing the total common volume and providing high spatial and temporal gradients between wash solution and reagent.

(715) Also feasible is a two-dimensional (i.e., thin, disc-like) version of this circuit that would allow tighter packing of reagent inputs, as indicated in FIGS. 80A and 80B at 80-1. This would be particularly useful if a very large number of reagents were required. Instead of flowing in only two opposite directions of a linear channel, such a device will permit radial flow across a circular channel. A shallow restrictive ring 80-2 replaces the restriction channels. A relatively deep and low resistance ring on the outermost section can serve as the waste output. Reagent inputs are supplied at 80-4 and the output is taken at 80-5.

(716) A variation of this two-dimensional structure can be made which does not rely on laminar flow to separate out the diffuse effluent. The reagent inputs are essentially packed in a single circle centered on the chip output. Instead of a free and open two-dimensional channel throughout the circuit, narrow channels connect the reagent inputs to both the chip output and waste ring. When a particular reagent input flows, it enters the central node and both exits to the chip and sweeps past the other reagent inputs on its way to the waste ring. Diffuse effluent from those ports enters the stream to waste, but cannot diffuse upstream toward the chip output. The relative fluidic resistances of the various channels can be adjusted for various performances characteristics (effluent isolation, waste rate minimization, etc.).

EQUIVALENTS

(717) While several inventive embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the inventive embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the inventive teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific inventive embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure.

(718) All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.

(719) All references, patents and patent applications disclosed herein are incorporated by reference with respect to the subject matter for which each is cited, which in some cases may encompass the entirety of the document.

(720) The indefinite articles a and an, as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean at least one.

(721) The phrase and/or, as used herein in the specification and in the claims, should be understood to mean either or both of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with and/or should be construed in the same fashion, i.e., one or more of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the and/or clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to A and/or B, when used in conjunction with open-ended language such as comprising can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

(722) As used herein in the specification and in the claims, or should be understood to have the same meaning as and/or as defined above. For example, when separating items in a list, or or and/or shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as only one of or exactly one of, or, when used in the claims, consisting of, will refer to the inclusion of exactly one element of a number or list of elements. In general, the term or as used herein shall only be interpreted as indicating exclusive alternatives (i.e. one or the other but not both) when preceded by terms of exclusivity, such as either, one of, only one of, or exactly one of. Consisting essentially of, when used in the claims, shall have its ordinary meaning as used in the field of patent law.

(723) As used herein in the specification and in the claims, the phrase at least one, in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase at least one refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, at least one of A and B (or, equivalently, at least one of A or B, or, equivalently at least one of A and/or B) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

(724) It should also be understood that, unless clearly indicated to the contrary, in any methods claimed herein that include more than one step or act, the order of the steps or acts of the method is not necessarily limited to the order in which the steps or acts of the method are recited.

(725) In the claims, as well as in the specification above, all transitional phrases such as comprising, including, carrying, having, containing, involving, holding, composed of, and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases consisting of and consisting essentially of shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

(726) Frame Averaging and Compression

(727) In regard to FIG. 17, and as discussed above, the array controller 250 reads one or more analog output signals (e.g., Vout1 and Vout2) including multiplexed respective pixel voltage signals from the array 100 and then digitizes these respective pixel signals to provide measurement data to the computer 260. In turn, the computer 260 can store and/or process the measurement data.

(728) In an embodiment, the ADC(s) 254 may be controlled by the timing generator 256 via the sampling clock signal CS to sample the output signals Vout1 and Vout2 at a high data rate to provide two or more digitized samples for each pixel measurement, which may then be averaged. In an embodiment, two or more pixel measurements in successive frames can be averaged for each pixel of every frame considered. Here, the output is the average measurement for each pixel of all frames considered. As a result of this frame averaging technique, reduction in noise for each pixel can be achieved.

(729) In regard to FIG. 17, the above-described frame averaging technique can occur in the array controller 250, the computer 260, or both the array controller 250 and the computer 260, according to an embodiment of the present invention. The computer 260 can store the pixel measurement data for further processing, according to an embodiment of the present invention. In another embodiment, the pixel measurement data can be stored in a memory storage device (not shown in FIG. 17) that is external to the array controller 250 and the computer 260.

(730) Variable frame rate averaging can also be performed on the data sampled from the sensor array (e.g., array 100 of FIG. 17). Variable frame rate averaging is similar to the frame averaging technique discussed above with the addition of allowing a variable number of frames to be averaged together. A benefit, among others, of variable frame rate averaging is that the number of frames averaged and outputted as a single frame can be done at any point during the data acquisition process. Once the variable frame rate averaging is performed on the data sampled from the sensor array, a keyframe delta compression can be performed on the resulting data to further compress the data to be stored.

(731) With faster sampling data rates and higher densities of sensor arrays, the pixel measurement data can consume a large amount of memory on the computer 260 and/or an external memory storage device. It is thus desirable to reduce memory consumption while maintaining the quality of the pixel measurement data A goal of method 8100 (discussed in detail below), among others, is to accurately capture data associated with a biological/chemical event, while reducing noise associated with the data. This goal can be achieved by implementing the frame averaging, variable frame rate averaging, and keyframe delta compression techniques described above. As a result, the amount of data stored (e.g., in the computer 260 of FIG. 17 or an external memory storage device) can be reduced.

(732) FIG. 81 is an illustration of an embodiment of a method 8100 for sampling a sensor array. Method 8100 can be applied to a system that includes a sensor array and an array controller such as, for example and without limitation, the system depicted in FIG. 17.

(733) In step 8110, a waveform associated with a chemical event occurring on a sensor array is measured. The chemical event that can occur on the sensor array can be, for example and without limitation, one or more stepwise changes in the concentration of one or more ionic species in an analyte solution in fluid contact with an ISFET array (e.g., array 100 of FIG. 17).

(734) FIG. 82 is an illustration of an example waveform 8200 of a stepwise change in the concentration of one or more ionic species in an analyte solution in fluid contact with an ISFET array (e.g., array 100 of FIG. 17). That is, the waveform 8200 represents a dynamic response of an ISFET array to a change in ionic strength of the analyte solution in fluid contact with the ISFET array. The x-axis of the waveform 8200 represents a frame number, which is a function of time. That is, depending on a clock signal provided by a timing generator (e.g., timing generator 256 of FIG. 17), the data rate at which frames are sampled from the ISFET array can vary, as would be understood by a person of ordinary skill in the art. Further, the y-axis of the waveform 8200 represents a number of counts, which is representative of voltage measured by the ISFET array.

(735) In regard to the waveform 8200 of FIG. 82, after a certain period of time and as passivation layer surface groups (from the ISFET array) react to the stimulus (e.g., as the surface charge density adjusts), the ISFET array returns to an equilibrium point. The return to the equilibrium point is indicated by a decay of the ISFET array response pulse 8230 illustrated in FIG. 82. The foregoing ISFET array characteristic is referred to herein as an ion-step or stepwise response.

(736) For ease of reference, the ion-step response depicted in the waveform 8200 of FIG. 82 will be used to facilitate in the explanation of method 8100. However, based on the description herein, a person of ordinary skill in the art will recognize that method 8100 of FIG. 81 is not limited to the waveform 8200 and the chemical reaction associated with the waveform 8200. Method 8100 can be applied to other waveforms associated with other types of chemical reactions.

(737) In regard to step 8110 of FIG. 81, the waveform 8200 of FIG. 82 can be determined by prior measurements of one or more analyte solutions flowing over the sensor array, according to an embodiment of the present invention. That is, in an embodiment, an array controller (e.g., array controller 250 of FIG. 17) can be used to sample the ISFET array to produce the waveform 8200. The sampling technique applied by the array controller can be frame averaging (e.g., averaging of 2, 4, 6, 8, or 10 frames), as described above, over the entire waveform 8200, according to an embodiment of the present invention. In another embodiment, the array controller can sample the ISFET array to collect frames of data without frame averaging.

(738) In regard to FIG. 82, a portion 8210 of the waveform 8200 can be considered a region of the waveform that has expected measured values because this region is prior to an ion-step response portion 8220 of the waveform. In an embodiment, the portion 8210 can be a time period between when an analyte enters the sensor array system and the analyte contacts an area proximate to an ISFET in the sensor array. As discussed above, the analyte can enter the sensor array system via a microfluidics system. In an embodiment, the expected measured values can indicate a time period that, for all ISFETs in the sensor array, is prior to an ion-step response.

(739) Also, based on the sampled data associated with the one or more analytes flowing over the sensor array, the time period of the ion-step response portion 8220 of the waveform can be determined, according to an embodiment of the present invention. In an embodiment, the sampled data can indicate a time period in which the ion-step response occurs for all ISFETs in the sensor array. The ion-step response can be the portion 8220 of the waveform that provides the most important information associated with the chemical reaction. The ion-step response portion 8220 of the waveform oftentimes has unpredictable measured values due to the nature of the biological/chemical experiment conducted on the sensor array such as, for example and without limitation, DNA sequencing. With DNA sequencing, the ion-step response 8220 also has unpredictable measured values due to the nature of the DNA itself and the polymerase interactions occurring on the sensor array.

(740) Further, based on the sampled data associated with the of one or more analytes flowing over the sensor array, the time period of the decay of the ISFET array response pulse 8230 of the waveform can be determined, according to an embodiment of the present invention. In an embodiment, the sampled data can indicate a time period in which the decay occurs for all ISFETs in the sensor array. The decay 8230 can be considered another region of the waveform 8200 that has expected measured values because this region is after the ion-step response portion 8220 of the waveform.

(741) In steps 8120-8140 of FIG. 81 (described in detail below), the first averaging, second averaging, and third averaging are applied to the sampled data collected in step 8110, where the sampled data represents the waveform 8200 of FIG. 82. As would be understood by a person of ordinary skill in the art based on the description below, steps 8120-8140 perform a variable frame rate averaging on the waveform 8200 of FIG. 82. Step 8150 of FIG. 81 applies a keyframe delta compression to the results from steps 8120-8140. A computer such as, for example and without limitation, the computer 260 of FIG. 17 can be used to receive the sampled data collected in step 8110 from the array controller (e.g., array controller 250 of FIG. 17) and perform steps 8120-8150 on the sampled data.

(742) In step 8120 of FIG. 81, a first frame averaging is applied to at least one region of the waveform 8200 associated with expected measured values. In an embodiment, the first frame averaging can include a first number of frames that are averaged during the at least one region associated with the expected measured values. Here, the first frame averaging is a frame averaging technique, as described above, where the first number of frames can be, for example and without limitation, 4, 6, 8, or 10 frames. Also, in an embodiment, the at least one region associated with the expected measured values can be the portion 8210 of the waveform 8200 (e.g., region prior to the ion-step response portion 8220 of the waveform 8200). As discussed above, a benefit of the frame averaging technique is not only a reduction in noise for each pixel of all frames considered (e.g., 4, 6, 8, or 10 frames) in the portion 8210 of the waveform 8200, but also a reduction in the amount of data stored over all of the frames considered. Based on the description herein, a person of ordinary skill in the art will recognize that the first number of frames (of step 8120) can be more or less than 4, 6, 8, or 10 frames.

(743) In step 8130, a second frame averaging is applied to the at least one region of the waveform 8200 associated with unpredictable measured values. In an embodiment, the second frame averaging can include a second number of frames that are averaged during the at least one region associated with unpredictable measured values. Here, the second frame averaging is a frame averaging technique, as described above, where the second number of frames is less than the first number of frames of step 8120. Also, in an embodiment, the at least one region associated with the unpredictable measured values can be the portion 8220 of the waveform 8200 (e.g., the ion-step response of the waveform 8200). A benefit, among others, of having the second number of frames less than the first number of frames is that accurate data on the ion-step curve 8220 can be stored. As discussed above, the ion-step curve 8220 can be the portion of the waveform 8200 that provides the most important information associated with the chemical event, according to an embodiment of the present invention.

(744) In another embodiment, the second number of frames in step 8130 can be zero, where no frames are averaged. As would be understood by a person of ordinary skill in the art based on the description herein, a tradeoff exists between the number of frames averaged and the accuracy of the data to be stored. Therefore, based on a particular chemical event and/or the specifications of the sensor system (e.g., sampling clock frequency), the number of frames to be averaged can vary.

(745) In step 8140, a third frame averaging is applied to a second region of the waveform 8200 associated with expected measured values. In an embodiment, the third frame averaging can include a third number of frames that are averaged during the second region associated with the expected measured values. Here, the third frame averaging is a frame averaging technique, as described above, where the third number of frames is higher than the second number of frames. Similar to the first number of frames, the third number of frames can be, for example and without limitation, 4, 6, 8, or 10 frames. Also, in an embodiment, the second region associated with the expected measured values can be the portion 8230 of the waveform 8200. A benefit of having a higher number of frames for step 8140 than the number of frames for step 8130, among others, is a reduction in the amount of data stored over all of the frames considered. This can be advantageous because the decay 8230 can be considered another portion of waveform 8200 with expected measured values. Based on the description herein, a person of ordinary skill in the art will recognize that the third number of frames (of step 8140) can be more or less than 4, 6, 8, or 10 frames.

(746) In step 8150, a keyframe delta compression is applied to results from the first, second, and third frame averaging from steps 8120, 8130, and 8140, respectively. In an embodiment, the keyframe delta compression compares a current frame of frame-averaged data associated with the waveform 8200 to a previous frame of frame-averaged data associated with the waveform 8200.

(747) In particular, the keyframe delta compression refers to a lossless compression algorithm where an initial measurement per pixel is stored in a keyframe using a first predetermined number of bits (e.g., 16 bits). For each subsequent frame measured during the at least one region associated with the chemical reaction, each pixel of the frame is compared to its corresponding keyframe value. The difference or delta between the pixel and its corresponding keyframe value is stored using a second predetermined number of bits (e.g., 8 bits). In an embodiment, the process of storing the delta between a pixel and its corresponding keyframe value continues until the delta cannot be stored using the second predetermined number of bits (e.g., 8 bits). At this point, a new keyframe value using the first predetermined number of bits (e.g., 16 bits) is stored, according to an embodiment of the present invention.

(748) Based on the description herein, a person of ordinary skill in the art will recognize that other types of data compression algorithms can be applied to the embodiments described herein. For instance, data compression algorithms such as, for example and without limitations, lossy compression algorithms (e.g., MP2 and MP4) and lossless compression algorithms can be used in step 8150 of FIG. 81.

(749) In summary, method 8100 reduces the amount of data associated with the waveform 8200 by increasing the number of frames that are averaged during portions of the waveform with expected measured values (e.g., portions 8210 and 8230 of FIG. 82), while reducing the number of frames that are averaged during portions of the waveform with unpredictable measured values (e.g., portion 8220 of FIG. 82). As a result, the amount of data associated with the waveform 8200 is not only reduced, but also the most important information associated with the chemical reaction (e.g., portion 8220) is accurately measured using a lower number of frames for the frame averaging technique. Further, to reduce the amount of data stored, a keyframe delta compression is applied to the results from the frame averaging of portions of the waveform with expected and unpredictable measured values.

(750) FIG. 84 illustrates a compression method according to an exemplary embodiment. In step 8401, an analog output or waveform associated with a chemical event occurring in a well or other reaction area on a sensor array is obtained. The analog output or waveform, chemical event, and sensor array may be as described elsewhere in the present specification, for example. In step 8402, the analog output or waveform is converted into a digitized output or waveform comprising a plurality of frames using a digitizer. The digitizer may be of any suitable digitizer type, and may convert the analog output or waveform to 14 bit data, for example. Various conversion frame rates may be used. For example, the rate may be 0.008478 second/frame (e.g., Ion 314 Chip by Ion Torrent), 0.034402 second/frame (e.g., Ion 316 Chip by Ion Torrent), 0.061075 second/frame (e.g., Ion 318 Chip by Ion Torrent), and 0.033 second/frame (e.g., Ion Proton chip I or Ion P1 Chip by Ion Torrent). More generally, the rate may be selected between about 0.004 second/frame and about 0.333 second/frame. In step 8403, an average of frames of the digitized output or waveform for each of a plurality of regions comprising a variable number of frames is determined. In an example, this may be performed by a field-programmable gate array (FPGA). In step 8404, the determined averages for a subset of the plurality of regions occurring within an acquisition time period are delta compressed, which may be performed as described elsewhere in the present specification, for example. In step 8405, the delta compressed averages are stored on any suitable storage medium (e.g., a hard drive or any other type of storage device) or transferred to downstream processing or analysis.

(751) FIGS. 85(a)-85(c) illustrate a variable frame averaging compression process according to various exemplary embodiments. FIG. 85(a) shows an exemplary waveform showing a hypothetical response to a flow of nucleotide species as a function of time. The double arrow underneath the waveform indicates an exemplary acquisition time period, which begins before the flow and ends after the flow has reached completion. One or more data frames may be sampled or acquired from the waveform, and this may be done at various sampling rates. In some examples, a raw frame time may be 0.008478 second, or 118.0 frames per second (e.g., Ion 314 Chip by Ion Torrent); 0.034402 second, or 29.1 frames per second (e.g., Ion 316 Chip by Ion Torrent); 0.061075 second, or 16.4 frames per second (e.g., Ion 318 Chip by Ion Torrent), and 0.033 second, or 30 frames per second (e.g., Ion Proton chip I or Ion P1 Chip by Ion Torrent). More generally, the raw frame time may be selected between about 0.004 second and about 0.333 second, or between about 3 frames per second and about 250 frames per second. In some cases, the raw frame time may be selected between about 0.0333 second and about 0.0667 second, or between about 15 frames per second and about 30 frames per second. In an example, the number of raw frames acquired may be 1000 times a ratio between a duration of an acquisition time period and a frame time. More generally, the number of raw frames acquired may be selected between about 10 and about 200. FIG. 85(b) shows exemplary acquisition times as a function of frame averaging rate changes (Ion 316 Chip). The three series of numbers above the curly brackets indicate the number of frames within each curly brackets range, with the top series representing numbers for an Ion 314 Chip, the middle series representing numbers for an Ion 316 Chip, and the bottom series representing numbers for an Ion 318 Chip. The three series of numbers under the curly brackets indicate the acquisition time for the various curly brackets, with the top series representing an Ion 314 Chip, the middle series representing an Ion 316 Chip, and the bottom series representing an Ion 318 Chip. Various levels of oversampling may be used. For example, 1, 2, 4, 8, 16, or other levels may be used. FIG. 85(c) shows in the top panel the number of oversampled frames that may be averaged (e.g., using an FPGA) to generate an output frame. In an embodiment, that number may be relatively larger (e.g., 8) in portions of the waveform that are less informative, pertinent, or useful so that retaining an average of data points rather than all data points can be done without significant loss or detriment. Conversely, that number may be relatively smaller (e.g., 1) in portions of the waveform that are more informative, pertinent, or useful so that in such portion more or every data point can be retained without averaging, for example. FIG. 85(c) also shows in the bottom panel the number of averaged frames FPGA output that can subsequently be used for downstream data analysis. Here, for example, there are only three averaged frames before the rise of the waveform, then 52 during the most informative portion of the waveform, then 12 during the early portion of the waveform tail, and then 8 during the rest of the waveform tail. Of course, this particular oversampling scheme is only an example, and different oversampling schemes may be used, including for different portions or regions of a sensor array, which may differ due to differences in the flow of reagents onto one area versus another area, for example.

(752) FIGS. 86(a)-86(d) illustrate a keyframe delta compression process according to various exemplary embodiments. FIG. 86(a) shows an exemplary waveform, including exemplary frames f.sub.0, . . . , f.sub.n1, f.sub.n, f.sub.n+1, . . . , f.sub.N. In an embodiment, the first frame may be uncompressed, and that frame may be used to uncompress the delta compressed frames to follow. The keyframe delta compression may be as further described in the present specification. In various embodiments, other compression approaches capable of transforming data in a way that makes the data more compact while allowing subsequent reconstruction without loss could also be used. FIG. 86(b) shows frames of variable frame averaging data read from an FPGA. There, eight consecutive 16-bit segments are compressed as a block. The blocks are .sub.0, . . . , .sub.i=ADC.sub.nADC.sub.n1, . . . , .sub.7. FIG. 86(c) shows an exemplary frame f.sub.n after compression. In an embodiment, the blocks .sub.0 through .sub.7 may be stored in 4, 5, 6, 7, 8, or 16 bytes. The first two bytes 8601 of compressed data may be a compression transition marker that provides compression-related information. For example, the first byte of the compression transition marker may indicate with a code (e.g., 0x7F), that the compression structure of the next group of markers, 8602 and 8603, is changing, and the second byte of the compression transition marker may indicate a number of bytes necessary to store .sub.0 through .sub.7 (for example, here NN=0x44 indicates that .sub.0 through .sub.7 fit into 4 bytes, NN=0x55 that .sub.0 through .sub.7 fit into 5 bytes, . . . , NN=0x88 that .sub.0 through .sub.7 fit into 8 bytes, and NN=0xBB that .sub.0 through .sub.7 require 16 bytes). In an example, the compression transition marker may be inserted only when the number of bytes .sub.0 through .sub.7 are stored into changes (e.g., 5 bytes (NN=0x55) to 8 bytes (NN=0x88)). FIG. 86(d) shows exemplary compressed data, including initial blocks 8604, 8605, and 8606 followed by different blocks 8607 and 8608 that may have different repeat patterns and/or storage lengths for .sub.0 through .sub.7.

(753) FIGS. 87(a)-87(b) illustrate a t.sub.0 compression process according to an exemplary embodiment. FIG. 87(a) shows an exemplary waveform and three time periods. The flowTime period represents a time during which nucleotide species may be flowed. The acqTime period represents a time during which one or more sensors collect data. The acqWindow period represents the portion of the waveform to be stored or used for downstream analysis. These three periods typically overlap such that the acqWindow period is a subinterval of the other two. In an embodiment, the t.sub.0 compression process includes not keyframe delta compressing the first frame of acquisition f.sub.0. Then, in an embodiment, the first frame f.sub.n in the acqWindow period is the average of all preceding frames outside the acqWindow window and subtracted from the first frame of acquisition f.sub.0. Finally, only the frames in acqWindow are keyframe delta compressed and stored to the disk or other storage media. FIG. 87(b) shows an exemplary compressed frame data block for storage in memory. In an embodiment, there is one such data block for each frame in the acqTime period. In the figure, the data block corresponds to the structure of an individual frame as serialized onto disk. There, the transitions and sum of pixel values are related to checking the integrity of the data, and the remaining portions represent the structure of the data per region. Of course, such a data structure is only an example, and other data structures could also be used.

(754) FIG. 88 illustrates exemplary waveform and data acquisition windows defining a data flow according to an exemplary embodiment. The data acquisition windows include four time periods: acqTime, writeTime, flowTime, and ftpTime. In various embodiments, during acqTime, an FPGA acquires and digitizes raw voltages or other sensor data from a flow chip or other sensor array, which may be written to shared memory, and the FPGA also does variable frame rate compression (VFC) compression. In various embodiments, during writeTime, and in parallel to acqTime, the VFC compressed data is read from memory shared with the FPGA, and is delta compressed and stored to a disk or other storage media. In an embodiment, at this point all other processes are locked out of using the CPU. The flowTime period may be controlled by scripts so as to be open loop and empirically set so that there is enough time to acquire the data and write it out to disk and possibly transfer it out via ftp. Finally, during ftpTime, data files that were previously written may be sent by ftp to a server or other resource for downstream processing and/or analysis. In various embodiments, acqTime may be from about 1 second to about 16 seconds, or from about 2 seconds to about 8 seconds, for example. In various embodiments, writeTime may be from about 0.5 second to about 40 seconds, or from about 1 second to about 30 seconds, for example. In various embodiments, flowTime may be from about 1 second to about 5 minutes, or from about 5 seconds to about 40 seconds, for example. In various embodiments, ftpTime may be from about 0 second to about 40 seconds, for example.

(755) FIG. 89 illustrates signal curves from a period prior to a nucleotide flow to a period after a subsequent wash flow for four exemplary regions in an exemplary ion detection chip (Ion 314 Chip). The vertical axis represents DC offset subtracted counts, and the horizontal axis represents frames of data acquired on the chip (or time, at 15 frames per second). The exemplary regions are the inlet, lower right, middle, and outlet regions. In the upper panel, arrow 8901 indicates a start of a nucleotide flow, and arrow 8902 indicates a start of a wash flow following the nucleotide flow. In the lower panel, arrow 8903 indicates a bump due to a nucleotide incorporation signal, and, at arrow 8904, a dotted line shows the median and the grey areas show the 25%-75% quantiles. As illustrated, the washes before the nucleotide flow over different regions occur at different times depending on their position in the flow cell.

(756) FIG. 90 illustrates signal curves from a period prior to a nucleotide flow to a period after a subsequent wash flow for four exemplary regions in an exemplary substantially larger ion detection chip (Ion Proton chip). Because the chip is larger, it takes longer for both the nucleotide and the wash to travel across the chip so that at any given time of the chip may be measuring non-useful data that can be discarded. Of course, that is only an example, and different behavior may occur with different chip geometries. In addition, different characteristics of the flow cells and flow rates will also impact exactly when fluid will reach different regions on the chip. As illustrated, the washes before the nucleotide flow over different regions occur at different times depending on their position in the flow cell, and the amount of frames that can be discarded is even larger than for a smaller chip as up to about 60% of the total data from the chip may not be measuring the nucleotide flow.

(757) FIG. 91 illustrates an exemplary compression method according to an embodiment. In step 9101, a waveform associated with a chemical event occurring on a sensor array, the waveform comprising at least one portion associated with expected measured values and at least one portion associated with unpredictable measured values, is measured. In step 9102, a first compression process is applied to the waveform, the first compression process including an averaging of one or more frames in one or more portions of the waveform. In step 9103, a second compression process is applied to the waveform, the second compression process including a truncating of data corresponding to a portion of the waveform that is not related to a nucleotide incorporation component of the waveform.

(758) According to an exemplary embodiment, there is provided a method for compressing nucleic acid sequencing data comprising: (1) obtaining raw data from a semiconductor-based sequencing sensor array comprising a plurality of sensors during a data acquisition time period, the raw data comprising at least a non-informative portion corresponding to a subinterval of the data acquisition time period having a location within the data acquisition time period that varies for different sensors according to a position of the sensor in the sensor array; and (2) transforming the raw data into compressed data using both a lossless compression process including a keyframe delta compression process and lossy compression processes including a variable frame averaging process and a data truncation process, the data truncation process being related for each sensor to the position of the sensor in the sensor array and configured to discard the non-informative portion of the raw data There is also provided a non-transitory machine-readable storage medium comprising instructions which, when executed by a processor, cause the processor to perform such a method and variants thereof. There is also provided a system, including: a machine-readable memory; and a processor configured to execute machine-readable instructions, which, when executed by the processor, cause the system to perform such a method and variants thereof.

(759) A lossless compression process generally refers to a compression process allowing reconstruction of the compressed the data in a way that is essentially identical to the data pre-compression. A lossy compression process generally refers to a compression process allowing reconstruction of the compressed the data in a way that is not identical to the data pre-compression but close enough (under some suitable measure that may be application/objective specific) to achieve a desired purpose. In various embodiments, in addition with other compression approaches discussed herein, compression may generally be based on taking advantage of (1) situations where data points of interest are different at different locations on a sensor array; (2) situations where measurements may be similar within a region; and (3) situations where an enzyme operates at a particular speed so the data points are within a particular time period. In various embodiments, more important portions of the data may be compressed using lossless processes and other less important portions of the data may be compressed using lossy processes.

(760) According to an exemplary embodiment, there is provided a compression method comprising: (1) measuring a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises at least one portion associated with expected measured values and at least one portion associated with unpredictable measured values; (2) applying a first compression process to the waveform, the first compression process including an averaging of one or more frames in one or more portions of the waveform; and (3) applying a second compression process to the waveform, the second compression process including a truncating of data corresponding to a portion of the waveform that is not related to a nucleotide incorporation component of the waveform. There is also provided a non-transitory machine-readable storage medium comprising instructions which, when executed by a processor, cause the processor to perform such a method and variants thereof. There is also provided a system, including: a machine-readable memory; and a processor configured to execute machine-readable instructions, which, when executed by the processor, cause the system to perform such a method and variants thereof.

(761) In the foregoing exemplary embodiments, the truncating of data may comprise determining, for each of a plurality of sensors in the sensor array, a cut-off time point for the waveform for that sensor defining a data range to be truncated. Any suitable waveform analysis or approach at identifying cut-off or transition points in a waveform may be used to identify cut-off points. Each cut-off time point may be determined by mining a plurality of past analysis runs for a given sensor array geometry. In an embodiment, mining may include determining when a nucleotide flow reaches a well as determined by a change in waveform. Other algorithms may include measuring a rate of enzyme incorporation and determining a portion of frames where nucleotides are still incorporating. Each cut-off time point may be determined prior to every run or during a calibration procedure. Each cut-off time point may be factory pre-determined for a given sensor array geometry. The sensors may be arranged in a plurality of regions in the sensor array, and each cut-off time point for sensors in a given region may be determined to have a common cut-off time point determined for sensors for that region. Each common cut-off time point may be determined by finding a best fit to a linear hinge model on a median trace for a region. In an embodiment, a linear hinge model may look for the point where two separate lines best explain a region of a trace, which may include looking for a change point in the data where the nucleotide flow is causing a change in readings of the sensor array compared to a flowed solution. Each common cut-off time point may be determined empirically and may depend on a position of that region relative to other regions along a fluidic flow of nucleotides onto the sensor array. More specifically, fluid may hit different parts of the sensor array at different time points. For example an area near an inlet would experience a new solution being flowed first, as it initially enters or displaces a wash inside the flow cell, and an area near an outlet would experience that new solution later (as seen in FIG. 90) as the fluid has to physically move across the sensor array. The cut-off time point of sensors in a region substantially near a fluidic inlet may be different from the cut-off time point of sensors in a region substantially near a fluidic outlet.

(762) In the foregoing exemplary embodiments, the averaging may comprise applying a first frame averaging to the at least one portion associated with the expected measured values, wherein the first frame averaging may comprise averaging a first number of frames during the at least one portion associated with the expected measured values; and applying a second frame averaging to the at least one portion associated with the unpredictable measured values, wherein the second frame averaging may comprise averaging a second number of frames during the at least one portion associated with the unpredictable measured values, the second number of frames being lower than the first number of frames. The method may further comprise: applying a third frame averaging to another portion associated with expected measured values, and wherein the third frame averaging may comprise averaging a third number of frames that is higher than the second number of frames; and applying a keyframe delta compression to results from the first, second, and third frame averaging, wherein the keyframe delta compression may comprise comparing a current frame of data from frame-averaged data to a previous frame of frame-averaged data associated with the waveform. Measuring the waveform may comprise measuring the waveform of a dynamic response of an ion-sensitive field effect transistor (ISFET) array to a change in ionic strength of an analyte solution in fluid contact with the ISFET array. Measuring the waveform of the dynamic response of the ISFET array may comprise associating the at least one portion with the unpredictable measured values to a stepwise increase in ion concentration in the analyte solution and associating the at least one portion with the expected measured values to at least one portion of the dynamic response outside of the stepwise increase in ion concentration. Applying the first frame averaging may comprise averaging the first number of frames during the at least one portion of the dynamic response outside of the stepwise increase in ion concentration. Applying the second frame averaging may comprise averaging the second number of frames during the stepwise increase in ion concentration in the analyte solution.

(763) According to an exemplary embodiment, there is provided a computer program product comprising a computer-usable medium having computer program logic recorded thereon that, when executed by one or more processors, samples and compresses data from a sensor array, the computer program logic comprising: (1) first computer readable program code that enables a processor to measure a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises at least one portion associated with expected measured values and at least one portion associated with unpredictable measured values; (2) second computer readable program code that enables a processor to apply a first compression process to the waveform, the first compression process including an averaging of one or more frames in one or more portions of the waveform; and (3) third computer readable program code that enables a processor to apply a second compression process to the waveform, the second compression process including a truncating of data corresponding to a portion of the waveform that is not related to a nucleotide incorporation component of the waveform.

(764) According to an exemplary embodiment, there is provided a system, comprising: (1) a sensor array; (2) an array controller coupled to the sensor array, wherein the array controller is configured to measure a waveform associated with a chemical event occurring on the sensor array, wherein the waveform comprises at least one portion associated with expected measured values and at least one portion associated with unpredictable measured values; and (3) a computer coupled to the array controller, wherein the computer is configured to: (i) apply a first compression process to the waveform, the first compression process including an averaging of one or more frames in one or more portions of the waveform; and (ii) apply a second compression process to the waveform, the second compression process including a truncating of data corresponding to a portion of the waveform that is not related to a nucleotide incorporation component of the waveform.

(765) In various exemplary embodiments, in addition or as an alternative to one or more of other compression approaches described in this application, only data corresponding to the time just around when the nucleotide washes over a well (see, e.g., FIG. 89, between the arrows 8901 and 8902 showing the start of the nucleotide and wash flows, respectively) may be deemed important for measuring the incorporation signal and retained for downstream processing and analysis (such as, e.g., base calling). Thus, in an embodiment the measurements of the wash solution before and after the nucleotide flow may be deemed uninformative and may be discarded once they have been determined.

(766) In various exemplary embodiments, a change in pH for one or more wells may be measured as a nucleotide solution is flowed across the chip from an inlet to an outlet. A change in proton concentration may be measured both from the different pH of the nucleotide solution compared to the wash and due to the incorporation of nucleotides in a particular well. As a nucleotide solution is flowing across a chip including wells, for example, the nucleotide solution may displace an existing wash solution in a period of microseconds or milliseconds. Different parts or regions of such a chip may be measuring different solutions as the nucleotide flows across the chip. For example, a region near the fluidic inlet may initially be exposed to the nucleotide solution while another region near the fluidic outlet is still measuring wash solution. Because a polymerase can operate relatively quickly, an incorporation signal may also happen relatively quickly and the nucleotide flow may be viewed as a wave of concentration washing across the chip. In an embodiment, the time during which such a wave is washing over a particular region may be deemed the most important for measuring the incorporation signal. Such a time may be determined empirically. For example, the shape of such a wave may be measured empirically over a chip including wells for 6464 sized regions, for example, over a number of sites by looking for the change in pH when the nucleotide replaces the wash solution above the well. Regions of other sizes (e.g., NM where N and M are positive integers) are also possible and may include regions comprising any of the possible subsets of wells that may be in a sensor array. In an embodiment, such a model may look for a change point by finding the best fit to a linear hinge model on the median trace for a region, which may yield results that are very reproducible across runs and sites for standard operating procedure conditions.

(767) In various exemplary embodiments, a compression scheme may exploit the property of nucleotide wash reaching different parts of a chip at different points in time. The frames acquired for any region of the chip before start of the nucleotide flow may be identified as not containing any information regarding the incorporation and may thus only be used to obtain a good estimate of the pH before the nucleotide wash. Therefore, these frames may advantageously not be stored for any region before the nucleotide wash has reached such region to minimize and/or reduce downstream computational burden. Instead, an average of the frames not recorded in this process may be used to better estimate the pH of the region for that time period. The time at which nucleotide starts flowing over a well or region (which may be referred to as t0 (time zero) herein), may be determined for each region of the chip by mining several past analysis runs for a particular chip type. In some cases, a single DAT file produced through this compression scheme may be 10%-15% smaller in size for exemplary ION TORRENT chips of the 31X series, and such a compression performance may be even more significant for larger chips. The benefits of compression become increasingly important as data sizes increase. Indeed, for an Ion Proton I chip, which has about 165 million wells, at 30 frames per second for 300 flows and 6 seconds per acquisition there could be about 165,000,000 wells*30 frames/second*14 bits*6 seconds/acquisition*300 flows/(8*1e6)=15,592,500, which is about 15 terabytes of data. Moreover, the number of wells and flows are expected to increase, leading to even higher amounts of data and a greater need for improved compression. In an embodiment, this compression scheme may advantageously be used in conjunction with variable frame rate if different parts of the time series can be sampled at different rates. For example, one variable frame rate scheme would be the maximum frame rate at time zero during incorporation but sample multiple data points later when the protons are diffusing out of the well at a relatively constant rate. In other embodiments, this compression scheme may advantageously be used in conjunction with both variable frame rate and keyframe delta compression.

(768) In various exemplary embodiments, a fluid containing a nucleotide solution may hit different portions of a sensor array at different times, and such times may be determined and used in data analysis as representative of a point at which an enzyme can begin to incorporate nucleotides in the nucleotide solution. In some cases, such times may be determined empirically by looking for a change point in the pH as a solution of a different pH is flowed over the sensor array, including the nucleotide solution itself which has a different pH than the wash buffer, as sensors will begin to measure a different voltage when exposed to different pH solution. In various embodiments, one or more change point detection algorithms, see chapter 2 of Jie Chen & A. K. Gupta, Parametric Statistical Change Point Analysis (Oberwolfach Seminars), Birkhauser (2000), which is incorporated herein by reference in its entirety, may be used to detect the change point. One possible algorithm is to compare a fit of a piecewise linear hinge model to a single linear model in a sliding window and look for the point at which fitting two linear models improves the fit the most compared to that of a single line within that window. In the case of a sensor array having multiple wells, if the data are locally linear the point where the best fitting piecewise linear models meet would be the change point, or to, where the nucleotide starts washing over the well. This model could be fit on a summary of any subset of wells or on a single well at a time.

(769) In various exemplary embodiments, a waveform obtained using any of the foregoing exemplary embodiments (whether pre- or post-compression) may be compressed (or further compressed) using a combination of a truncation process (such as described above) and a substitution process as described next. In an embodiment, the truncation process may be a t0 compression process as described above. In an exemplary substitution process, a waveform (or portion thereof) may be replaced with a substitute representation, which may be another waveform or a set of parameters or coefficients that can be stored very compactly while allowing downstream reconstruction of the waveform or otherwise remaining representative of the initial waveform in some way. Such an approach may reduce data storage needs to a minimal amount of data yielding a maximal amount of sequencing accuracy.

(770) FIG. 92 illustrates three exemplary waveforms with or without compression using a substitution process. The top waveform (blue) represents an initial waveform sampled at different rates, with sparser sampling at the beginning and end of the waveform and denser sampling in the transitory portion of the waveform. This waveform consists of 55 frames of data, which would require about 55 bytes to store delta compressed. The middle waveform (red, and shifted down by 100 counts for visibility purposes) represents a slightly less dense, processed waveform. Once an appropriate cut-off point (e.g., t0) has been determined, this waveform could be truncated down to 32 frames of data, which would require about 32 bytes to store delta compressed Finally, the bottom waveform (blue, and shifted down by 200 counts for visibility purposes) represents the waveform resulting from the projection of the middle waveform onto the first eight eigenvectors or principal components of a covariance matrix computed from data from a sensor array. For example, the covariance matrix may be computed as =XX.sup.T, where X represents a matrix with a row for each frame and a column for each sensor on a sensor array such as described herein. By representing the bottom waveform using the coefficients of eight (for example) eigenvectors or principal components, the bottom waveform would require about 14 bytes of data per flow per well, which represents a significant reduction, which can significantly improve data analysis performance when processing very large numbers of wells (e.g., millions, or more).

(771) In various exemplary embodiments, the waveform substitution process may include determining one or more parameters characterizing the waveform. The one or more parameters may be selected from a larger set of parameters used for downstream analysis. In an example, the one or more parameters may include a tmid_nuc parameter (which may be expressed as time or data frame) characterizing a point in time at which concentration of the nucleotide has risen halfway to the final nucleotide concentration in a nucleotide concentration rise, and a sigma parameter (which may be expressed as a rate or speed) characterizing a rate or speed of the nucleotide concentration rise. These parameters may be determined or estimated based on certain characteristics of a representative nucleotide incorporation curve and existing relationships between the tmid_nuc and sigma parameters and those characteristics. In an embodiment, at least one of these parameters may be related to a t0 (time zero) parameter of the truncation process, such as described above, which may be used in combination with the substitution process. In the case of tmid_nuc, a relationship exists as a start of nucleotides hitting a well is related to a point in time at which concentration of the nucleotide has risen halfway to the final nucleotide concentration. In the case of the sigma parameter, a relationship exists as pH is related to the nucleotide concentration above the well and is related to the speed of the rise of concentration of nucleotide in the well. These parameters may be determined based on the data using any suitable waveform analysis or curve fitting methods or models known in the art. For example, in an embodiment the parameters could be determined using linear regression after a suitable transformation of data as seen in FIGS. 93 and 94 with t0 being estimated determined using some suitable change point detection algorithms, such as by finding a best fit to a linear hinge model on a median trace for a region, for example.

(772) FIG. 93 illustrates a relationship between sigma and a rate of proton concentration change (in frames per count) after t0 (time zero). Any suitable statistical method or model may be used to define a relationship between sigma and the rate of proton concentration change, such as, e.g., a linear regression. As shown, a linear relationship could be used to relate sigma to the rate of proton concentration change.

(773) FIG. 94 illustrates a relationship between tmid_nuc and time zero. Any suitable statistical method or model may be used to define a relationship between tmid_nuc and time zero. As shown, there is typically a relatively tight fit between tmid_nuc and time zero, and an estimate of the latter typically serves as a good estimate of the former.

(774) FIG. 95 illustrates exemplary time zero points and rates of pH changes after time zero based on raw data for wells in different regions on a chip. The vertical axis represents DC offset subtracted counts, and the horizontal axis represents time. The exemplary regions are the inlet, lower right, middle, and outlet regions. In the upper panel, the wells are empty. In the lower panel, the wells are non-empty.

(775) In various exemplary embodiments, the waveform may be stored in a smaller number of bytes than originally generated but containing exactly the same information using compression schemes, for example by using zip and Huffman codes or other such lossless compression techniques. In some cases, delta compression as described above, which appears to be particularly useful given the generally smooth nature (e.g., with relatively small changes in counts between consecutive time points) of nucleotide incorporation waveforms, may be used. In an example, in addition to delta compression, residuals may be stored using a Huffman code in which multiple wells are packed into bits as small as possible with a prefix specifying that number for writing.

(776) In various exemplary embodiments, the waveform may be stored in a smaller number of bytes than originally generated, while allowing for some difference in the information being stored, for example by using compression schemes such as JPEG or other lossy compression techniques. In an embodiment, the waveform may be represented by a linear combination of the first N principal component vectors (eigenvectors of the covariance matrix, also sometimes referred to as a normalized scatter matrix), as most of the information is contained in the first 5 or 6 principal components, for example, and waveforms from individual wells may advantageously be well represented by only the coefficients for these eigenvectors for compact storage. In various embodiments, these coefficients may in turn be stored compactly by dynamically truncating them to lower precision and storing them compactly using Huffman codes or any other suitable encoding scheme. Although most of the information is contained in the first 5 or 6 principal components here, that is only an example. In general, depending on characteristics of an underlying sequencing system or technology, as well as trade-off between a desire to leave data as close as possible to raw data and a need to increase speed without unduly affecting accuracy, fewer or more principal components could be used. For example, 1, 2, 3, 4, 5, 6, 7, 8, 9, or 10, or more principal components could be used. An overview of principal component analysis may be found in Pearson, K., On Lines and Planes of Closest Fit to Systems of Points in Space, Philosophical Magazine, Vol. 2, No. 11, pp. 559-572 (1901), and Abdi et al., Principal component analysis, Wiley Interdisciplinary Reviews: Computational Statistics, Vol. 2, No. 4, pp. 433-459 (2010).

(777) FIG. 96 illustrates relative weights of eigenvalues corresponding to the eigenvectors of the covariance matrix for wells in a 100 by 100 spatially contiguous region of a chip. As shown, most of the information is contained in the first 5 or 6 eigenvectors (ranked from right to left, noting that the relative weight of the first eigenvalue is not actually displayed given that it is so large relative to the weight of the others), and the relative weight of subsequent eigenvectors diminishes gradually.

(778) FIG. 97 illustrates residuals per frame using a linear combination of the first 5 eigenvectors to represent wells in a 100 by 100 spatially contiguous region of a chip. As shown, the residuals are generally unbiased and relatively stable over time through different frames. Here, the eigenvectors are specific to a contiguous region and the linear coefficients to the eigenvectors are specific to each well. Thus, if the measurements for a well are X, then what are found are the coefficients a.sub.1, a.sub.2, . . . , a.sub.n for eigenvectors b.sub.1, b.sub.2, . . . , b.sub.n such that Y=X(a.sub.1b.sub.1+a.sub.2b.sub.2+ . . . +a.sub.nb.sub.n) is minimized, where a.sub.n are optimized for the well and b.sub.n are the eigenvectors for the region. Any suitable mathematical optimization technique or algorithm may be used to obtain the coefficients minimizing Y.

(779) FIGS. 98(a)-98(f) illustrate an exemplary linear combination of eigenvectors. FIG. 98(a) shows curve 9801, which represents raw time compressed data, and curve 9802, which represents a substitute representation corresponding to a linear combination of the first five eigenvectors. FIG. 98(b) shows the curve corresponding to the first eigenvector of the covariance matrix. FIG. 98(c) shows the curve corresponding to the second eigenvector of the covariance matrix. FIG. 98(d) shows the curve corresponding to the third eigenvector of the covariance matrix. FIG. 98(e) shows the curve corresponding to the fourth eigenvector of the covariance matrix. FIG. 98(f) shows the curve corresponding to the fifth eigenvector of the covariance matrix. In the figures, the x-axis represents frames and the y-axis represents counts. In this example, the coefficients for the linear combination are 1859.776, 108.725, 86.296, 16.849, and 0.300, respectively.

(780) FIG. 99 illustrates an exemplary method for compression of sequencing data. In step 9901, a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction, is measured. In step 9902, a first compression process is applied to the waveform, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction. In step 9903, a second compression process is applied to the waveform, the second compression process including a data substitution process that replaces at least a portion of the waveform with a plurality of coefficients representative of the portion of the waveform.

(781) According to an embodiment, a time zero point and post time zero slope may be obtained or determined for each well in a set of wells. This may be done using any of the approaches described above regarding the t0 compression process and determination of cut-off points or t0 values, or using any other suitable curve fitting and/or analysis method or model. A tmid_nuc and sigma parameters may be determined during a first nucleotide flow based on the time zero point and post time zero slope. For example, in an embodiment the parameters could be determined using linear regression after a suitable transformation of data as seen in FIGS. 93 and 94, with t0 being estimated determined using some suitable change point detection algorithms, such as by finding a best fit to a linear hinge model on a median trace for a region, for example. A waveform for a second nucleotide flow may then be acquired, projected into a processed waveform having a desired variable frame rate using principal component analysis, and replaced with a set of coefficients of projections of the processed waveform onto one or more principal components of a covariance matrix, which can be stored more compactly. For example, instead of storing the entire frame (N.sub.frames)wells (N.sub.wells) matrix X for a region, one could store the first N.sub.eigen vectors, where N.sub.eigen<<N.sub.wells and then store the coefficients where N.sub.eigen<N.sub.frames, thereby storing only N.sub.eignN.sub.wells entries total.

(782) According to an exemplary embodiment, there is provided a compression method, comprising: measuring a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction; applying a first compression process to the waveform, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction; and applying a second compression process to the waveform, the second compression process including a data substitution process that replaces at least a portion of the waveform with a plurality of coefficients representative of the portion of the waveform.

(783) In such a method, the truncating of data may comprise determining, for each of a plurality of sensors in the sensor array, a cut-off time point for the waveform for that sensor defining a data range to be truncated. Each cut-off time point may be determined by mining a plurality of past analysis runs for a given sensor array geometry. Each cut-off time point may be determined prior to every run or during a calibration procedure. Each cut-off time point may be factory pre-determined for a given sensor array geometry. The sensors may be arranged in a plurality of regions in the sensor array, and each cut-off time point for sensors in a given region may be determined to have a common cut-off time point determined for sensors for that region. Each common cut-off time point may be determined by finding a best fit to a linear hinge model on a median trace for a region. Each common cut-off time point may be determined empirically and may depend on a position of that region relative to other regions along a fluidic flow of nucleotides onto the sensor array. The cut-off time point of sensors in a region substantially near a fluidic inlet may be different from the cut-off time point of sensors in a region substantially near a fluidic outlet.

(784) In such a method, the second compression process may include replacing the waveform with a plurality of coefficients of a linear combination of one or more principal component vectors representative of the portion of the waveform. The second compression process may include storing the plurality of coefficients compactly by dynamically truncating the coefficients to a lower precision and encoding the truncated coefficients using a Huffman code. The second compression process may include replacing the portion of the waveform with a plurality of coefficients of a linear combination of between about 5 and about 10 principal component vectors representative of the portion of the waveform. The second compression process may include replacing the portion of the waveform with a plurality of coefficients of a linear combination of 5 or 6 principal component vectors representative of the portion of the waveform.

(785) Measuring the waveform may comprise measuring the waveform of a dynamic response of an ion-sensitive field effect transistor (ISFET) array to a change in ionic strength of an analyte solution in fluid contact with the ISFET array. Measuring the waveform of the dynamic response of the ISFET array may comprise associating a portion of the waveform to a stepwise increase in ion concentration in the analyte solution and associating another portion of the waveform to at least one portion of the dynamic response outside of the stepwise increase in ion concentration.

(786) According to an exemplary embodiment, there is provided a computer program product comprising a non-transitory computer-usable medium having computer program logic recorded thereon that, when executed by one or more processors, samples and compresses data from a sensor array, the computer program logic comprising: first computer readable program code that enables a processor to measure a waveform associated with a chemical event occurring on a sensor array, wherein the waveform comprises a plurality of measured values and the chemical event is indicative of a number of nucleotide incorporations in a genetic sequencing reaction; second computer readable program code that enables a processor to apply a first compression process to the waveform, the first compression process including a truncating of data corresponding to a portion of the waveform that is not related to nucleotide incorporations in the genetic sequencing reaction; and computer readable program code that enables a processor to apply a second compression process to the waveform, the second compression process including replacing at least a portion of the waveform with a plurality of coefficients representative of the portion of the waveform.

(787) According to an exemplary embodiment, there is provided a method for compressing nucleic acid sequencing data, comprising: obtaining raw data from a semiconductor-based sequencing sensor array comprising a plurality of sensors during a data acquisition time period, the raw data comprising at least a non-informative portion corresponding to a subinterval of the data acquisition time period having a location within the data acquisition time period that varies for different sensors according to a position of the sensor in the sensor array; and transforming the raw data into compressed data using both (1) a lossless compression process and (2) lossy compression processes including a data truncation process and a data substitution process, the data truncation process being related for each sensor to the position of the sensor in the sensor array and configured to discard the non-informative portion of the raw data, and the data substitution process being adapted to replace the raw data for each sensor with a plurality of coefficients of a linear combination of one or more principal component vectors representative of the raw data for each sensor.

(788) In such a method, the data substitution process may comprise storing the plurality of coefficients compactly by dynamically truncating the coefficients to a lower precision and encoding the truncated coefficients using a Huffman code. The data substitution process may comprise replacing the raw data for each sensor with a plurality of coefficients of a linear combination of between about 5 and about 10 principal component vectors representative of the raw data for each sensor. The data substitution process may comprise replacing the raw data for each sensor with a plurality of coefficients of a linear combination of 5 or 6 principal component vectors representative of the raw data for each sensor.

(789) Example Computer System

(790) Various aspects of the embodiments described herein may be implemented in software, firmware, hardware, or a combination thereof. FIG. 83 is an illustration of an example computer system 8300 in which embodiments described herein, or portions thereof, can be implemented as computer-readable code. For example, the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81 can be implemented in computer system 8300. Various embodiments are described in terms of this example computer system 8300.

(791) After reading the description herein, it will become apparent to a person skilled in the relevant art how to implement embodiments described herein using other computer systems and/or computer architectures. For instance, in an embodiment, computer system 8300 (or a portion thereof) may be a stand-alone computing system (e.g., array controller 250 of FIG. 17) that communicates with array 100 of FIG. 17 to perform the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81. In another embodiment, computer system 8300 (or a portion thereof) can be integrated as an on-chip controller on a device incorporating array 100 to perform the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81. In yet another embodiment, computer system 8300 (or a portion thereof) can be implemented as a stand-alone computer system and an on-chip controller that communicates with array 100 to perform the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81.

(792) Computer system 8300 can be any commercially available and well known computer capable of performing the functions described herein, such as computers available from International Business Machines, Apple, Sun, HP, Dell, Compaq, Cray, etc.

(793) Computer system 8300 includes one or more processors, such as processor 8304. Processor 8304 may be a special purpose or a general-purpose processor. Processor 8304 is connected to a communication infrastructure 8306 (e.g., a bus or network).

(794) Computer system 8300 also includes a main memory 8308, preferably random access memory (RAM), and may also include a secondary memory 8310. Main memory 8308 has stored therein a control logic 8309 (computer software) and data. Secondary memory 8310 can include, for example, a hard disk drive 8312, a removable storage drive 8314, and/or a memory stick. Removable storage drive 8314 can comprise a floppy disk drive, a magnetic tape drive, an optical disk drive, a flash memory, or the like. The removable storage drive 8314 reads from and/or writes to a removable storage unit 8317 in a well-known manner Removable storage unit 8318 can include a floppy disk, magnetic tape, optical disk, etc. which is read by and written to by removable storage drive 8318. As will be appreciated by persons skilled in the relevant art, removable storage unit 8317 includes a computer-usable storage medium 8318 having stored therein a control logic 8319 (e.g., computer software) and/or data.

(795) In alternative implementations, secondary memory 8310 can include other similar devices for allowing computer programs or other instructions to be loaded into computer system 8300. Such devices can include, for example, a removable storage unit 8322 and an interface 8320. Examples of such devices can include a program cartridge and cartridge interface (such as those found in video game devices), a removable memory chip (e.g., EPROM or PROM) and associated socket, and other removable storage units 8322 and interfaces 8320 which allow software and data to be transferred from the removable storage unit 8322 to computer system 8300.

(796) Computer system 8300 also includes a display 8330 that communicates with computer system 8300 via a display interface 8302. Although not shown in computer system 8300 of FIG. 83, as would be understood by a person skilled in the relevant art, computer system 8300 can communicate with other input/output devices such as, for example and without limitation, a keyboard, a pointing device, and a Bluetooth device.

(797) Computer system 8300 can also include a communications interface 8324. Communications interface 8324 allows software and data to be transferred between computer system 8300 and external devices. Communications interface 8324 can include a modem, a network interface (such as an Ethernet card), a communications port, a PCMCIA slot and card, or the like. Software and data transferred via communications interface 8324 are in the form of signals, which may be electronic, electromagnetic, optical, or other signals capable of being received by communications interface 8324. These signals are provided to communications interface 8324 via a communications path 8326. Communications path 8326 carries signals and may be implemented using wire or cable, fiber optics, a phone line, a cellular phone link, a RF link or other communications channels.

(798) In this document, the terms computer program medium and computer-usable medium are used to generally refer to media such as removable storage unit 8317, removable storage unit 8318, and a hard disk installed in hard disk drive 8312. Computer program medium and computer-usable medium can also refer to memories, such as main memory 8308 and secondary memory 8310, which can be memory semiconductors (e.g., DRAMs, etc.). These computer program products provide software to computer system 8300.

(799) Computer programs (also called computer control logic) are stored on main memory 8308 and/or secondary memory 8310. Computer programs may also be received via communications interface 8324. Such computer programs, when executed, enable computer system 8300 to implement embodiments described herein. In particular, the computer programs, when executed, enable processor 8304 to implement processes described herein, such as the steps in the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81, discussed above. Accordingly, such computer programs represent controllers of the computer system 8300. Where embodiments are implemented using software, the software can be stored on a computer program product and loaded into computer system 8300 using removable storage drive 8314, interface 8320, hard drive 8312 or communications interface 8324.

(800) Based on the description herein, a person skilled in the relevant art will recognize that the computer programs, when executed, can enable one or more processors to implement processes described above, such as the steps in the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81. In an embodiment, the one or more processors can be part of a computing device incorporated in a clustered computing environment or server farm. Further, in an embodiment, the computing process performed by the clustered computing environment such as, for example, the steps in the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 may be carried out across multiple processors located at the same or different locations.

(801) Based on the description herein, a person of skilled in the relevant art will recognize that the computer programs, when executed, can enable multiple processors to implement processes described above, such as the steps in the methods illustrated in the flowchart of FIG. 18B and flowchart 8100 of FIG. 81. In an embodiment, the computing process performed by the multiple processors can be carried out across multiple processors located at a different location from one another.

(802) Embodiments are also directed to computer program products including software stored on any computer-usable medium (e.g., computer useable medium 8318 and 8331). Such software, when executed in one or more data processing device, causes a data processing device(s) to operate as described herein. Embodiments employ any computer-usable or -readable medium, known now or in the future. Examples of computer-usable mediums include, but are not limited to, primary storage devices (e.g., any type of random access memory), secondary storage devices (e.g., hard drives, floppy disks, CD ROMS, ZIP disks, tapes, magnetic storage devices, optical storage devices, MEMS, nanotechnological storage devices, etc.), and communication mediums (e.g., wired and wireless communications networks, local area networks, wide area networks, intranets, etc.).

(803) Embodiments have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

(804) According to various embodiments, one or more features of any one or more of the above-discussed teachings and/or embodiments may be performed or implemented using appropriately configured and/or programmed hardware and/or software elements. Determining whether an embodiment is implemented using hardware and/or software elements may be based on any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds, etc., and other design or performance constraints.

(805) Examples of hardware elements may include processors, microprocessors, input(s) and/or output(s) (I/O) device(s) (or peripherals) that are communicatively coupled via a local interface circuit, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, application specific integrated circuits (ASIC), programmable logic devices (PLD), digital signal processors (DSP), field programmable gate array (FPGA), logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. The local interface may include, for example, one or more buses or other wired or wireless connections, controllers, buffers (caches), drivers, repeaters and receivers, etc., to allow appropriate communications between hardware components. A processor is a hardware device for executing software, particularly software stored in memory. The processor can be any custom made or commercially available processor, a central processing unit (CPU), an auxiliary processor among several processors associated with the computer, a semiconductor based microprocessor (e.g., in the form of a microchip or chip set), a macroprocessor, or generally any device for executing software instructions. A processor can also represent a distributed processing architecture. The I/O devices can include input devices, for example, a keyboard, a mouse, a scanner, a microphone, a touch screen, an interface for various medical devices and/or laboratory instruments, a bar code reader, a stylus, a laser reader, a radio-frequency device reader, etc. Furthermore, the I/O devices also can include output devices, for example, a printer, a bar code printer, a display, etc. Finally, the I/O devices further can include devices that communicate as both inputs and outputs, for example, a modulator/demodulator (modem; for accessing another device, system, or network), a radio frequency (RF) or other transceiver, a telephonic interface, a bridge, a router, etc.

(806) Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (API), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. A software in memory may include one or more separate programs, which may include ordered listings of executable instructions for implementing logical functions. The software in memory may include a system for identifying data streams in accordance with the present teachings and any suitable custom made or commercially available operating system (O/S), which may control the execution of other computer programs such as the system, and provides scheduling, input-output control, file and data management, memory management, communication control, etc.

(807) According to various embodiments, one or more features of any one or more of the above-discussed teachings and/or embodiments may be performed or implemented using appropriately configured and/or programmed non-transitory machine-readable medium or article that may store an instruction or a set of instructions that, if executed by a machine, may cause the machine to perform a method and/or operations in accordance with the embodiments. Such a machine may include, for example, any suitable processing platform, computing platform, computing device, processing device, computing system, processing system, computer, processor, scientific or laboratory instrument, etc., and may be implemented using any suitable combination of hardware and/or software. The machine-readable medium or article may include, for example, any suitable type of memory unit, memory device, memory article, memory medium, storage device, storage article, storage medium and/or storage unit, for example, memory, removable or non-removable media, erasable or non-erasable media, writeable or re-writeable media, digital or analog media, hard disk, floppy disk, read-only memory compact disc (CD-ROM), recordable compact disc (CD-R), rewriteable compact disc (CD-RW), optical disk, magnetic media, magneto-optical media, removable memory cards or disks, various types of Digital Versatile Disc (DVD), a tape, a cassette, etc., including any medium suitable for use in a computer. Memory can include any one or a combination of volatile memory elements (e.g., random access memory (RAM, such as DRAM, SRAM, SDRAM, etc.)) and nonvolatile memory elements (e.g., ROM, EPROM, EEROM, Flash memory, hard drive, tape, CDROM, etc.). Moreover, memory can incorporate electronic, magnetic, optical, and/or other types of storage media. Memory can have a distributed architecture where various components are situated remote from one another, but are still accessed by the processor. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, encrypted code, etc., implemented using any suitable high-level, low-level, object-oriented, visual, compiled and/or interpreted programming language.

(808) According to various embodiments, one or more features of any one or more of the above-discussed teachings and/or embodiments may be performed or implemented at least partly using a distributed, clustered, remote, or cloud computing resource.

(809) According to various embodiments, one or more features of any one or more of the above-discussed teachings and/or embodiments may be performed or implemented using a source program, executable program (object code), script, or any other entity comprising a set of instructions to be performed. When a source program, the program can be translated via a compiler, assembler, interpreter, etc., which may or may not be included within the memory, so as to operate properly in connection with the O/S. The instructions may be written using (a) an object oriented programming language, which has classes of data and methods, or (b) a procedural programming language, which has routines, subroutines, and/or functions, which may include, for example, C, C++, Pascal, Basic, Fortran, Cobol, Perl, Java, and Ada.

(810) While various embodiments have been described above, it should be understood that they have been presented by way of example only, and not limitation. It will be understood by those skilled in the relevant art that various changes in form and details can be made therein without departing from the spirit and scope of the embodiments described herein. It should be understood that this description is not limited to these examples. This description is applicable to any elements operating as described herein. Accordingly, the breadth and scope of this description should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

(811) Each of the following is incorporated by reference herein in its entirety: U.S. patent application Ser. No. 13/334,747, filed Dec. 22, 2011, titled Methods and Apparatus for Measuring Analytes; U.S. patent application Ser. No. 12/475,311, filed May 29, 2009, titled Methods and Apparatus for Measuring Analytes; U.S. patent application Ser. No. 13/340,490, filed Dec. 29, 2011, titled Methods, Systems, and Computer Readable Media for Nucleic Acid Sequencing; and U.S. Prov. Pat. Appl. No. 61/428,733, filed Dec. 30, 2010, titled Apparatus, Methods, and Software for Performing Electrochemical Reactions, and the contents of each of which are incorporated by reference herein in their entireties.