All-CMOS, low-voltage, wide-temperature range, voltage reference circuit

Abstract

A CMOS voltage reference is disclosed. The CMOS voltage reference may include a PTAT current bias circuit including a start-up circuit, a core module implementing high order non-linear curvature compensation and an output stage supplying the reference voltage. The CMOS voltage reference may include a PTAT current bias circuit having a start-up and a CTAT feedback loop and a PTAT feedback loop and a compensating circuit summing the current from the CTAT feedback loop and the PTAT feedback loop.

Claims

1. A complementary metal oxide semiconductor voltage reference, comprising: a PTAT biasing circuit including a start-up circuit; a core module implementing high-order non-linear compensation, the core module biased by the PTAT circuit, the core module including: a first P-type CMOS transistor coupled to a VDD voltage and having a gate that is driven by a feedback loop originating from a first node, the first P-type CMOS transistor also including a drain terminal; a first N-type subthreshold CMOS transistor having a gate and a drain coupled to the drain of the first P-type CMOS transistor at the first node and a source coupled to a common voltage; a source-degenerated second N-type subthreshold CMOS transistor; a series resistance, including a high-resistivity poly-silicon resistor and a low-temperature coefficient poly-silicon resistor in series, coupled between the first node and the common voltage so as to generate a node voltage at the first node, the node voltage coupled to the gate of the source-degenerated second N-type subthreshold CMOS transistor, the first N-type subthreshold CMOS transistor and the second N-type subthreshold CMOS transistor, the high-resistivity poly-silicon resistor and the low-temperature coefficient poly-silicon resistor having complimentary non-linear responses to changes in temperature; the second N-type CMOS transistor controlling a gate voltage of a third N-type CMOS transistor via the drain terminal, in conjunction with a PTAT circuit bias; and the third N-type CMOS transistor controlling a gate voltage of the first P-type CMOS transistor via a diode-connected second P-type transistor, in which the second P-type transistor shares a common gate voltage with the first P-type transistor; and an output stage including a P-type CMOS transistor and two different types of polysilicon resistors in series, responsive to the core module and the feedback loop, for supplying reference voltage in order to provide a reference voltage at an output.

2. The complementary metal oxide semiconductor voltage reference according to claim 1, wherein the poly-silicon resistors utilize a trimming methodology to concurrently trim plurality of non-linearities and slope of the reference voltage.

3. The complementary metal oxide semiconductor voltage reference according to claim 2, wherein the complementary metal oxide semiconductor voltage reference compensates for the non-linearities and the slope performed between a transistor MN.sub.5 and the poly-silicon resistors.

4. The complementary metal oxide semiconductor voltage reference according to claim 3, wherein the reference voltage is dependent from the poly-silicon resistors and the transistor MN.sub.5 to provide a temperature insensitive voltage.

5. The complementary metal oxide semiconductor voltage reference according to claim 1, wherein the poly-silicon resistors are set so as to minimize temperature coefficient.

6. The complementary metal oxide semiconductor voltage reference according to claim 1, wherein the complementary metal oxide semiconductor voltage reference utilizes temperature-dependent threshold voltage and carrier mobility of a MOSFET to generate a plurality of PTAT and complementary to absolute temperature CTAT currents, which are summed in order to provide a first order compensated voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The present invention will be described by way of exemplary embodiments, but not limitations, illustrated in the accompanying drawings in which like references denote similar elements, and in which:

(2) FIG. 1 illustrates a medium ohmic p-type poly-silicon resistor versus temperature graph, a sub-threshold CMOS versus temperature graph and a high ohmic p-type poly resistor versus temperature graph, in accordance with one embodiment of the present invention.

(3) FIG. 2 illustrates an electrical schematic of a voltage reference, in accordance with one embodiment of the present invention.

(4) FIG. 3 illustrates a graph of a plurality of deviations of the non-linearities influencing the TD of a reference voltage, in accordance with one embodiment of the present invention.

(5) FIG. 4 illustrates a graph of a plurality of deviations of the slope influencing the TD of the reference voltage, in accordance with one embodiment of the present invention.

(6) FIG. 5 illustrates a graph of simulated TD of a voltage reference output, in accordance with one embodiment of the present invention.

(7) FIG. 6 illustrates a graph of measured TD of a voltage reference output biased at 0.7V, in accordance with one embodiment of the present invention.

(8) FIG. 7 illustrates a graph of a measured and simulated PSRR of the proposed topology with different biased voltages at 27 C., in accordance with one embodiment of the present invention.

(9) FIG. 8 illustrates a graph of a measured noise spectrum of the proposed topology biased at 0.7V for 60 C., 27 C. and 125 C., in accordance with one embodiment of the present invention.

(10) FIG. 9 illustrates an electrical schematic of a voltage reference, in accordance with one embodiment of the present invention.

(11) FIG. 10 illustrates a graph of a high resistivity poly-silicon resistor, low temperature coefficient poly-silicon resistor and NMOS sub-threshold transistor, current versus temperature, for a given bias voltage, in accordance with one embodiment of the present invention.

(12) FIG. 11 illustrates a graph of a simulated temperature drift of the reference voltage over a temperature range of 190 C. (45 C. to 145 C.), in accordance with one embodiment of the present invention.

(13) FIG. 12 illustrates a graph of a simulated performance throughout the temperature range (45 C. to 145 C.) and the supply voltage range (0.4 V to 2 V), in accordance with one embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(14) Various aspects of the illustrative embodiments will be described utilizing terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present invention may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials and configurations are set forth in order to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to one skilled in the art that the present invention may be practiced without the specific details. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative embodiments.

(15) Various operations will be described as multiple discrete operations, in turn, in a manner that is most helpful in understanding the present invention. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations need not be performed in the order of presentation.

(16) The phrase in one embodiment is used repeatedly. The phrase generally does not refer to the same embodiment, however, it may. The terms comprising, having and including are synonymous, unless the context dictates otherwise.

(17) The drain-source current in CMOS transistors, which operate in the sub-threshold region depends exponentially on the gate-source voltage and drain-source voltage:

(18) $I_{\mathrm{DS}}={\mathrm{KI}}_0\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)\left(1-\exp \left(-\frac{V_{\mathrm{DS}}}{U_T}\right)\right)$

(19) where K is the transistor size aspect ratio W.sub.eff/L.sub.eff, V.sub.TH is the transistor threshold voltage and where U.sub.T=KT/q is the thermal voltage that is temperature dependent. I.sub.0 may be described by:
I.sub.0=C.sub.ox(n1)U.sub.T.sup.2

(20) where is the mobility of carriers in the device channel, C.sub.ox is the oxide capacitance per unit area and n is the sub-threshold slope factor which is expressed as:

(21) $n=1+\frac{C_d}{C_{\mathrm{ox}}}$

(22) where C.sub.d is the surface depletion capacitance per unit area and is described by:

(23) $C_d=\sqrt{q{\mathrm{.Math.}}_{\mathrm{si}}\frac{N_{\mathrm{CH}}}{2{}_S}}$

(24) where q is the electron charge, si is the silicon permittivity, N.sub.CH is the doping concentration of the channel and .sub.S is the surface potential. The device is considered to be in the saturation region if the following equation is valid:

(25) $1\exp \left(-\frac{V_{\mathrm{DS}}}{U_T}\right)$

(26) Inequality of the above equation is valid approximately when V.sub.DS4U.sub.T. Thus, the dependence of I.sub.DS in saturation becomes:

(27) $I_{\mathrm{DS}}=K{C}_{\mathrm{ox}}\left(n-1\right)U_T^2\exp \left(\frac{V_{\mathrm{GS}}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)$

(28) Investigating, the drain-source current temperature dependencies are the thermal voltage, the threshold voltage and the mobility. The mobility temperature dependence is approximately expressed as:

(29) $\left(T\right)={{}_0\left(\frac{T}{T_0}\right)}^{-m}$
where .sub.0 is the mobility at room temperature T.sub.0, T is the absolute temperature and m is the mobility temperature exponent which is a technology dependent constant. The threshold voltage and gate-source voltage temperature dependence may be expressed as

(30) $V_{\mathrm{TH}}\left(T\right)=V_{\mathrm{TH}}\left(T_0\right)+K_T\frac{T}{T_0}$$V_{\mathrm{GS}}\left(T\right)=V_{\mathrm{GS}}\left(T_0\right)+K_T\frac{T}{T_0}$
where K.sub.T is a negative number between 0.5 mV/ C. and 3 mV/ C. and depends on the doping level, oxide thickness and V.sub.SB. With increasing of temperature, the drain-source current is increased by threshold voltage and decreased by mobility. For low currents, the threshold voltage temperature dependence dominates, while for high currents the mobility temperature dependence dominates.

(31) FIG. 1 illustrates a medium ohmic p-type poly-silicon resistor versus temperature graph 100, a sub-threshold CMOS versus temperature graph 110 and a high ohmic p-type poly resistor versus temperature graph 120, in accordance with one embodiment of the present invention.

(32) The medium ohmic p-type poly-silicon resistor versus temperature graph 100 may have current readings on a y-axis 102 versus temperature readings in Celsius on an x-axis 104. The sub-threshold CMOS versus temperature graph 110 may have current on a y-axis 112 versus temperature readings in Celsius on an x-axis 114. The high ohmic p-type poly-silicon resistor versus temperature graph 120 may have current readings on a y-axis 122 versus temperature readings in Celsius on an x-axis 124.

(33) Considering all the demands and limitations of modern integrated circuit or IC applications, a novel, robust and high performance voltage reference is proposed. The methodology that was utilized in order to improve the temperature drift or TD performance is illustrated in FIG. 1, where the current is plotted as a function of temperature, for a given bias voltage, corresponding to the nominal bias point in the circuit. High ohmic p-type poly resistors and medium ohmic p poly resistors with different non-linearities opposed to the ones of sub-threshold CMOS were utilized in order to achieve high order compensation of the reference voltage.

(34) FIG. 2 illustrates an electrical schematic of a voltage reference 200, in accordance with one embodiment of the present invention.

(35) The voltage reference 200 may include a proportional to absolute temperature or PTAT circuit 210, a core module 220 and an output stage 230. The PTAT circuit 210 may be an electronic circuit transistor biasing that includes start-up circuits 212 such as MP.sub.su1, MP.sub.su2, C.sub.1. The core module 220 may implement high-order non-linear compensation. The output stage 230 may supply any reference voltage.

(36) The topology of the voltage reference design is illustrated in FIG. 2, where standard 0.18 m CMOS devices were utilized, with all transistors operating in sub-threshold. The topology includes three main modules shown in FIG. 2. A PTAT circuit, including the start-up circuit (MP.sub.su1, MP.sub.su2, C.sub.1), is shown in FIG. 2(a) which generates a PTAT current for supplying the module of FIG. 2(b). In the core module of FIG. 2(b), the high order non-linear compensation is performed, where MN.sub.4 is biased with a PTAT current from the PTAT circuit. While temperature increases, the gate source voltage of MN.sub.4 decreases, thus decreasing the voltage drop across R.sub.2, R.sub.3 and MN.sub.5. As a result, the current flow through R.sub.2, R.sub.3 is decreasing while the current flow through MN.sub.5 is increasing because of a simultaneous decrease of its threshold voltage. Thus the slope of the current IC is relatively compensated at a first order. The second level of compensation is performed by the use of the medium ohmic p poly resistors (R.sub.3 and R.sub.6), high ohmic p-type poly resistors (R.sub.2 and R.sub.5) and sub-threshold CMOS (MN.sub.4 and MN.sub.5). The use of these specific devices exploits their complimentary non-linear responses over temperature. As a result, a mutually compensated reference voltage is achieved, were both, the slope as well as the non-linearities are compensated over temperature. The final compensated current is mirrored in the output module of FIG. 2(c) where we get the reference voltage.

(37) The reference voltage is dependent from the current IC which constitutes from two currents, one through the resistors R.sub.2, R.sub.3 and the one through the transistor MN.sub.5. By selecting a proper ratio between the two currents, the topology may simply and effectively compensated through a straightforward method so as to provide a temperature insensitive voltage at the output. The reference voltage at the output of the proposed topology in FIG. 2 may be expressed as
V.sub.REF=I.sub.CR.sub.5,6

(38) where R.sub.x,y=R.sub.x+R.sub.y and the current IC consists of the currents through resistors R.sub.2 and R.sub.3, and the current through the transistor MN.sub.5 as:
I.sub.C=I.sub.R2,3+I.sub.MN5

(39) and may be expanded in the form of:

(40) $I_C=\frac{V_{\mathrm{GS}4}+I_{\mathrm{B\_PTAT}}{R}_4}{R_{2,3}}+K_{\mathrm{MN}5}{I}_0\exp \left(\frac{V_{\mathrm{GS}5}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)$

(41) applying some recalculations in, it may be rewritten as:

(42) $I_C=\frac{V_{\mathrm{GS}4}}{R_{2,3}}+\frac{R_4}{R_{2,3}}{I}_{\mathrm{B\_PTAT}}+K_{\mathrm{MN}5}{I}_0\exp \left(\frac{V_{\mathrm{GS}5}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)$

(43) The current through a PTAT circuit may be expressed by:

(44) 0$I_{\mathrm{PTAT}}=\frac{U_T}{R_1}+\frac{K_{\mathrm{MP}3}}{K_{\mathrm{MP}2}}\ln \left(\frac{K_{\mathrm{MP}2}{K}_{\mathrm{MN}2}}{K_{\mathrm{MP}1}{K}_{\mathrm{MN}1}}\right)$

(45) Where for this topology as shown in Table I the ratios:

(46) $\frac{{\mathrm{KMP}}_3}{{\mathrm{KMP}}_2}=1$$\mathrm{and}$$\frac{{\mathrm{KMP}}_2}{{\mathrm{KMP}}_1}=1$

(47) Substituting into, the current IC becomes of the form:

(48) $I_C=\frac{V_{\mathrm{GS}4}}{R_{2,3}}+\frac{R_4}{R_{2,3}}\frac{U_T}{R_1}\ln \left(\frac{K_{\mathrm{MN}2}}{K_{\mathrm{MN}1}}\right)+K_{\mathrm{MN}5}{I}_0\exp \left(\frac{\frac{U_T{R}_4}{R_1}\ln \left(\frac{K_{\mathrm{MN}2}}{K_{\mathrm{MN}1}}\right)+V_{\mathrm{GS}4}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)$

(49) TABLE-US-00001 TABLE I Circuit Elements Dimensions of the Proposed Voltage Reference Architecture Component Parameter MP.sub.su1 W = 3 m, L = 10 m MP.sub.su2 W = 2 m, L = 10 m MP.sub.1, MP.sub.2, MP.sub.3 W = 12 m, L = 4 m MR.sub.4, MP.sub.5, MP.sub.6 W = 20 m, L = 4 m MN.sub.1 W = 15 m, L = 4 m MN.sub.2 W = 300 m, L = 4 m MN.sub.3 W = 8 m, L = 8 m MN.sub.4 W = 100 m, L = 4 m MN.sub.5 W = 40 m, L = 4 m R.sub.1 (rpmpoly) 330 K R.sub.2 (rphpoly), R.sub.3 (rpmpoly) 500 K R.sub.4 (rphpoly) 220 K R.sub.5 (rphpoly) 157.5 K R.sub.6 (rpmpoly) 130 K C.sub.1 2 pF C.sub.2 3 pF

(50) Therefore by substituting the IC, the reference voltage becomes

(51) $V_{\mathrm{REF}}=\underset{\underset{}{}}{\frac{V_{\mathrm{GS}4}{R}_{5,6}}{R_{2,3}}}+\underset{\underset{}{}}{\frac{R_4{R}_{5,6}}{R_1{R}_{2,3}}{U}_T\ln \left(\frac{K_{\mathrm{MN}2}}{K_{\mathrm{MN}1}}\right)}+\underset{\underset{}{}}{R_{5,6}{K}_{\mathrm{MN}5}{I}_0\exp \left(\frac{V_{\mathrm{GS}5}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)}$

(52) It may be deduced that the resistors of the segments and are cancelling out between their numerator and denominator, thus the process variations of the resistors are not affecting the reference voltage slope. The resistors process variations are only affecting the non-linear part of the segment, where R5, 6 are remaining. Finally, replacing V.sub.GS5 with (I.sub.PTATR.sub.4+V.sub.GS4 a detailed equation of the output reference voltage of the proposed topology is obtained without considering the temperature dependence:

(53) $V_{\mathrm{REF}}=\underset{\underset{}{}}{\frac{V_{\mathrm{GS}4}{R}_{5,6}}{R_{2,3}}}+\underset{\underset{}{}}{\frac{R_4{R}_{5,6}}{R_1{R}_{2,3}}{U}_T\ln \left(\frac{K_{\mathrm{MN}2}}{K_{\mathrm{MN}1}}\right)}+\underset{\underset{}{}}{R_{5,6}{K}_{\mathrm{MN}5}{I}_0\exp \left(\frac{V_{\mathrm{GS}5}-V_{\mathrm{TH}}}{{\mathrm{nU}}_T}\right)}$

(54) At this point we may incorporate the temperature dependence of the transistors and resistors in order to tackle into the high order non-linear compensation which is the eliciting factor that limits the performance of the state of the art voltage references. The temperature dependence of the poly-silicon resistors that are utilized in the proposed topology is expressed by:
R.sub.x(T)=R.sub.x(T.sub.0)(1+T+T.sup.2)

(55) where and are technology dependent constants.

(56) After some calculations:

(57) $V_{\mathrm{REF}}=\underset{\underset{}{}}{\stackrel{\stackrel{{}_1}{}}{\frac{V_{\mathrm{GS}4}\left(T_0\right)R_{5,6}\left(T_0\right)}{R_{2,3}\left(T_0\right)}}+\stackrel{\stackrel{{}_2}{}}{K_T\frac{R_{5,6}\left(T_0\right)}{T_0{R}_{2,3}\left(T_0\right)}}T}+\underset{\underset{}{}}{\frac{R_4\left(T_0\right)R_{5,5}\left(T_0\right)}{R_1\left(T_0\right)R_{2,5}\left(T_0\right)}\frac{K}{q}\ln \left(\frac{K_{\mathrm{MN}2}}{K_{\mathrm{MN}1}}\right)T}+\underset{\underset{}{}}{R_{5,6}\left(T_0\right)\left(1+T+T^2\right)K_{\mathrm{MN}5}{C}_{\mathrm{ox}}\left(n-1\right){}_0{\left(\frac{T}{T_0}\right)}^{-1.5}{\left(\frac{\mathrm{KT}}{q}\right)}^2\exp \left(\frac{V_{\mathrm{GS}5}\left(T_0\right)+K_T\frac{T}{T_0}-V_{\mathrm{TH}}}{n\frac{\mathrm{KT}}{q}}\right)}$
Applying and doing a few recalculations:

(58) $={}_1+{}_2\mathrm{dT}.Math.\frac{d}{dT}={}_2.fwdarw.\mathrm{constant}$$\frac{d\left(T\right)}{dT}=.fwdarw.\mathrm{constant}$$\frac{d}{dT}=\sqrt{T}$

(59) After extracting the temperature dependence of the proposed topology it is perceived that the nonlinear compensation is performed from segment , which includes a second order non-linear compensation multiplied with an exponential compensation. The combination of two complementary high-order non-linear compensations, multiplied across temperature, results in a higher order nonlinear compensation which leads to a superior temperature compensation over a wider temperature range. The resistors ratios are tuning the slope as well as the non-linearities of the reference voltage. By proper sizing of the resistance ratios, the optimum TD of the reference voltage may be achieved.

(60) While operating in sub-threshold region, process variations may affect the performance of the fabricated chips, thus resistor trimming will ensure that the simulated performance will approximately match the measured results. In this invention we propose a new trimming methodology which has essential advantages compared to prior-art. The developed trimming method is very simple and effective with minimum effort and time costs. The impact of resistors R.sub.2 and R.sub.4 to the reference voltage slope and non-linearities, as well as their tunability range, imposes that these resistors are the chosen ones for post-layout fine tuning and post-fabrication trimming. Thus, resistors R.sub.2 and R.sub.4 are designed to be trimmed, each with 3-bits of trimming.

(61) FIG. 3 illustrates a graph 300 of a plurality of deviations of the non-linearities influencing the TD of a reference voltage, in accordance with one embodiment of the present invention.

(62) The graph 300 may include the deviations of the non-linearities on the y-axis 310 versus temperature readings in Celsius on an x-axis 320.

(63) The simplicity and effectiveness of the proposed trimming method is based on the fact that two resistors are able to trim four different cases of the reference voltage deviations. This is clearly demonstrated in FIG. 3 where all the cases of the reference voltage deviations are simulated, discriminated and demonstrated to over temperature.

(64) FIG. 4 illustrates a graph 400 of a plurality of deviations of the slope influencing the TD of the reference voltage, in accordance with one embodiment of the present invention.

(65) The graph 400 may include the deviations of the slope (linear component on the y-axis 410 versus temperature readings in Celsius on an x-axis 420.

(66) In FIG. 3 the deviations of the reference voltage non-linearities are illustrated, while the slope compensation is optimum. Where V.sub.REF (RW) indicates that R.sub.2 and R.sub.3 poly-si resistors non-linearities are dominating the ones of MN.sub.4 and MN.sub.5 transistors, and where V.sub.REF (NW) indicates that MN.sub.4 and MN.sub.5 transistor non-linearities are dominating the ones of R.sub.2 and R.sub.3. In FIG. 4 the deviations of the reference voltage slope are illustrated, whereas the non-linearities compensation is optimum. V.sub.REF (PS) indicates that the current drawn by the MN.sub.5 transistor is dominating the one drawn by R.sub.2 and R.sub.3, while V.sub.REF (NS) indicates that the current drawn by the resistors R.sub.2 and R.sub.3 is dominating the one drawn by MN.sub.5. The reasoning behind this strategy is that R.sub.2 and R.sub.3 are tuning the influence of the resistors on IC slope and non-linearities while R.sub.4 is acting as source degeneration of MN.sub.4, tuning the influence of sub-threshold transistor MN.sub.4 on the IC slope and non-linearities.

(67) TABLE-US-00002 TABLE II STRATEGY FOR POST-LAYOUT TUNING & POST-FABRICATED TRIMMING Case Correction Strategy VREF_NW R.sub.2 & R.sub.4 VREF_RW R.sub.2 & R.sub.4 VREF_NS R.sub.2 & R.sub.4 VREF_PS R.sub.2 & R.sub.4

(68) A clear and detailed strategy of trimming is shown in Table II. With 2.sup.2 combinations of the two resistors, all four possible worst case discriminated scenarios have a simple counter measure for optimizing the performance. Another very important advantage of the proposed trimming method is that the TD performance may be trimmed over the whole temperature range at a single point, which makes it trivial, saving time and costs. Applying a full temperature sweep on the reference circuit, identifying the case of deviation from FIGS. 3 and 4 and following the straightforward indications of Table II is leading to a trivial compensation of any deviation of the reference voltage. The proposed trimming method is not dedicated only for the proposed voltage reference topology, as it may be expanded and utilized in a wide range of voltage references and BGRs circuits that use CMOS devices and resistors for compensating the reference voltage.

(69) FIG. 5 illustrates a graph 500 of simulated TD of a voltage reference output, in accordance with one embodiment of the present invention.

(70) The graph 500 may include the output reference voltage on the y-axis 510 versus temperature readings in Celsius on an x-axis 520.

(71) The reference voltage of the topology of FIG. 2 was simulated utilizing CMOS 0.18 m technology. The results across temperature corners are presented in FIG. 5 where the TD is 2.4 ppm/ C. with a bias of 0.7V. The simulated results show an improved non-linear compensation over a wider temperature range. The proposed voltage reference of FIG. 2 was fabricated at Tower Jazz foundry, in CMOS 0.18 m semi-conductors technology with the devices sized as shown in Table I. Nine fabricated chips from two different wafers were extensively measured and characterized. The measurements were performed with a Keithley 4200 Semiconductor Characterization System and an Espec SU-261 Temperature Chamber.

(72) TABLE-US-00003 TABLE III MEASURED TD OF 9 SAMPLES WITH BIAS VOLTAGE OF 0.7 V FOR A TEMPERATURE RANGE OF 185 C. (60 C. TO 125 C.) Sample TD ppm/ C. 1 11 2 14.5 3 15.7 4 12.8 5 17.2 6 9.9 7 19.4 8 10.7 9 9.3

(73) The measured post-trimmed TD of the nice chips with a supply voltage of 0.7V is presented in Table III where the TD is between 9.3 ppm/ C. and 19.4 ppm/ C. The topology may operate reliable for a wide range of bias voltages that are between 0.6V-1.8V.

(74) FIG. 6 illustrates a graph 600 of measured TD of a voltage reference output biased at 0.7V, in accordance with one embodiment of the present invention.

(75) The graph 600 may include measured output reference voltage on the y-axis 610 versus temperature readings in Celsius on an x-axis 620.

(76) The TD was measured utilizing the box-method and is presented in FIG. 6, where the proposed voltage reference achieves a TD of 9.3 ppm/ C. over a wide temperature range of 185 C. (60 C. to 125 C.) with a bias voltage of 0.7V. The proposed trimming method allows for even better TD performance than 9.3 ppm/ C., in the expense of narrowing the temperature range if that is necessary by the application.

(77) FIG. 7 illustrates a graph 700 of a measured and simulated PSRR of the proposed topology with different biased voltages at 27 C., in accordance with one embodiment of the present invention.

(78) The graph 700 may include the PSRR in decibels on a y-axis 710 and the Frequency in Hertz on the x-axis 720.

(79) The measured and simulated power supply rejection ratio or PSRR at 27 C. is presented in FIG. 7 and it's around 28 dB for bias voltage of 0.7V and it increases for higher supply voltages. Although PSRR is inferior compared to some of the prior-art designs, it may be significantly improved at the system level by stacking a relatively big transistor at top of all the sub-threshold topologies. This will substantially improve the PSRR with a minor increase of the supply voltage.

(80) FIG. 8 illustrates a graph 800 of a measured noise spectrum of the proposed topology biased at 0.7V for 60 C., 27 C. and 125 C., in accordance with one embodiment of the present invention.

(81) The graph 800 may include a noise reading 810 on a y-axis and the Frequency in Hertz on the x-axis 820.

(82) The measured noise spectrum at room temperature as well as in the extreme temperature corners without filtering capacitors is presented in FIG. 8. The total root mean square voltage noise measured at the output between 0.1 Hz and 50 Hz is 59 V without any external capacitors. Thus the total noise is well below the TD performance of the reference voltage. Although not necessary, the addition of a load capacitor at the output would further improve the noise value. The power consumption at room temperature with a bias of 0.7V is 2.7 W and the minimum supply voltage for the topology is 0.6V. The topology does not face any start-up problems under any bias conditions while utilizing slow and fast ramps at the supply during simulations as well as during measurements.

(83) A breakthrough, ultra-low power, low voltage, all-CMOS voltage reference topology is presented. The proposed circuit is simple to design and demonstrates the feasibility of designing circuits in sub-threshold for power aware applications while maintaining a competitive performance for a wide temperature range. The accuracy of TD is maintained even in the very low temperature of 60 C. where no other prior art designs are performing up to date. The eliciting factor of limiting the TD performance of prior-art voltage references (non-linearities) was eliminated with a straightforward and effective way. The fully CMOS design without any external capacitors increase the integration and minimizes the cost and size of the IC. The novel and effective trimming method that was proposed may compensate the reference voltage slope and non-linearities variations due to operating in sub-threshold region. The proposed voltage reference is suitable for low power, low area and high accuracy biomedical applications, mobile devices, energy harvesting systems and space applications that may operate reliably in extreme temperatures.

(84) FIG. 9 illustrates an electrical schematic of a voltage reference 900, in accordance with one embodiment of the present invention.

(85) The voltage reference 900 may include a CTAT feedback loop 910, a PTAT feedback loop 920, a PTAT current bias circuit 930 and an output summing-compensating circuit 940.

(86) The proposed design is illustrated in FIG. 9, where FIG. 9(a) shows the core reference module, FIG. 9(b) shows the start-up circuit (MP.sub.su1, MPs.sub.u2 and C.sub.1) and PTAT generator and FIG. 9(c) shows the reference output stage. The low V.sub.TH (threshold voltage) N channel and P-channel transistors, utilized in the design, typically have a threshold voltage of 0.41V and 0.45V respectively.

(87) The design relies on the fact that the high-resistivity poly-silicon resistors (rpolyh), the low-temperature coefficient poly-silicon resistors (rpolyz), and the CMOS sub-threshold N-type device have unique, but complimentary non-linear responses to changes in temperature. These are graphically illustrated in FIG. 10, where the current is plotted as a function of temperature, for a given bias voltage, corresponding to the nominal bias point in the circuit.

(88) By carefully selecting the ratio of the above currents, in conjunction with the output stage resistors, one may get a temperature insensitive voltage at the reference output. More specifically, from FIG. 9, the gate-source voltage of MN.sub.4 decreases with temperature, thus decreasing the voltage drop across R.sub.2 and R.sub.3. This creates a CTAT current across MP.sub.5 that is mirrored to MP.sub.9. In a similar way, the gate-source voltage of MN.sub.6 decreases with temperature, thus decreasing the gate-source voltage of MN.sub.7. Although, V.sub.TH of MN.sub.7 is decreasing as well with temperature, thus the current flowing across the device is increased. Through MP.sub.8 this PTAT current is mirrored to MP.sub.10. A CTAT and a PTAT currents through MP.sub.9 and MP.sub.10 respectively are summed through R.sub.7 and R.sub.8, giving a curvature corrected reference voltage with high-order non-linear compensation. Capacitors C.sub.2 and C.sub.3 are utilized to compensate the phase margin of the two loops so as to ensure the circuit's stability.

(89) The output of the circuit design in FIG. 9 may be expressed as:

(90) $V_{\mathrm{REF}}=\left(I_{\mathrm{CTAT}}+I_{\mathrm{PTAT}}\right)\left(R_7+R_8\right)$$V_{\mathrm{REF}}=\left(\frac{V_{\mathrm{GS\_MN}4}+V_{R4}+V_{R5}}{R_2+R_3}+\frac{V_{\mathrm{GS\_MN}6}+V_{R6}}{r_{o7}+1/G_{m7}}\right)\left(R_7+R_8\right)$

(91) Despite the fact that all MOS devices are operated in the sub-threshold regime, mismatch may be maintained under control by increasing device area and by utilizing standard matching techniques. However, process variations, do effect performance of the fabricated chips, thus resistors R.sub.6 and R.sub.7 are designed to be trimmed so as to compensate process variations of the reference voltage. After extensive Monte Carlo process and mismatch simulations, the values of the trimmable resistors were chosen such that a fast binary search algorithm may be utilized during post fabrication trimming.

(92) FIG. 10 illustrates a graph 1000 of a high resistivity poly-silicon resistor, low temperature coefficient poly-silicon resistor and NMOS sub-threshold transistor, current versus temperature, for a given bias voltage, in accordance with one embodiment of the present invention.

(93) The graph 1000 may include a current reading 1010 on a y-axis versus temperature readings in Celsius on an x-axis 1020.

(94) TABLE-US-00004 TABLE IV Devices Dimensions of the Circuit Topology Component Parameter MP.sub.su1 W = 5 m, L = 10 m MP.sub.su2 W = 4 m, L = 12 m MP.sub.1, MP.sub.2, MP.sub.3, MP.sub.6 W = 25 m, L = 5 m MP.sub.4, MP.sub.5, MP.sub.7, MP.sub.8 W = 80 m, L = 5 m MP.sub.9, MP.sub.10 W = 45 m, L = 5 m MN.sub.1 W = 35 m, L = 5 m MN.sub.2 W = 105 m, L = 5 m MN.sub.3, MN.sub.5 W = 20 m, L = 20 m MN.sub.4, MN.sub.6 W = 200 m, L = 5 m MN.sub.7 W = 400 m, L = 5 m R.sub.1 (rpolyh), R.sub.8 (rpolyh) 300 K R.sub.2 (rpolyz), R.sub.3 (rpolyh) 345 K R.sub.4 (rpolyz), R.sub.5 (rpolyh) 150 K R.sub.6 (rpolyh) 190 K R.sub.7 (rpolyz) 243 K C.sub.1 2 pF C.sub.2 20 pF C.sub.3 5 pF

(95) The proposed design of FIG. 9 was implemented in 0.35 m, 3.3 V standard CMOS process utilizing low VTH transistors. All the elements sizes are shown in Table 5 including the resistors types that were utilized in the circuit.

(96) FIG. 11 illustrates a graph 1100 of a simulated temperature drift of the reference voltage over a temperature range of 190 C. (45 C. to 145 C.), in accordance with one embodiment of the present invention.

(97) The graph 1100 may include an output voltage reading 1110 on a y-axis versus temperature readings in Celsius on an x-axis 1120. FIG. 11 shows the reference voltage with respect to an extended temperature range of 45 C. to 145 C.

(98) FIG. 12 illustrates a graph 1200 of a simulated performance throughout the temperature range (45 C. to 145 C.) and the supply voltage range (0.4 V to 2 V), in accordance with one embodiment of the present invention.

(99) The graph 1200 may include a simulated performance reading 1210 on a y-axis versus a supply voltage reading on an x-axis 1220.

(100) FIG. 12 shows the reference voltage value throughout the temperature range (45 C. to 145 C.) and the supply voltage range (0.4 V to 2 V).

(101) The proposed circuit had demonstrated that it is possible to design an all-CMOS voltage reference circuit in the sub-threshold regime, whilst maintaining a very competitive performance. By utilizing different kinds of polysilicon resistors and a diode-connected, sub-threshold MOSFET device is possible design a circuit that may easily operate with a supply voltage of 0.75V, yielding a temperature coefficient of 2 ppm/ C. and consuming a mere 2 W. The proposed topology is suitable especially for applications that have tight limitations on the power budget but still need high performance of temperature drift, such as high accuracy biomedical implants, wearable medical devices and energy harvesting systems. Simulations and Monte-Carlo analysis show that this is an extremely promising design.

(102) While the present invention has been related in terms of the foregoing embodiments, those skilled in the art will recognize that the present invention is not limited to the embodiments described. The present invention may be practiced with modification and alteration within the spirit and scope of the appended claims. Thus, the description is to be regarded as illustrative instead of restrictive on the present invention.