Event input module

Abstract

Disclosed is an event input module, wherein the event input module receives time information which is an IRIG-B signal of a predetermined method from an outside time provider, allocates the time information to a detected event and determines event generation information.

Claims

1. An event input module of a PLC (Programmable Logic Controller), the module comprising: a first receiver configured to receive a signal from an external sensor unit, the first receiver including a first resistor configured to limit an input current and a second resistor configured to maintain an OFF guarantee voltage; a second receiver configured to receive time information from an external time provider, the time Information is an IRIG (Inter-Range Instrumentation Group)-B signal of the RS-485 type; a controller configured to determine event generation information by allocating the received time information to an event detected via a signal received from the first receiver; and a memory configured to store the determined event generation information.

2. The event input module of claim 1, wherein the controller is further configured to receive the IRIG-B signal via a timer port (TMR).

3. The event input module of claim 2, wherein the controller is further configured to interpret information related to a signal transmitted from the first receiver by detecting a pulse width of the received IRIG-B signal.

4. The event input module of claim 1, further comprising an interface unit configured to exchange a signal received from the controller with a Central Processing Unit (CPU) module of a PLC.

5. The event input module of claim 4, wherein the interface unit includes a memory accessible by the CPU module and the controller.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram illustrating synchronization of PLC systems according to prior art.

(2) FIG. 2 is a block diagram modeling a time delay of FIG. 1.

(3) FIG. 3 is an exemplary view illustrating configuration of an event input module according to an exemplary embodiment of the present disclosure.

(4) FIG. 4 is an exemplary view illustrating a time synchronization between two PLCs.

(5) FIG. 5 is an exemplary view modeling a time delay of FIG. 4.

DETAILED DESCRIPTION OF THE DISCLOSURE

(6) Various exemplary embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which some exemplary embodiments are shown. The present inventive concept may, however, be embodied in many different forms and should not be construed as limited to the example embodiments set forth herein. Rather, the described aspect is intended to embrace all such alterations, modifications, and variations that fall within the scope and novel idea of the present disclosure.

(7) Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

(8) FIG. 3 is an exemplary view illustrating configuration of an event input module (40) according to an exemplary embodiment of the present disclosure, where the event input module (40) may receive a signal inputted from an outside sensor unit (30) and transmit the signal to a CPU module (50).

(9) Referring to FIG. 3, the event input module (40) may include an event receiver (41), an IRIG (Inter-Range Instrumentation Group)-B signal receiver (42), a memory (43), a controller (44) and an interface unit (45).

(10) The event receiver (41), which detects an event by receiving a signal outputted from the outside sensor unit (30), may include a resistor (R1) configured to limit an input current, a retaining resistor configured to retain an OFF guarantee voltage (R2) and a photo-coupler (41A). The event receiver (41) operates by receiving a 24V-voltage signal from the outside sensor unit (30). The outside sensor unit (30) is an NPN or PNP sensor configured to sense generation of event, the detailed structure of which will be omitted as it is well known to the skilled in the art.

(11) The IRIG-B signal receiver (42) receives an IRIG-B signal from a time provider (20) in an RS-485 method, where the RS-485 method is selected because a time transmission is characteristically enabled from one time synchronization facility to a plurality of event input modules. An IRIG-B time synchronization protocol is one of IRIG standards, and one of the most widely used time synchronization methods as well. Thus, IRIG-B time synchronization protocol is well known to the skilled in the art and detailed explanation thereto will be omitted herefrom. The time provider (20) may be a GPS receiver, for example.

(12) The memory (43) stored an event generation time, and the memory (43) may be configured with a non-volatile memory so that an already-generated event time can be maintained, even if a power is turned off.

(13) The controller (44) takes charge of controlling the event input module (40) and receives, at a time port (TMR), a signal from the IRIG-B signal receiver (42). The IRIG-B signal generates 100 pulses at each second, and transmits in the order of second information, minute information, time information, day information and year information. At this time, one pulse has a 10 ms period, and the controller (44) can determine a duration in which period of each signal and high state are maintained, by receiving the signal at the time port of the controller (44).

(14) The interface unit (45) takes charge of interface between the event input module (40) and CPU module (50), and allows data to be exchanged between the two systems using a predetermined method.

(15) Now, operation of the event input module (40) according to the present disclosure will be described.

(16) A 24V voltage signal received from outside sensor unit (30) may form a loop current by flowing through a current limit resistor (R1) of an even receiver (41). The OFF retaining resistor (R2) of the event receiver (41) prevents the photo-coupler (41A) from operating when a voltage that fails to reach a level for OFF guarantee at the outside sensor unit (30). To with, the R2 can maintain the OFF guarantee voltage.

(17) Subsequently, an input signal is transmitted to an input port of the controller (44), whereby the controller (44) can detect generation of an event. Meanwhile, the time information inputted from the outside time provider (20) in an IRIG-B format is transmitted to the controller (44) through the IRIG-B signal receiver (42).

(18) At this time, the time information can be received through the time port (TMR) of the controller (44) to interpret the transmitted information by detecting a pulse width of the IRIG-B signal. The information is received on a second unit, and then, the event input module (40) prepares to provide time information at all time so that even a millisecond value can be determined by using a timer setting of the controller (44).

(19) In addition, the moment an event generated by the outside sensor unit (30) is transmitted to the controller (44) through the event receiver (41), the controller (44) allocates the prepared time information to a relevant event, where the event data is transmitted to the memory (43), where the event data can be kept as event generation information.

(20) The interface unit (45) exchanges data with the CPU module (50). For example, the interface unit (45) may be configured with a circuit such as an ASIC (Application Specific Integrated Circuit) including a CPU module (50) and a memory accessible by the controller (44).

(21) FIG. 4 is an exemplary view illustrating time synchronization between two PLCs, the principle of which is applied to the system of FIG. 1 according to prior art, and FIG. 5 is an exemplary view modeling a time delay of FIG. 4.

(22) It can be noted from FIG. 4 that communication modules are removed from each PLC system over FIG. 1 according to the present disclosure whereby the system configuration is simplified.

(23) Furthermore, it can be intuitively compared that the time delay elements from t2 to t6 are removed to thereby enable accurate time synchronization as illustrated in FIG. 5.

(24) That is, the time delay elements at PLCs (1, 2) of FIG. 3 may be respectively expressed by the following Equations 3 and 4.
t=t1+t7+t8[Equation 3]
t=t1+t7+t8[Equation 4]

(25) In fact, the t1(t1) and t8(t8) which are time delay elements generated on a signal transmission path are at negligible levels, such that important time delay elements between two systems may be summarized as t7 and t7.

(26) Furthermore, because the two event input modules (40, 60) are systems using same hardware and firmware, it can be said that an error of time required for time interpretation can be also negligible levels.

(27) It can be also noticed from FIG. 5 that time delay elements between the event input modules (40, 60) and the CPU modules (50, 70) are not shown, which means that time required for synchronization has been already determined by the event input modules (40, 60), and well indicates how the time delay elements at the CPU modules according to the conventional system prior art affect the present disclosure, whereby the present disclosure can provide an advanced time synchronization to the power system including power generation, power transmission and power distribution, and to the automatic systems applicable to process plants.

(28) As apparent from the foregoing, the present disclosure provides an event input module configured to implement an IRIG-B interface to solve time delay elements in the conventional PLC systems, through which a method enabling an accurate time synchronization can be provided. Furthermore, a system configuration for time synchronization between mutually different PLC systems can be simplified, whereby advantages can be obtained in terms of costs and spaces.

(29) Most of the time delay elements are generated in the course of data processing rather than from the transmission path, and the present disclosure can fundamentally solve the delay elements that may be influenced by PLC user program, by removing the time delay elements at the CPU modules that take the lion's share of the time delay elements.

(30) Although the event input module according to the present disclosure has been described with reference to a number of limited illustrative embodiments thereof, it should be understood that numerous other modifications and embodiments can be devised by those skilled in the art that will fall within the spirit and scope of the principles of this disclosure. Therefore, it should be understood that the above-described embodiments are not limited by any of the details of the foregoing description and drawings, unless otherwise specified, but rather should be construed broadly within the scope as defined in the appended claims