Dead time circuit for a switching circuit and a switching amplifier

Abstract

A dead time circuit (750) for a switching circuit is disclosed. The dead-time circuit comprises: an input (752) for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs (754a, 754b); a first feedforward path (756) coupled to the first output and arranged to receive the switching signal; a second feedforward path (758) coupled to the second output and arranged to receive the switching signal; a first feedback path (760) forming a first feedback loop between the first output and the second feedforward path; and a second feedback path (762) forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit (764a, 764b), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed.

Claims

1. A dead time circuit for a switching circuit, the dead-time circuit comprising: (i) an input for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; (ii) first and second outputs; (iii) a first feedforward path coupled to the first output and arranged to receive the switching signal; (iv) a second feedforward path coupled to the second output and arranged to receive the switching signal; (v) a first feedback path forming a first feedback loop between the first output and the second feedforward path; and (vi) a second feedback path forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit, each having a time delay greater than a time period of the ground bounce signal determined according to the equation: t=2(LC)^0.5, where t is the time period of the ground bounce signal, L is the inductance of a bonding wire and C is the capacitance of the at least one supply rail.

2. The dead time circuit according to claim 1, wherein the first feedforward path includes a first logic gate for receiving the switching signal and an output signal from the second output via the second feedback path.

3. The dead time circuit according to claim 2, wherein the second feedback path includes a second logic gate.

4. The dead time circuit according to claim 3, wherein the second logic gate includes an inverter.

5. The dead time circuit according to claim 2, wherein the first logic gate's output is coupled to an input of the first delay circuit, and the first delay circuit's output is coupled to a first driver for boosting a first delayed signal from the first delay circuit.

6. The dead time circuit according to claim 1, wherein the second feedforward path includes a third logic gate for receiving the switching signal and an output signal from the first output via the first feedback path.

7. The dead time circuit according to claim 6, wherein the first feedback path includes a fourth logic gate.

8. The dead time circuit according to claim 7, wherein the fourth logic gate includes an inverter or a Level Shifter.

9. The dead time circuit according to claim 6, wherein the third logic gate's output is coupled to an input of the second delay circuit, and the second delay circuit's output is coupled to a second driver for boosting a second delayed signal from the second delay circuit.

10. The dead time circuit according to claim 1, wherein the second feedforward path includes third and fourth logic gates, the third logic gate for receiving the switching signal, the fourth logic gate for receiving the third logic gate's output and an output signal from the first output via the first feedback path.

11. The dead time circuit according to claim 10, wherein the third and fourth logic gates respectively include an inverter and an AND gate.

12. The dead time circuit according to claim 1, wherein the first feedforward path includes first and second logic gates, the first logic gate for receiving the switching signal, the second logic gate for receiving the first logic gate's output and an output signal from the second output via the second feedback path.

13. The dead time circuit according to claim 12, wherein the first and second logic gates respectively include an inverter and a NOR gate.

14. A switching circuit for generating a switching signal, the switching circuit comprising: a loop filter for producing a filtered signal from an input signal; a modulator for modulating the filtered signal to produce a modulated switching signal; and an output stage including the dead time circuit according to claim 1, wherein the modulated switching signal is delayed by the first and second delay circuits to generate the switching signal for driving a load.

15. The switching circuit according to claim 14, wherein the modulator includes a pulse width modulator, bang-bang control modulator, Sigma-Delta modulator or self-oscillation modulator.

16. The switching circuit according to claim 14 in the form of an amplifier or a DC-DC converter.

17. A switching amplifier comprising: an inner feedback loop; and an outer feedback loop having a loop gain and comprises a first integrator with at least one zero and a second integrator; wherein the inner feedback loop includes a closed-loop gain comprising the second integrator of the outer feedback loop, the closed-loop gain of the inner feedback loop having at least one pole; the first integrator having a reactive element configured to generate a zero to at least partially cancel the at least one pole of the closed-loop gain of the inner feedback loop.

18. The switching amplifier according to claim 17, wherein the first integrator has three poles and a further zero, and the closed-loop gain of the inner feedback loop has one zero and a further pole.

19. The switching amplifier according to claim 18, wherein the further zero of the first integrator at least partially cancels the further pole of the closed-loop gain of the inner feedback loop.

20. The switching amplifier according to claim 17, wherein the reactive element emulates an inductor.

21. The switching amplifier according to claim 20, wherein the inductor includes a transconductance circuit.

22. The switching amplifier according to claim 17, further comprising a modulator wherein the second integrator's input is electrically coupled to an output of the first integrator and to an amplifier output for producing an amplified signal, and the second integrator's output is electrically coupled to an input to the modulator, and wherein the first integrator's input is electrically coupled to the amplifier output.

23. The switching amplifier according to claim 22, wherein the first integrator's input is also electrically coupled to an amplifier input for receiving a signal to be amplified.

24. The switching amplifier according to claim 22, further comprising a third feedback loop having a third integrator, the third integrator's input is electrically coupled to an amplifier input for receiving a signal to be amplified, and to the amplifier output.

25. A switching amplifier comprising: an inner feedback loop; an outer feedback loop having a loop gain and comprises a first integrator with at least one zero and a second integrator; wherein the inner feedback loop includes a closed-loop gain comprising the second integrator of the outer feedback loop, the closed-loop gain of the inner feedback loop having at least one pole; the first integrator having a reactive element configured to generate a zero to at least partially cancel the at least one pole of the closed-loop gain of the inner feedback loop; and an output stage having a dead time circuit wherein the dead time circuit comprises: (i) an input for receiving a switching signal of a switching circuit with at least one supply rail having a ground bounce signal; (ii) first and second outputs; (iii) a first feedforward path coupled to the first output and arranged to receive the switching signal; (iv) a second feedforward path coupled to the second output and arranged to receive the switching signal; (v) a first feedback path forming a first feedback loop between the first output and the second feedforward path; and (vi) a second feedback path forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit, each having a time delay greater than a time period of the ground bounce signal determined according to the equation: t=2(LC)^0.5, where t is the time period of the ground bounce signal, L is the inductance of a bonding wire and C is the capacitance of the at least one supply rail.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention are disclosed hereinafter with reference to the accompanying drawings, in which:

(2) FIG. 1 is a block diagram of a Class D amplifier (CDA), according to the prior art;

(3) FIG. 2 includes FIGS. 2a and 2b, which respectively shows output waveforms generated by the CDA under an ideal and a practical scenario;

(4) FIG. 3 is a schematic diagram of a PWM CDA, according to the prior art;

(5) FIG. 4 includes FIGS. 4a and 4b, which respectively shows ground-bounce coupling paths at an integrator and a carrier generator of the CDA of FIG. 1;

(6) FIG. 5 depicts occurrence of false switching in a PWM signal;

(7) FIG. 6 is a schematic diagram of a conventional double-feedback PWM CDA;

(8) FIG. 7 includes FIGS. 7a and 7b, which respectively shows a conventional dead-time circuit and a dead-time circuit (based on a first embodiment) configured to be used in an upper branch of a CDA bridge-tied load (BTL) output stage;

(9) FIG. 8a shows a second dead-time circuit, based on a second embodiment;

(10) FIG. 8b shows a third dead-time circuit, based on a third embodiment;

(11) FIG. 8c shows a fourth dead-time circuit, based on a fourth embodiment;

(12) FIG. 9 includes FIGS. 9a and 9b, which are respective schematic diagrams of a proposed double-feedback PWM CDA and an inductor configuration used in the proposed double-feedback PWM CDA, based on a fifth embodiment;

(13) FIG. 10 is a block diagram of the double-feedback PWM CDA of FIG. 9a, in which an inner feedback loop is realized within a shaded area shown in FIG. 9a;

(14) FIG. 11 is a simplified block diagram of FIG. 10;

(15) FIG. 12 is a block diagram of a proposed triple-feedback PWM CDA, based on a sixth embodiment;

(16) FIG. 13 is a comparison graph of loop-gains of the conventional double feedback PWM CDA of FIG. 6, the double feedback PWM CDA of FIG. 9a, and the proposed triple feedback PWM CDA of FIG. 12; and

(17) FIG. 14 is a block diagram of another double-feedback PWM CDA, based on a seventh embodiment.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

1. A Ground-Bounce-Insensitive Dead Time Circuit

(18) FIG. 7a shows a conventional dead-time circuit 700, while FIG. 7b shows a proposed dead-time circuit 750 configured to be incorporated in an upper branch of a BTL output stage of a switching circuit (e.g. a Class D amplifier (CDA), but not limited to as such), according to a first embodiment. The proposed dead-time circuit 750 is hereinafter referred to as the first dead-time circuit 750. As a background, dead-time circuits are commonly employed to prevent simultaneous switching-on both the high-side and low-side power transistors of output stages. Specifically in this instance, the first dead-time circuit 750 is arranged to be ground-bounce-insensitive, and is thus able to significantly reduce false switching in the said output stage due to ground-bounce occurrences, and beneficially, with minimal hardware overheads incurred.

(19) Particularly, the first dead time circuit 750 comprises an input 752 for receiving a switching signal of the switching circuit with at least one supply rail (not shown) having a ground bounce signal; first and second outputs 754a, 754b (which are in turn respectively coupled to first and second power transistors 755a, 755b labelled as M.sub.p1, M.sub.n1); a first feedforward path 756 coupled to the first output 754a and arranged to receive the switching signal; a second feedforward path 758 coupled to the second output 754b and arranged to receive the switching signal; a first feedback path 760 forming a first feedback loop between the first output 754a and the second feedforward path 758; and a second feedback path 762 forming a second feedback loop between the second output 754b and the first feedforward path 756. The first and second outputs 754a, 754b are respectively labelled as V.sub.P1 and V.sub.n1 in FIG. 7b. The switching signal is labelled as V.sub.PWM-P (in FIGS. 7a and 7b) and is ground-bounce induced. Each of the first and second feedforward paths 756, 758 is arranged to include a respective first and second delay circuit 764a, 764b (i.e. labelled as Delay_GB_P and Delay_GB_N), each having a time delay greater than a predetermined time period of the ground bounce signal. Further, each of the first and second feedforward paths 756, 758 also includes a respective first and second NOR gate 766a, 766b (i.e. labelled as NOR_P and NOR_N), as well as a respective first and second driver circuit 768a, 768b (i.e. labelled as Driver_P and Driver_N). A first inverter 770a is arranged between the input 752 and the first NOR gate 766a, whereas a second inverter 770b is arranged in the first feedback path 760.

(20) It is to be appreciated that the output of the first NOR gate 766a is coupled to an input of the first delay circuit 764a, and the output of the first delay circuit 764a is coupled to the first driver 768a for boosting a first delayed signal from the first delay circuit 768a. Similarly, the output of the second NOR gate 766b is coupled to an input of the second delay circuit 764b, and the output of the second delay circuit 764b is coupled to the second driver 768b for boosting a second delayed signal from the second delay circuit 768b.

(21) The configuration of the first dead time circuit 750 differs from the conventional dead time circuit 700 in that (for the first dead time circuit 750) the first and second delay circuits 784e. 764b are positioned respectively in the first and second feedforward paths 756, 758, whereas for the conventional dead time circuit 700, the corresponding delay circuits are instead positioned respectively within the associated feedback paths. That is, placement of the remaining components of the first dead time circuit 750 is largely the same as in the conventional dead time circuit 700, except for the above explained. For good order, it is to be highlighted that like components in the conventional dead-time circuit 700 to those in the first dead-time circuit 750 are described below using the same reference numerals, but with additional inclusion of to the said reference numerals.

(22) Furthermore, for the first dead time circuit 750, the delay of the first and second delay circuits 764a, 764b is purposefully configured to be longer than t.sub.GB (i.e. a period of the ground-bounce). More specifically, it is to be appreciated that a delay of the first and second delay circuits 764a, 764b to be configured is design-dependent in that the delay may depend on supply voltage, switching frequency of the CDA, parasitic capacitance/inductance/resistance, inductance of the bonding wire, and etc. In this embodiment, the delay is configured to be about 2 ns. However, in the conventional dead time circuit 700, the delay of the associated delay circuits 764a, 764b (i.e. labelled as Delay_P and Delay_N in FIG. 7a to differentiate from Delay_GB_P and Delay_GB_N) is configured to be shorter than 1/f.sub.GB (i.e. f.sub.GB is a frequency of the ground-bounce). It is also to be appreciated that the value of t.sub.GB is determined by the inductance of any bonding wires, decoupling capacitors used and/or parasitic capacitance of the switching circuit (e.g. an amplifier) itself. A value of t.sub.GB may be obtained via simulations/experiments, but a general estimate of t.sub.GB may be obtained from equation (1):
t.sub.GB=2p(LC)^0.5(1)
wherein L is the inductance of a bonding wire and C is the total capacitance between supply rails (including a decoupling capacitor and parasitic capacitance).

(23) To understand why the conventional dead-time circuit 700 suffers from false switching, an explanation is provided with reference to FIG. 7a. For the conventional dead-time circuit 700, the delay of the first and second delay circuits 764a, 764b therein are shorter than t.sub.GBthis being because the delay needed for dead time is shorter than 1/f.sub.GB. Further, as mentioned, the first and second delay circuits 764a, 764b (of the conventional dead-time circuit 700) are respectively positioned in the first and second feedback paths 760, 762 (i.e. see FIG. 7a). As a result, the conventional dead-time circuit 700 does not prevent the false switching signal V.sub.PWM-P (due to ground-bounce) from propagating to the gate (i.e. generating a voltage, V.sub.n1) of an output transistor (of the second output 754b). For example, consider a case when V.sub.p1 and V.sub.n1 are both high, and false switching occurs in the switching signal V.sub.PWM-P. V.sub.p1 does not switch because one of the inputs to the first NOR gate 766a, V.sub.fdn1, is held high. So any high-frequency (and hence short pulses) switching is likely to be blocked by the first delay circuit 764a (i.e. Delay_P). However as the first delay circuit 764a is embedded in the second feedback path 762, short pulses at the input 752 may propagate to V.sub.n1, and hence cause the output transistor (of the second output 754b) to (false) switch. This false switching in turn induces more ground-bounce, thereby exacerbating the problem (by potentially then creating further more false pulses).

(24) The proposed (ground-bounce-insensitive) first dead time circuit 750 of FIG. 7b is however able to mitigate the above problem. Advantageously, in the first dead time circuit 750, the ground-bounce-induced short pulses at V.sub.PWM-P are blocked by the second delay circuit 764b (i.e. Delay_GB_N), and thus unable to further propagate to the gate of the second output 754b (i.e. M.sub.n1), thereby eliminating any false switching. Consequently, this improves the reliability and/or linearity characteristics of the switching circuit, in which the first dead time circuit 750 is incorporated. It is to be appreciated that an overall delay of the first dead time circuit 750 is longer than the conventional dead-time circuit 700, due to the longer delay (as configured) and the placement of the first and second delay circuits 764a, 764b. But the longer delay is largely inconsequential because the associated effects on linearity are determined to be negligible.

(25) To reiterate, the first dead time circuit 750 is applicable in the switching circuit (for generating a switching signal), in which the switching circuit comprises a loop filter for producing a filtered signal from an input signal; a modulator for modulating the filtered signal to produce a modulated switching signal; and an output stage (which incorporates the said dead time circuit 750), wherein the modulated switching signal is delayed by the first and second delay circuits 764a, 764b to generate the switching signal for driving a load. The modulator may be a pulse width modulator, bang-bang control modulator, Sigma-Delta modulator, self-oscillation modulator or the like.

(26) For example, the switching circuit may be audio CDAs, the high speed Class D supply modulators for RF polar amplifiers, DC-DC Converters or other suitable circuits, in which switching (with large current flow) is to be performed. Conventionally, RF polar amplifiers are used for high power RF amplifiers for base stations, but not in mobile devices. This is because the large ground-bounce issue prevents RF polar amplifiers from being used in mobile devices, and so the first dead time circuit 750 can now be seen as an enabler for usage of RF polar amplifiers in mobile devices.

(27) The remaining configurations will be described hereinafter. For the sake of brevity, description of like elements, functionalities and operations that are common between the different configurations are not repeated; reference will instead be made to similar parts of the relevant configuration(s).

(28) FIG. 8a shows a second dead-time circuit 800, based on a second embodiment. The second dead-time circuit 800 is largely similar in configuration to the first dead-time circuit 750, except for the following differences. The first and second NOR gates 766a, 766b are now respectively replaced by first and second AND gates 802a, 802b (i.e. both labelled as AND in FIG. 8a). Additionally, the first inverter 770a is now arranged to be positioned between the input 752 and second AND gate 802b (in the second feedforward path 758), whilst the second inverter 770b is now instead arranged in the second feedback path 762.

(29) FIG. 8b shows a third dead-time circuit 840, based on a third embodiment. In particular, the third dead-time circuit 840 is a variant of the second dead-time circuit 800. In this case, the first and second power transistors 755a, 755b M.sub.p1, M.sub.n1 are replaced by an n-channel totem-pole configuration output stage 842 (wherein output transistors used therein are of n-type transistors only). A first Level Shifter 844a is also arranged in the first feedforward path 756, positioned between the first delay circuit 764a and first driver circuit 768a. Further, a second Level Shifter 844b is now arranged in the first feedback path 760.

(30) FIG. 8c shows a fourth dead-time circuit 870, based on a fourth embodiment. The fourth dead-time circuit 870 is a variation of the third dead-time circuit 840, and the differences are explained below. The first and second AND gates 802a, 802b are replaced by the first and second NOR gates 766a, 766b, thus in this respect reverting to the similar configuration in the first dead-time circuit 750. Moreover, the second inverter 770b is omitted from the second feedback path 762, while the first inverter 770a is now re-arranged to between the input 752 and the first NOR gate 766a.

2. High-Gain Loop Filter Designs

(31) FIGS. 9a and 9b are respective schematic diagrams of a proposed double-feedback PWM CDA 900, and an active inductor 950 utilised in the proposed double-feedback PWM CDA 900, based on a fifth embodiment. It is to be appreciated that the double-feedback PWM CDA 900 differs from the conventional double-feedback PWM CDA 600 of FIG. 6 in that respective active inductors 950 are serially coupled to respective resistors labelled as R.sub.23 and then connected to a common ground, but otherwise largely similar in the remaining circuit configuration. The double-feedback PWM CDA 900 includes a loop filter, which comprises an inner feedback loop 902 and an outer feedback loop 904 having a loop gain. The outer feedback loop 904 acts as a first integrator 904 with at least one zero and also includes a second integrator 906, wherein the inner feedback loop 902 includes a closed-loop gain comprising the second integrator 906 of the outer feedback loop 904, the closed-loop gain of the inner feedback loop 902 having at least one pole. That is, the inner feedback loop 902 and outer feedback loop 904 in configuration include the second integrator 906see FIG. 10. Also, the terms outer feedback loop 904 and first integrator 904 will be used interchangeably hereinafter, wherever appropriate. Further, the first integrator 904 has at least one reactive element configured to generate a zero to at least partially cancel the at least one pole of the closed-loop gain of the inner feedback loop 902. In this instance, the active inductor 950 is an example of the reactive element.

(32) The double-feedback PWM CDA 900 further includes a modulator, in which an input of the second integrator 906 is electrically coupled to the output of the first integrator 904 and to the output of the double-feedback PWM CDA 900 for producing an amplified signal. Also, an output of the second integrator 906 is electrically coupled to an input to the modulator, and an input of the first integrator 904 is electrically coupled to the output of the double-feedback PWM CDA 900. Moreover, the input of the first integrator 904 is also electrically coupled to an input of the double-feedback PWM CDA 900 for receiving a signal to be amplified.

(33) Specifically, the first integrator 904 is arranged to have three poles and a further zero, and the closed-loop gain of the inner feedback loop 902 has one zero and a further pole. The further zero of the first integrator 904 at least partially cancels the further pole of the closed-loop gain of the inner feedback loop 902. So the reactive element functions to generate an additional pole and one additional zero, and thus eventually, the proposed double-feedback PWM CDA 900 is provided with five poles and three zeros (as opposed to only four poles and two zeros for the conventional double-feedback PWM CDA 600 of FIG. 6).

(34) The proposed double-feedback PWM CDA 900 is configured so that an overall loop gain of the loop filter is significantly increased, while yet ensuring stability. In the loop filter, active inductor(s) may be employed in the outer feedback loop 904 (as aforementioned). In this case, the active inductor 950 is realized using first and second transconductance amplifiers 952a, 952b (connected in parallel) and a capacitor 954 (i.e. see FIG. 9b). The output of the first transconductance amplifier 952a is coupled to a negative input of the second transconductance amplifier 952b, while the output of the second transconductance amplifier 952b is coupled to a positive input of the first transconductance amplifier 952a. A negative input of the first transconductance amplifier 952a and a positive input of the second transconductance amplifier 952b are coupled to a common ground. One end of the capacitor 954 is then connected in series to the transconductance amplifiers 952a, 952b, while another end of the capacitor 954 is coupled to the same common ground as the transconductance amplifiers 952a, 952b. From the perspective of commercial CDAs, the additional IC area to include the reactive element is considered negligible in the context of the overall IC area required for the PWM CDA 900, and hence the added cost is also negligible.

(35) It is to be appreciated that the two zeros generated by the outer feedback loop 904 are purposefully devised to cancel out the poles in the inner feedback loop 902. Ideally, a residual number of poles and zeros is to be reduced to three poles and one zero, but it is to be appreciated that for the proposed double-feedback PWM CDA 900, there is no necessity for ideal (i.e. perfect) cancellation to be achieved to derive significant improvements for the PWM CDA 900. As a result, the stability requirement may thus be relaxedspecifically, the phase shift of the loop gain of the loop filter (which has a double-feedback loop) is comparable to that of a single-feedback loop. Hence, the overall loop gain of the proposed double-feedback PWM CDA 900 is configurable to be significantly higher (e.g. about 10 dB higher at a frequency of 1 kHz) than the conventional double-feedback PWM CDA 600. Furthermore, the loop filter may also be stably configured to have triple feedback loops (to be further explained below), and hence a significantly improved loop gain (i.e. leading to significantly improved PSRR and other non-linearities) is realizable. Also for both cases, because of the increased loop gain, the PSRR and PS-IMD (and other non-linearities, including THD+N) are improved accordingly.

(36) To delineate the proposed double-feedback PWM CDA 900 and also effect of the reactive element on the overall performance of the loop filter, reference is made to FIG. 10, which is a block diagram representation 1000 of the double-feedback PWM CDA 900. In FIG. 10, a first block 1006 labelled as G.sub.1 is the integrator gain of the inner feedback loop 902, a second block 1008 labelled as G.sub.PWM is the PWM stage gain, and a third block 1010 labelled as G.sub.2 is the integrator gain of the outer feedback loop. Also, a first circular block 1004a arranged on the left of the third block 1010 represents the first integrator 904, while a second circular block 1004b arranged on the right of the third block 1010 then represents the second integrator 906. Accordingly, the overall loop gain of the double-feedback PWM CDA 900 is expressed as:
G.sub.overall=G.sub.1G.sub.2G.sub.PWM+G.sub.1G.sub.PWM(2)

(37) To ensure the stability of the overall design (of the double-feedback PWM CDA 900), it is important that both the inner feedback loop 902 and the outer feedback loop 904 are stable. In this aspect, it is to be appreciated that the inner feedback loop 902 is configured as an 2.sup.nd order integrator and so is stable. As a result, the block diagram representation 1000 of FIG. 10 may be simplified to a more streamlined representation 1100 shown in FIG. 11, where a fourth block 1102 labelled as G.sub.inner represents the closed loop gain of the inner feedback loop 902. Consequently, G.sub.2 and G.sub.inner are respectively expressed as:

(38) $\begin{array}{cc}{G}_2=\frac{1}{R_{22}{R}_{23}{C}^2{s}^2}\left[\frac{2{\mathrm{LCs}}^2+2R_{23}\mathrm{Cs}+1}{\frac{\mathrm{Ls}}{R_{23}}+1}\right]& \left(3\right)\\ G_{\mathrm{inner}}=\frac{R_{12}}{R_{11}}\left[\frac{2R_{13}\mathrm{Cs}+1}{\frac{R_{12}{R}_{13}{C}^2{s}^2}{G_{\mathrm{PWM}}}+2R_{13}\mathrm{Cs}+1}\right]& \left(4\right)\end{array}$

(39) The loop gain, G.sub.outer, of the outer feedback loop 904 is then expressed as:

(40) $\begin{array}{cc}{G}_{\mathrm{outer}}=G_2{G}_{\mathrm{inner}}=\frac{R_{12}}{R_{11}}\frac{1}{R_{22}{R}_{23}{C}^2{s}^2}[\frac{2R_{13}\mathrm{Cs}+1}{\frac{R_{12}{R}_{13}{C}^2}{G_{\mathrm{PWM}}}{s}^2+2R_{13}\mathrm{Cs}+1}][\frac{2{\mathrm{LCs}}^2+2R_{23}\mathrm{Cs}+1}{\frac{L}{R_{23}}s+1}]& \left(5\right)\end{array}$

(41) It is observed from equation (5) that if conditions (A1) and (A2) below are satisfied, then G.sub.outer may be simplified to equation (8). The conditions (A1) and (A2) are set out as:

(42) Condition (A1):

(43) $\begin{array}{cc}\frac{R_{12}{R}_{13}{C}^2}{G_{\mathrm{PWM}}}{s}^2+2R_{13}\mathrm{Cs}+1=2{\mathrm{LCs}}^2+2R_{23}\mathrm{Cs}+1\mathrm{wherein}\frac{R_{12}{R}_{13}{C}^2}{G_{\mathrm{PWM}}}=2\mathrm{LC}\mathrm{and}{R}_{13}=R_{23}& \left(6\right)\end{array}$
Condition (A2):
2R.sub.13C>L/R.sub.23(7)

(44) Accordingly, with conditions (A1) and (A2) satisfied, the simplified expression for G.sub.outer is then:

(45) $\begin{array}{cc}{G}_{\mathrm{outer}}=\frac{R_{12}}{R_{11}}\frac{1}{R_{22}{R}_{23}{C}^2{s}^2}\frac{2R_{13}\mathrm{Cs}+1}{\frac{L}{R_{23}}s+1}& \left(8\right)\end{array}$

(46) That is, if the conditions (A1)) and (A2) are satisfied, the two zeros in the outer feedback loop 904 cancel the poles of the inner feedback loop 902. Hence, the proposed double-feedback PWM CDA 900 simplifies to a three pole and a one zero arrangement. More specifically, with respect to equation (5), it is to be appreciated that if the conditions (A1) and (A2) are satisfied, the positions of two zeros are the same as the positions of two poles. Hence, the two poles are cancelled by the two zeros. So effectively, the PWM CDA 900 simplifies to a three pole and one zero arrangement. The conditions (A1) and (A2) ensure a perfect pole-zero cancellation. Practically, perfect cancellation is a strict requirement to obtain a stable PWM CDA 900. The PWM CDA 900 may have a stable configuration as long as positions of the poles and zeros are close. It is however to be appreciated the positions of the poles and zeros may deviate due to process variations of resistors (R), capacitors (C) and inductors (L) arranged in the PWM CDA 900, but usually do not significantly affect the stability of the PWM CDA 900. Compared to the conventional double-feedback PWM CDA 600, a total number of poles (in the proposed double-feedback PWM CDA 900) are reduced from four to three. Effectively, the loop gain and phase shift of the outer feedback loop 904 is now equivalent to a system with a double-pole having lead-lag compensation. Hence the double-feedback PWM CDA 900 is considered to be stable. It is to be appreciated that the overall loop gain of the double-feedback PWM CDA 900 is significantly higher than that of a design based on a single-feedback loop, and also easily configurable to be significantly higher than the conventional double-feedback PWM CDA 600.

(47) For completeness, it is highlighted that it is not necessary for perfect pole-zero cancellation to be attained (i.e. where this may be the case for practical implementations). To clarify, although a perfect pole-zero cancellation is preferred, it may be not necessary. This is because while a perfect pole-zero cancellation is designed for and intended, when a circuit of the double-feedback PWM CDA 900 is being designed, but however due to process variations (i.e. the process variations for resistors and capacitors is typically about 20%), a perfect cancellation may be difficult to attain. In the proposed double-feedback PWM CDA 900, the stability of the double-feedback PWM CDA 900 is arranged to be unaffected by said process variations, although the pole-zero cancellation is only partial (and not perfect). In this instance, although the double-feedback PWM CDA 900 is configured as a five poles and three zeros arrangement, the double-feedback PWM CDA 900 preserves the stability characteristics due to partial cancellation of the at least one pole of the closed-loop gain of the inner feedback loop 902. In this manner, the overall loop gain of the double-feedback PWM CDA 900 is thus still significantly higher than the conventional double-feedback PWM CDA 600, thereby ensuring reduced non-linearities.

(48) The remaining configurations will be described hereinafter. For the sake of brevity, description of like elements, functionalities and operations that are common between the different configurations are not repeated; reference will instead be made to similar parts of the relevant configuration(s).

(49) A triple-feedback PWM CDA 1200 (as shown in FIG. 12), based upon the double-feedback PWM CDA 900, is now disclosed below in a sixth embodiment. Specifically, it is to be appreciated that as the overall phase shift of the loop gain of the two inner feedback loops (in the double-feedback PWM CDA 900) is equivalent to a single feedback PWM CDA, an additional feedback loop 1202 (i.e. hereafter as third feedback loop) may be included to further increase the loop gain, which then re-configures the double-feedback PWM CDA 900 to become the triple-feedback PWM CDA 1200. So, the triple-feedback PWM CDA 1200 is a combination of the double-feedback PWM CDA 900 (of FIG. 9a) with the third feedback loop 1202, whose outputs are serially coupled to the inputs of the double-feedback PWM CDA 900, as depicted in FIG. 12. The third feedback loop 1202 acts as a third integrator whose input is electrically coupled to an input of the triple-feedback PWM CDA 1200 for receiving a signal to be amplified, and to an output of the triple-feedback PWM CDA 1200. In contrast, it is highlighted that in conventional loop filters, having a triple-feedback loop arrangement generally instead causes instability or that the resulting loop gain attained is even lower than a double-feedback arrangement, due to instability.

(50) To illustrate significance of the triple-feedback PWM CDA 1200, the overall loop-gains of the conventional double-feedback PWM CDA 600 (of FIG. 6), double-feedback PWM CDA 900 (of FIG. 9a), and triple-feedback PWM CDA 1200 are shown in a comparison graph 1300 of FIG. 13. From the graph 1300, it is apparent that compared to the conventional double-feedback PWM CDA 600, the loop-gain of the proposed double-feedback PWM CDA 900 is about 10 dB higher for the frequency range of 600 kHz-20 kHz. Accordingly, this approximately translates to a significant 10 dB improvement in PSRR and PS-IMD (and other non-linearities). In contrast, the loop-gain of the proposed triple-feedback PWM CDA 1200 is comparatively higher: about 40 dB higher for frequencies less than or equal to 1 kHz, and more than 17 dB higher for frequencies between 1 kHz-20 kHz. The improved loop gain (of the proposed triple-feedback PWM CDA 1200) beneficially translates to commensurable significant improvements in the PSRR and PS-IMD (and other non-linearities).

(51) FIG. 14 shows a block diagram of another double-feedback PWM CDA 1400 (having a variant loop filter), based on a seventh embodiment. The seventh embodiment is based largely upon the fifth embodiment. Particularly, compared to the double-feedback PWM CDA 900 of FIG. 9a, the present double-feedback PWM CDA 1400 is further configured with two additional identical capacitors 1402 (i.e. respectively labelled as C.sub.13 in FIG. 14) in the second integrator 906. Each capacitor 1402 is in a parallel circuit arrangement with a corresponding resistor labelled as R.sub.13 (also positioned in the second integrator 906), and both are coupled to a common ground. For this present double-feedback PWM CDA 1400, the closed-loop gain of the inner feedback loop 902 (of the variant loop filter), G.sub.inner,alt, and the loop gain of the outer feedback loop 904, G.sub.outer,alt, are thereby respectively expressed as equations (9) and (10) below.

(52) $\begin{array}{cc}{G}_{\mathrm{inner},\mathrm{alt}}=\frac{R_{12}}{R_{11}}\left[\frac{\left(2R_{13}C+R_{13}{C}_{13}\right)s+1}{\frac{R_{12}{R}_{13}{C}^2{s}^2}{G_{\mathrm{PWM}}}+\left(2R_{13}C+R_{13}{C}_{13}\right)s+1}\right]& \left(9\right)\\ \begin{array}{c}{G}_{\mathrm{outer},\mathrm{alt}}=G_2{G}_{\mathrm{inner},\mathrm{alt}}\\ =\frac{R_{12}}{R_{11}}\frac{1}{R_{22}{R}_{23}{C}^2{s}^2}\left[\frac{\left(2R_{13}C+R_{13}{C}_{13}\right)s+1}{\begin{array}{c}\frac{R_{12}{R}_{13}{C}^2{s}^2}{G_{\mathrm{PWM}}}+\\ \left(2R_{13}C+R_{13}{C}_{13}\right)s+1\end{array}}\right]\\ [\frac{2{\mathrm{LCs}}^2+2R_{23}\mathrm{Cs}+1}{\frac{L}{R_{23}}s+1}]\end{array}& \left(10\right)\end{array}$

(53) It is apparent from equation (10) that, similar to the fifth embodiment, if conditions (B1) and (B2) below are satisfied, equation (10) may be simplified to equation (13). Conditions (B1) and (B2) are set out as:

(54) Condition (B1):

(55) $\begin{array}{cc}\frac{R_{12}{R}_{13}{C}^2{s}^2}{G_{\mathrm{PWM}}}+\left(2R_{13}C+R_{13}{C}_{13}\right)s+1=2{\mathrm{LCs}}^2+2R_{23}\mathrm{Cs}+1\mathrm{wherein}\frac{R_{12}{R}_{13}{C}^2}{G_{\mathrm{PWM}}}=2\mathrm{LC}\mathrm{and}2R_{13}C+R_{13}{C}_{13}=R_{23}C& \left(11\right)\end{array}$
Condition (B2):
2R.sub.13C+R.sub.13C.sub.13>L/R.sub.23(12)

(56) Accordingly, with conditions (B1) and (B2) satisfied, the simplified expression for G.sub.outer,alt is then:

(57) $\begin{array}{cc}{G}_{\mathrm{outer},\mathrm{alt}}=G_2{G}_{\mathrm{inner},\mathrm{alt}}=\frac{R_{12}}{R_{13}}\frac{1}{R_{22}{R}_{23}{C}^2{s}^2}\left[\frac{\left(2R_{13}C+R_{13}{C}_{13}\right)s+1}{\frac{L}{R_{23}}s+1}\right]& \left(13\right)\end{array}$

(58) Similar to the fifth embodiment, for the seventh embodiment, the loop gain of the outer feedback loop 904 has a double-pole with lead-lag compensation, hence providing a stable feedback loop. An advantage of the seventh embodiment is that there is usage of a further design parameter in the form of capacitance (i.e. the two capacitors 1402, labelled as C.sub.13 in FIG. 14), and hence provides an additional degree of design freedom for the CDA, albeit at a cost of slight increase in hardware requirements and power dissipation. Nevertheless, for the double-feedback PWM CDA 1400 (of the seventh embodiment), the overall hardware and power dissipation overheads (compared to conventional designs) are considered negligible (i.e. less than 1%) in the context of total IC area needed for the PWM CDA 1400.

(59) For completeness, it is again to be appreciated that for practical implementations, the pole-zero cancellation is not perfect due to components variation and etc. Nevertheless, the stability condition is still provided for in the double-feedback PWM CDA 1400 (of the seventh embodiment) and so the loop gain is easily designed to be significantly higher than conventional designs, thereby obtaining the desired improvements in PSRR and PS-IMD (and other non-linearities).

(60) In summary, the proposed loop filters are configured to beneficially improve the loop gain of double-feedback CDAs (e.g. by more than 10 dB), which consequently may translate to greater than 10 dB of improvement in PSRR and PS-IMD. Furthermore, since the phase-shift of the loop gain of the double-feedback arrangement (of the loop filter) is comparable to that of a single feedback arrangement, realization of a triple feedback PWM CDA with significantly (e.g. greater than 40 dB at a frequency of 217 Hz) higher loop gain (compared to a double-feedback arrangement) is also possible. Accordingly, the PSRR and PS-IMD are also reduced by approximately the same amount (subjected to the floor noise).

3. Relationship Between the Ground-Bounce-Insensitive Dead Time Circuit and High-Gain Loop Filter Designs

(61) It is to be appreciated that some key attributes that may qualify the performance of CDAs include PSRR, PS-IMD and THD+N. In this regard, one object of the proposed dead-time circuit 750, 800, 840, 870 is to improve the THD+N attribute. Compared to conventional dead time circuits, the proposed dead time circuit 750, 800, 840, 870 is able to largely eliminate false switching in the Class D output stage that occur due to ground-bounce. As a result, the THD+N performance is improved significantly. On the other hand, an object of the proposed (high-loop gain) loop filter is to improve all three attributes: PSRR, PS-IMD and THD+N. Compared to conventional loop filters, the proposed loop filter is advantageous in that comparatively higher loop gain may be attained, thus resulting in better PSRR, PS-IMD and THD+N. Therefore, in a further embodiment, the proposed dead-time circuit 750, 800, 840, 870 and (high-loop gain) loop filter may be incorporated in combination, if desired, in a switching circuit/amplifier (e.g. an audio CDA) to improve the PSRR, PS-IMD and THD+N attributes simultaneously. The switching circuit may be any of those as mentioned in the first embodiment, and hence not repeated for brevity.

(62) While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary, and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practising the claimed invention.

(63) For example, the proposed dead-time circuit 750, 800, 840, 870 and (high-loop gain) loop filter are each independently usable without the other. Also, in respect of the proposed dead-time circuit 750, 800, 840, 870, other suitable logic gates may be used in place of the first and second NOR gate 766a, 766b (of FIG. 7b/8c) or the first and second AND gates 802a, 802b (of FIG. 8a/8b) or the first and second inverters 770a, 770b. Further, it is to be appreciated that the proposed dead-time circuit 750, 800, 840, 870 and proposed (high-loop gain) loop filter may be fabricated using the CMOS process, or any other suitable fabrication processes.