Semiconductor Device

Abstract

The present application provides a semiconductor device, which includes a shallow trench isolation structure, located in a substrate, and comprises a first region and a second region alternately arranged. The width of the first region is greater than the width of the second region. A first filling layer and a second filling layer are sequentially arranged in the first region, and a first filling layer is arranged in the second region; wherein, in the first region, the height of the first filling layer is lower than the height of the second filling layer. The device provides an advantage that the saddle-shaped shallow trench isolation structure in the first region reduces the trapping centers during any interference from adjacent word line structures, and also reduces the overlap areas of adjacent word line structures formed subsequently, thereby reducing parasitic capacitance, curtailing leakage and improving the semiconductor device's performance.

Claims

1. A semiconductor device, comprising: a shallow trench isolation structure, located in a substrate, wherein the shallow trench isolation structure comprises a first region and a second region alternately arranged; wherein a width of the first region is greater than a width of the second region; wherein the first region comprises a first filling layer and a second filling layer sequentially arranged, wherein the second region comprises the first filling layer; and wherein a height of the first filling layer is lower than a height of the second filling layer in the first region.

2. The semiconductor device according to claim 1, wherein the first filling layer in the first region and the first filling layer in the second region have a same height.

3. The semiconductor device according to claim 1, wherein the height of the first filling layer in the first region is smaller than the height of the first filling layer in the second region.

4. The semiconductor device according to claim 1, wherein the first filling layer is disposed around the second filling layer.

5. The semiconductor device according to claim 1, wherein a width of the second filling layer is less than or equal to a half of a width of the first region.

6. The semiconductor device according to claim 1, wherein the first filling layer is an oxide layer, and the second filling layer is a nitride layer.

7. The semiconductor device according to claim 1, further comprising: an active region, disposed between the first region and the second region of the shallow trench isolation structure; and a word line structure arranged above the first region of the shallow trench isolation structure, the active region, and the second region of the shallow trench isolation structure along a predetermined direction.

8. The semiconductor device according to claim 7, wherein a thickness of the word line structure disposed above the first filling layer in the first region is greater than a thickness of the word line structure disposed above the active region.

9. The semiconductor device according to claim 7, wherein a thickness of the word line structure disposed above the second filling layer in the first region is smaller than the thickness of the word line structure disposed above the active region.

10. The semiconductor device according to claim 9, wherein the thickness of the word line structure disposed above the second filling layer in the first region is greater than or equal to two-thirds of the thickness of the word line structure disposed above the active region.

11. The semiconductor device according to claim 7, wherein a thickness of the word line structure disposed above the second filling layer in the first region is equal to the thickness of the word line structure disposed above the active region.

12. The semiconductor device according to claim 7, wherein the word line structure comprises a gate oxide layer, a buffer layer, and a metal layer, wherein the buffer layer covers the gate oxide layer, and wherein the metal layer covers the buffer layer.

13. The semiconductor device according to claim 7, wherein the semiconductor device further comprises more than one of the word line structure, wherein the more than one of the word line structures are arranged in parallel in a direction perpendicular to the predetermined direction.

14. The semiconductor device according to claim 13, wherein the first region and the second region of the shallow trench isolation structure is arranged in a staggered manner adjacent to an area where the one of the word line structures passes.

15. The semiconductor device according to claim 7, wherein the active region extends in a direction at an acute angle to the predetermined direction.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to explain the technical solutions of the embodiments of the present application more clearly, the following will briefly introduce the drawings that need to be used in the embodiments of the present application. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative work, other drawings can be obtained from these drawings.

[0025] FIG. 1 is a schematic diagram of an active region and a shallow trench isolation region of a word line structure of a semiconductor device;

[0026] FIG. 2 is a schematic top view of the semiconductor device according to a first embodiment of the present application;

[0027] FIG. 3 is a schematic cross-sectional view taken along line B-B in FIG. 2;

[0028] FIG. 4 is a schematic top view of a semiconductor device according to a second embodiment of the present application;

[0029] FIG. 5 is a schematic cross-sectional view taken along line B-B in FIG. 4;

[0030] FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present application;

[0031] FIG. 7A is a schematic cross-sectional view taken along line C-C in FIG. 1 in an existing art;

[0032] FIG. 7B is a schematic cross-sectional view along the line C-C in FIG. 4 according to the present application.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0033] In order to make the purpose, technical means and effects of this application clearer and clearer, the application will be further elaborated below in conjunction with the accompanying drawings. It should be understood that the embodiments described here are only a part of the embodiments of the present application, rather than all the embodiments, and are not intended to limit the present application. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative work shall fall within the protection scope of this application.

[0034] Please refer to FIG. 1. It has been discovered by the applicant that in a semiconductor device, a thickness of the word line structure at 44 nm (for example, word line structure 10-2) above the active region (for example, active region 11-2) is less than a thickness of the word line structure at 80 nm (for example, word line structure 10-1) above the trench isolation structure 12. Thus, the word line structure (for example, word line structure 10-1) disposed above the shallow trench isolation structure 12) has a larger thickness, then along the extension direction of the active region (for example, active region 11-2), the word line structure (for example, word line structure 10-1) arranged above the shallow trench isolation structure 12 and the arranged in overlap area of the word line structure (for example, the word line structure 10-2) above the active region (for example, the active region 11-2) is relatively large. Then, when the word line structure (for example, word line structure 10-1) is powered on, it can connect to the adjacent word line structure (for example, the word line structure 10-2) to form a larger overlap area, which generates a larger parasitic capacitance, which in turn causes leakage.

[0035] In view of the foregoing problems, the present application provides a semiconductor device that can reduce the overlap area of the word line structure located above the active region and the word line structure located above the shallow trench isolation region in the active region extension direction, thereby reducing parasitic capacitance to reduce leakage generation.

[0036] FIG. 2 is a schematic top view of the semiconductor device according to a first embodiment of the present application, and FIG. 3 is a schematic cross-sectional view taken along line B-B in FIG. 2. In FIG. 2 and FIG. 3, the semiconductor device has a substrate 200 and a shallow trench isolation structure 210.

[0037] The substrate 200 may be a single crystal silicon (Si) substrate, a germanium (Ge) substrate, a SiGe substrate, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like. According to the actual requirements of the device, a suitable semiconductor material can be selected as the substrate 200, which is not limited herein. In this embodiment, description is made by taking the substrate 200 as a single crystal silicon substrate as an example.

[0038] The shallow trench isolation structure 210 is located in the substrate 200, and the shallow trench isolation structures 210 divide the substrate 200 into a plurality of active regions 220.

[0039] In this embodiment, the method for forming the shallow trench isolation structures 210 in the substrate 200 may be: forming shallow trenches in the substrate 200 by photolithography and etch processes, and the areas defined between the shallow trenches are active regions 220. The shallow trenches are filled with material to form the shallow trench isolation structures 210. Herein, the active regions 210 extend along a predetermined direction E.

[0040] The shallow trench isolation structures 210 include the first regions 210A and the second regions 210B arranged alternately along a predetermined direction, and an active region 220 is disposed between one first region 210A and one second region 210B in the shallow trench isolation structure 210. The width W1 of the first region 210A is greater than the width W2 of the second region 210B. Herein, in FIG. 2, the first region 210A and the second region 210B are schematically outlined by dashed lines. The predetermined direction is the extension direction of the subsequently formed word line structures, and the word line structures periodically passe through the first regions 210A, the active regions 220, the second regions 210B, and the active regions 220. A word line structure passing through the first regions 210A is called a passing word line (Passing WL).

[0041] In this embodiment, the predetermined direction is the D direction as shown in FIG. 2. The predetermined direction D and the extending direction E of the active region 220 form an acute angle. Preferably, the acute angle is an angle between 60 degree and 80 degree, for example, is 69 degree according some embodiments. In other embodiments of the present application, the predetermined direction D and the active region extension direction E may also form a right angle. Herein, the included angle between the predetermined direction D and the extending direction E of the active region 202 depends on the manufacturing process of the active region 220, and will not be repeated here.

[0042] In the predetermined direction D, between two active regions 220 arranged at intervals, if the width of the shallow trench isolation structure 210 is relatively large, the isolation structure is the first region 210A; between the two adjacent active regions 220, if the width of the shallow trench isolation structure 210 is relatively small, the structure is the second region 210B.

[0043] A first filling layer 211 and a second filling layer 212 are sequentially disposed in the first regions 210A, and a first filling layer 211 is arranged in the second area 210B. Specifically, a shallow trench is formed in the substrate 200 by using photolithography and etch processes. After the shallow trench is formed, the first region 210A is formed by a process such as chemical vapor deposition. A first filling layer 211 covers the sidewalls of the shallow trench and has the same profile as the shallow trench, and then the second filling layer 212 fills the shallow trench 210. The first filling layer 211 and the second filling layer 212 together serve as the shallow trench isolation structure 210. In the second region 210B, the first filling layer 211 is formed by a process such as chemical vapor deposition. The first filling layer 211 fills up the shallow trench and serves as the shallow trench isolation structure 210.

[0044] Since the width W1 of the first region 210A is larger than the width W2 of the second region 210B, after the first filling layer 211 is formed in the shallow trench, the shallow trench in the first region 210A is not filled up, as the shallow trenches located in the second region 210B are filled. Therefore, the second filling layer 212 continues to fill in the first region 210A, thus to fill the shallow trenches.

[0045] Further, in the first regions 210A, the first filling layer 211 is arranged around the second filling layer 212, that is, in the first regions 210A, the second filling layer 212 is arranged in the center of the first region 210A, the first filling layer 211 is disposed on the edge of the first region 210A. Furthermore, in the first region 210A, the first filling layer 211 evenly surrounds the second filling layer 212 to improve the isolation performance of the shallow trench isolation structure 210.

[0046] In the first region 210A, the height H1 of the first filling layer 211 is smaller than the height H2 of the second filling layer 212. Herein, in this embodiment, the height H1 of the first filling layer 211 refers to the distance from the bottom surface of the shallow trench isolation structure 210 to the upper surface of the first filling layer 211, and the height H2 of the second filling layer 212 refers to the distance from the bottom surface of the shallow trench isolation structure 210 to the upper surface of the second filling layer 212 of the shallow trench isolation structure 210. The distance from the bottom surface of the shallow trench isolation structure 210 to the upper surface of the first filling layer 211 is smaller than the distance from the bottom surface of the shallow trench isolation structure 210 to the top surface of the second filling layer 212. In other embodiments of the present application, a certain baseline of the substrate 200 can also be used as a reference standard to define the heights of the first filling layer 211 and the second filling layer 212. It can be understood that, in order to facilitate comparison, the height reference of the first filling layer 211 and the second filling layer 212 should be the same.

[0047] Specifically, in this embodiment, in the first region 210A, the shallow trench isolation structure is a saddle shape with a high middle and low ends. After the word line structure is subsequently formed, the shallow trench isolation structure passes through the first The thickness of the middle region (that is, the region above the second filling layer 212) of the word line structure of the region 210A (that is, through the word line) is smaller than the thickness of the two end regions (that is, the region above the first filling layer 211), so that in the direction E of the active region extension direction, the overlap area between the word line structure and its adjacent word line structure passing through the active regions is reduced, thereby reducing the word line structure and the sides of the word line structure located in the first regions 210A. The parasitic capacitances between the word line structures that pass through the active regions 220 are not turned on, thereby reducing the generation of leakage current, greatly improving the electrical performance of semiconductor devices, and improving the yield of semiconductor device products.

[0048] Furthermore, in this embodiment, in the manufacturing process of the semiconductor device of the present application, the first filling layer 211 located in the first region 210A and the second region 210B can be formed by the same process step. The first filling layer 211 in the first region 210A has the same height as the first filling layer 211 in the second region 210B, that is, the height H1 of the first filling layer 211 in the first region 210A is the same as the height H3 of the first filling layer 211 in the first region 210B. In other embodiments of the present application, since the width W1 of the first region 210A is greater than the width W2 of the second region 210B, when the filler is etched to form the first filling layer, the etching rate of the first filling layer in the region 210A is greater than that of the second region 210B, so that the height H1 of the first filling layer 211 in the first region 210A is smaller than the height H3 of the first filling layer 211 in the second region 210B.

[0049] Further, in this embodiment, the width W3 of the second filling layer 212 is less than or equal to half of the width W1 of the first region 210A, so as to maximize the electrical isolation performance of the shallow trench isolation structure and minimize the parasitic capacitance caused by the word lines, thereby reducing leakage current.

[0050] Further, the first filling layer 211 is an oxide layer, and the second filling layer 212 is a nitride layer, these can be determined according to the material of the semiconductor substrate 200. For example, in this embodiment, the semiconductor substrate 200 is a single crystal silicon substrate, the first filling layer for 210A is a silicon oxide layer, and the second filling layer is a silicon nitride layer. In other embodiments of the present application, for the semiconductor germanium substrate, the first filling layer for 210A is a germanium oxide layer, and the second filling layer 212 is a germanium nitride layer. Among them, the thermal expansion coefficient of nitride material is close to the thermal expansion coefficient of the semiconductor substrate, so nitride can reduce stress and improve the performance of the semiconductor device in the high-temperature manufacturing process of the other subsequent processes.

[0051] The semiconductor device of the present application includes a saddle-shaped shallow trench isolation structure in the first region to reduce the trapping centers during the interference of the word line structures, and to also reduce the overlapping area of the adjacent word line structures formed subsequently, thereby reducing the parasitic capacitance, leakage and improving the performance of semiconductor devices.

[0052] This application also provides a second embodiment of a semiconductor device. FIG. 4 is a schematic top view of a semiconductor device according to a second embodiment of the present application, and FIG. 5 is a schematic cross-sectional view taken along line B-B in FIG. 4. Please refer to FIG. 4 and FIG. 5, the semiconductor device of the present application further includes a word line structure 230. The word line structure 230 is disposed in the first region 210A of the shallow trench isolation structure 210, the active region 220, and the second region 210B of the shallow trench isolation structure 210 along a predetermined direction.

[0053] Specifically, in this embodiment, the word line structure 230 extends in a predetermined direction (direction D as shown in FIG. 4), and sequentially passes through the first regions 210A of the shallow trench isolation structure 210, the active regions 220, the second regions 210B of the shallow trench isolation structure 210. The word line structure 230 fills the shallow trench isolation structure 210 and the trenches of the active region 220 to form a buried word line structure. Herein, since the height of the first filling layer 211 is smaller than the height of the second filling layer 212 in the first region 210A, after the word line structure 230 is formed, the thickness S1 of the word line structure 230 above the first filling layer 211 is greater than the thickness S2 of the word line structure 230 disposed above the second filling layer 212 of the first region 210A.

[0054] That is, referring to FIG. 5, in the first region 210A, the word line structure 230 is a concave shape with a thin middle portion and thick ends, that is, the thickness of the middle region (that is, the region above the second filling layer 212) of the word line structure passing through the first region is less than the thickness of the two end regions (that is, the region above the first filling layer 211). Referring to FIG. 7B, which is a schematic cross-sectional view along the C-C line in FIG. 4, along the extending direction E of the active region 220, the thickness of the word line structure 230 is small, so that the word line structure 230 passing through the active region in the extension direction E of the active area 220 has a smaller overlapping area with adjacent ones, thereby reducing the parasitic capacitance between the word line structure 230 located in the first region 210A and the word line structure that passes the active region 220 and yet not turned on, thereby reducing the generation of leakage current, the electrical performance of semiconductor devices is greatly improved, and the yield of semiconductor products is improved.

[0055] Further, in this embodiment, the thickness S1 of the word line structure 230 disposed above the first filling layer 211 of the first region 210A is greater than the thickness S3 of the word line structure 230 disposed above the active region 220, and the thickness S4 (not shown in FIG. 5) of the word line structure 230 disposed above the first filling layer 211 of the second region 210B is greater than the thickness S3 of the word line structure 230 disposed above the active region 220. That is, in the semiconductor device of the present application, the word line structure located above the shallow trench isolation structure 210 and the word line structure located above the active region 220 are in a saddle structure to enhance the performance of the semiconductor device. The semiconductor device of the present application can reduce parasitic capacitance and leakage current while keeping the word line structure in a saddle structure, which greatly improves the performance of the semiconductor device. Further, the thickness S2 of the word line structure 230 disposed above the second filling layer 212 of the first region 210A is smaller than the thickness S3 of the word line structure 230 disposed above the active region 220, and is disposed in the first region 210A. The thickness S2 of the word line structure 230 above the second filling layer 212 in a region 210A is greater than or equal to two-thirds of the thickness S3 of the word line structure 230 disposed above the active region 220, so as to reduce parasitic capacitance. At the same time, the resistance of the word line structure is maintained at a reasonable level.

[0056] In another embodiment of the present application, the thickness S2 of the word line structure 230 disposed above the second filling layer 212 of the first region 210A is equal to the thickness S3 of the word line structure 230 disposed above the active region 220. Specifically, please refer to FIG. 6, which is a schematic cross-sectional view of the third embodiment of the semiconductor device of this application. In the third embodiment, the word line structure 230 disposed above the second filling layer 212 of the first region 210A has the thickness S2 which is equal to the thickness S3 of the word line structure 230 disposed above the active region 220.

[0057] Further, please continue to refer to FIGS. 4 and 5, the word line structure 230 includes a gate oxide layer 231, a buffer layer 232 and a metal layer 233. The gate oxide layer 231 covers the shallow trench isolation structure 210 and the surface of the active region 220 where the word line structure 230 needs to be formed, the buffer layer 232 covers the gate oxide layer 231, and the metal layer 233 covers the buffer layer 232.

[0058] This embodiment discloses a method for preparing the word line structure 230 specifically includes the following steps: disposing the surface of the shallow trench isolation structure 210 and the active region 220 with a gate oxide layer 231, where thermal oxidation can be used, and methods such as oxidation is applied to form the gate oxide layer 231; forming the buffer layer 232 on the surface of the gate oxide layer 231, wherein the buffer layer 232 can be formed by atomic layer deposition or chemical vapor deposition; filling the metal material layer, wherein the method of filling the metal material layer can be a chemical vapor deposition process; removing the excess metal material layer, and only leaving the metal material above the shallow trench isolation structure 210 and the active region 220 layer to form a metal layer 233, in which a mechanical grinding and etching process can be used to remove the excess metal material layer.

[0059] In this embodiment, the gate oxide layer 231 is silicon oxide, the buffer layer 232 is a Ti/TiN layer, and the metal layer 233 is a metal tungsten layer. In other embodiments of the present application, the word line structure 230 may also be other structures.

[0060] The semiconductor device includes a plurality of word line structures 230, arranged in parallel in a direction perpendicular to the predetermined direction (direction D as shown in FIG. 4). When a word line structure is energized and turned on, it will form a parasitic capacitance with other non-energized word line structures 230 in the active region 220 adjacent to it, thereby causing leakage. In the present application, a first filling layer 211 and a second filling layer 211 with different heights are arranged in the first region 210A, so that the thickness of the word line structure 230 formed in the first region 210A is reduced, so as to reduce trapping centers during the interference of the word line structure, and reduce the overlapping area of adjacent word line structures, thereby reducing parasitic capacitance, reducing leakage, and improving the performance of semiconductor devices.

[0061] For example, please continue to refer to FIG. 4, taking the word line structure 230-1, the word line structure 230-2, and the word line structure 230-3 as examples. The word line structure 230-1 extends along the D direction and periodically passes through the second regions 210B, the active regions 220, the first regions 210A, and the active region 220; the word line structure 230-2 extends along the D direction and passes through the second region 210B periodically, the active region 220, the first region 210A, and the active region 220, the word line structure 230-3 extends along the D direction, and periodically passes through the second regions 210B, the active regions 220, the first regions 210A, and the active regions 220. The thickness of the word line structure 230-1 located above the second filling layer 212 of the first region 210A is smaller than that of the word line structure 230-2 located above the active region 220-2 and the thickness of the word line structure 230-2 located above the active regions 220-2. The thickness of the word line structure 230-3 above the source regions 220-3 reduces the trapping centers during the interference of the word line structure, and makes it located in the direction along the extension direction (E direction) of the active regions 220. The overlapping area of the word line structure 230-1 above the second filling layer 212 of the first region 210A and the word line structure 230-2 and the word line structure 230-3 above the active region 220 is reduced to be small. When the word line structure 230-1 is activated but the word line structure 230-2 and the word line structure 230-3 are not activated, the electron transmission is reduced, thereby reducing the parasitic capacitance, reducing the leakage, and improving the performance of the semiconductor device.

[0062] Further, adjacent to the area through which the word line structure 230 passes, the first region 210A and the second region 210B are staggered. Specifically, please continue to refer to FIG. 4, taking the word line structure 230-1 and the word line structure 230-2 as an example, the first region 210A located in the area passed by the word line structure 230-1 and the first region 210A of the area passed by the word line structure 230-2 are not arranged in the direction perpendicular to the predetermined direction (D direction), nor are they arranged in the extension direction of the active area 220 (E direction) are arranged directly opposite to each other, but arranged in a staggered way. The second region 210B located in the area passed by the word line structure 230-1 and the second region 210B located in the area passed by the word line structure 230-2 are also set staggered. Wherein, the first region 210A located in the area passed by the word line structure 230-1 and the second area 210B located in the area passed by the word line structure 230-2 are located partially overlapping along the extension direction of the active area 220 (E Direction).

[0063] Further, in the present embodiment, in the extending direction (E direction) of the active regions 220, the first region 210A located in the area passed by the word line structure 230-1 is different from the first region 210A located in the area where the word line structure 230-2 passes. The first region 210A of the area passed by 230-2 is staggered and partially overlapped, and the second region 210B located in the area passed by the word line structure 230-1 and the second region 210B located in the area passed by the word line structure 230-2 are completely staggered and has no overlap.

[0064] Furthermore, in this embodiment, the area above the word line structure 230 and the area of the substrate 200 not covered by the word line structure 230 area are also covered with a passivation layer. The passivation layer protects the word line structure 230 and the substrate 200 from damages of the external environment or subsequent processes on the semiconductor devices. In this embodiment, the passivation layer is a silicon nitride layer. In other embodiments of the present application, the passivation layer may also be other structural layers.

[0065] The thickness of the word line structure located above the second filling layer 212 of the first region 210A of the shallow trench isolation structure 210 is reduced, thereby reducing the trapping centers of the subsequent interference devices to the word lines, which then reduces the parasitic capacitance, leakage current and improve the performance of semiconductor devices.

[0066] The principle of reducing parasitic capacitance of the semiconductor device of the present application will be further explained below in conjunction with FIG. 7A and FIG. 7B. FIG. 7A is a schematic cross-sectional view taken along line C-C in FIG. 1 in the existing art, in which word line structures are provided above the active regions and above the shallow trench isolation structure; FIG. 7B is a schematic cross-sectional view taken along line C-C in FIG. 4 of the present application, herein, a word line structure is provided above the active region and above the second filling layer of the first region of the shallow trench isolation structure.

[0067] Referring to FIG. 1 and FIG. 7A, the active region 11-2 and the active region 11-3 of the semiconductor device are respectively provided with a word line structure 10-2 and a word line structure 10-3, and the shallow trench isolation structure 12 is provided with word line structure 10-1. Herein, the thickness of the word line structure 10-2 and the word line structure 10-3 arranged above the active regions is smaller than the thickness of the word line structure 10-1 arranged above the shallow trench isolation structure 12, that is, the thickness of the word line structure 10-1 arranged above the shallow trench isolation structure 12. The word line structure 10-1 above the isolation structure 12 has a relatively large thickness, which means, the word line structure 10-1 disposed above the shallow trench isolation structure 12 along the extension direction of the active region 11-2 and the active region 11-3 have relatively large overlapping areas with the word line structure 10-2 and the word line structure 10-3 disposed above the active area. When the word line structure 10-1 is energized and turned on, it will induce the adjacent word line structure 10-2 and the word line structure 10-3 which are located above the active area 11-2 and the active area 11-3 that are not turned on. The overlapping areas are larger, so electrons are transported more, resulting in larger parasitic capacitance, which in turn causes leakage.

[0068] In FIG. 4 and FIG. 7B, the active region 220-2 and the active region 220-3 of the semiconductor device are respectively provided with a word line structure 230-2 and a word line structure 230-3, the first shallow trench isolation structure of word line structure 230-1 is provided on the second filling layer 212 of the first region 210A. Herein, the thickness of the word line structure 230-1 disposed on the second filling layer 212 of the first region 210A of the shallow trench isolation structure 210 is less than or equal to the thickness of the word line structure 230-1 disposed above the active region 220-2 and the active region 220-3. The thickness of the word line structure 230-1 disposed above the second filling layer 212 of the first region 210A of the shallow trench isolation structure 210, compared with the existing art (the structure shown in FIG. 7A), is reduced. So that the second filling layer 212 of the first region 210A of the shallow trench isolation structure 210, arranged along the extension direction of the active area 220-2 and the active area 220-3, has less overlap area with the word line structure 230-1 above the layer 212, and the word line structure 230-2 and the word line structure 230-3 disposed over the active area 220-2 and the active area 220-3 is reduced. When the word line structure 230-1 is energized and turned on, it induces less electron transmission from the not-turned-on yet adjacent word line structure 230-2 and the word line structure 230-3, located above the active area 220-2 and the active area 220-3, and the word line structure 230-3, because of the smaller overlapping area, thereby reducing the parasitic capacitance, the leakage, and improving the performance of the semiconductor device.

[0069] The above are only the preferred embodiments of this application. It should be pointed out that for those of ordinary skill in the art, without departing from the principle of this application, several improvements and modifications can be made, and these improvements and modifications should also be considered in the scope of protection of this application.