CALIBRATION DEVICE, SETUP, AND METHOD FOR MEASURING A RADIO FREQUENCY SIGNAL GENERATOR

Abstract

The present disclosure relates to a calibration device, a calibration setup, and a calibration method for measuring a radio frequency (RF) signal generator. The calibration device comprises an input configured to receive an RF signal of the RF signal generator, wherein the RF signal is output for the purpose of calibration and has discrete frequency lines. The calibration device further comprises a mixer configured to mix the RF signal with a first local oscillator (LO) signal and a second LO signal. The mixing may comprise a logical AND combination of the RF and LO signals, and obtains an intermediated frequency (IF) signal. The IF signal has discrete frequency lines and has a smaller bandwidth than the RF signal.

Claims

1. A calibration device for measuring a radio frequency, RF, signal generator, the calibration device comprising: an input configured to receive an RF signal of the RF signal generator, wherein the RF signal has discrete frequency lines; a pulse generator configured to generate a first local oscillator, LO, signal and a second LO signal; and a mixer configured to mix the RF signal with the first LO signal and the second LO signal, thereby obtaining an intermediate frequency, IF, signal that has discrete frequency lines and a smaller bandwidth than the RF signal.

2. The calibration device according to claim 1, wherein the mixing of the RF signal with the first LO signal and the second LO signal comprises a logical AND combination of the RF signal, the first LO signal, and the second LO signal.

3. The calibration device according to claim 1, wherein the second LO signal is a negative and time-delayed copy of the first LO signal.

4. The calibration device according to claim 1, wherein the first LO signal and the second LO signal are selected such that a logical AND combination of the first LO signal and the second LO signal results in a comb signal; wherein the comb signal has a higher bandwidth than the RF signal; wherein the comb signal has equidistant discrete frequency lines; and wherein each of the equidistant discrete frequency lines of the comb signal is different to the discrete frequency lines of the RF signal with regard to frequency.

5. The calibration device according to claim 1, wherein the pulse generator and the mixer are integrated.

6. The calibration device according to claim 1, wherein the mixer comprises: a first stage of transistors adapted to receive the RF signal as input; a second stage of transistors connected to the first stage and adapted to receive the second LO signal as input; and a third stage of transistors connected to the second stage and adapted to receive the first LO signal as input.

7. The calibration device according to claim 6, wherein: the first stage comprises a first transistor pair connected to a current source; and the first transistor pair is controlled by the RF signal and is configured to provide a modulated current, which is modulated by the RF signal, to the second stage.

8. The calibration device according to claim 7, wherein: the second stage comprises a second transistor pair and a third transistor pair, which are each connected to the first transistor pair and are controlled by the second LO signal; the third stage comprises a fourth transistor pair and a fifth transistor pair, which are connected to the second transistor pair and the third transistor pair, respectively, and are controlled by the first LO signal; and the second and third stage are configured to mix the modulated current, which is provided by the first stage, with the second LO signal and the first LO signal, thereby providing a pulse-modulated current as the IF signal to an output of the mixer.

9. The calibration device according to claim 7, wherein: the first transistor pair comprises a first transistor and a second transistor, wherein opposite phases of the RF signal are connected to control terminals of the first transistor and the second transistor, respectively; wherein input terminals of the first transistor and the second transistor are connected to each other and to the current source; and wherein output terminals of the first transistor and the second transistor are connected to the second stage.

10. The calibration device according to claim 8, wherein: the second transistor pair comprises a third transistor and a fourth transistor connected by their input terminals, wherein opposite phases of the second LO signal are connected to control terminals of the third transistor and the fourth transistor, respectively; and the third transistor pair comprises a fifth transistor and a sixth transistor connected by their input terminals, wherein opposite phases of the second LO signal are connected to control terminals of the fifth transistor and the sixth transistor, respectively wherein the input terminals of the third, fourth, fifth, and sixth transistor are connected to the first stage; wherein output terminals of the third transistor and the sixth transistor are connected to the third stage; and wherein output terminals of the fourth transistor and the fifth transistor are connected to a first supply voltage.

11. The calibration device according to claim 8, wherein: the fourth transistor pair comprises a seventh transistor and an eighth transistor connected by their input terminals, wherein opposite phases of the first LO signal are connected to control terminals of the seventh transistor and the eighth transistor, respectively; and the fifth transistor pair comprises a ninth transistor and the tenth transistor connected by their input terminals, wherein opposite phases of the first LO signal are connected to control terminals of the ninth transistor and the tenth transistor, respectively wherein input terminals of the seventh, eighth, ninth, and tenth transistor are connected to the second stage; wherein output terminals of the seventh transistor and the tenth transistor are connected to the output of the mixer; and wherein output terminals of the eighth transistor and the ninth transistor are connected to a second supply voltage.

12. The calibration device according to claim 10, wherein: the third stage comprises a sixth transistor pair comprising an eleventh transistor and a twelfth transistor connected by their control terminals; wherein the control terminals of the eleventh transistor and the twelfth transistor are connected to the first supply voltage; wherein output terminals of the eleventh transistor and the twelfth transistor are connected to the second supply voltage; and wherein input terminals of the eleventh transistor and the twelfth transistor are connected to the output terminals of the fourth transistor and the fifth transistor, respectively.

13. The calibration device according to claim 1, further comprising: a hold gate connected to the output of the mixer; wherein the hold gate is configured to convert a current pulse of the IF signal provided by the mixer to a voltage and to hold the voltage until the next current pulse of the IF signal is output by the mixer, thereby outputting a modulated voltage as an integrated IF signal.

14. The calibration device according to claim 1, further comprising a low noise amplifier configured to amplify the RF signal before providing it to the mixer.

15. The calibration device according to claim 1, further comprising: a first frequency divider configured to receive a first clock signal, to convert the first clock signal into a second clock signal, and to provide the second clock signal to the pulse generator; wherein the pulse generator is configured to generate the first LO signal and the second LO signal based on the second clock signal.

16. The calibration device according to claim 13, further comprising: a first frequency divider configured to receive a first clock signal, to convert the first clock signal into a second clock signal, and to provide the second clock signal to the pulse generator; wherein the pulse generator is configured to generate the first LO signal and the second LO signal based on the second clock signal, the hold gate comprises a capacitor connected to the output of the mixer and a supply voltage, respectively, and comprises a switch connected in parallel to the capacitor; and the switch is controlled by the second clock signal.

17. The calibration device according to claim 15, further comprising: a second frequency divider; wherein the first frequency divider is further configured to provide the second clock signal to the second frequency divider; wherein the second frequency divider is configured to convert the second clock signal into a third clock signal; and wherein the calibration device is further configured to add the third clock signal provided by the second frequency divider to the IF signal provided by the mixer or to the integrated IF signal provided by the hold gate, thereby obtaining a modified IF signal.

18. The calibration device according to claim 17, further configured to sample the modified IF signal to reconstruct a phase of the second clock signal provided by the first frequency divider.

19. The calibration device according to claim 17, further comprising a clock output configured to output the third clock signal provided by the second frequency divider.

20. A calibration setup comprising the calibration device according to claim 1 and the signal generator configured to output the RF signal to a device under test, DUT.

21. A method for measuring a radio frequency, RF, signal generator, the method comprising: receiving an RF signal of the RF signal generator, wherein the RF signal has discrete frequency lines; and mixing the RF signal with a first local oscillator, LO, signal and a second LO signal, thereby obtaining an intermediate frequency, IF, signal that has discrete frequency lines and a smaller bandwidth than the RF signal.

22. A computer program comprising instructions which, when the program is executed by a processor, for example by a processor of the calibration device, cause the processor to perform the method according to claim 21.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The above described aspects and implementations are explained in the following description of embodiments with respect to the enclosed drawings:

[0056] FIG. 1 shows a calibration device according to this disclosure.

[0057] FIG. 2 shows an exemplary calibration device with integrated mixer and pulse generator according to this disclosure.

[0058] FIG. 3 shows a first exemplary mixer of a calibration device according to this disclosure.

[0059] FIG. 4 shows a second exemplary mixer of a calibration device according to this disclosure

[0060] FIG. 5 shows spectrums of the RF signal, of a comb signal that results from an AND combination of the first LO signal and the second LO signal, and of the IF signal.

[0061] FIG. 6 shows a calibration setup according to this disclosure, which includes the calibration device and the signal generator.

[0062] FIG. 7 shows additional, optional components of an exemplary calibration device according to this disclosure.

[0063] FIGS. 8A and 8B show a hold gate of an exemplary calibration device according to this disclosure, and its effect on the IF signal output by the mixer.

[0064] FIG. 9 shows a method according to this disclosure for measuring an RF signal generator.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

[0065] FIG. 1 shows a calibration device 10 according to this disclosure. The calibration device 10 may be used to measure a RF signal generator 11. Together with the RF signal generator 11, the calibration device 10 may form a calibration setup, which may be used to calibrate a DUT.

[0066] The calibration device 10 comprises an input configured to receive an RF signal 12 of the RF signal generator 11, wherein the RF signal 12 has discrete frequency lines, for instance, may be established based on a comb signal. The RF signal frequency lines may be referred to as tones. This RF signal 12 may be referred to as RF calibration signal 12 in this disclosure, since it is output for the purpose of calibration, for example, in a calibration mode of the RF signal generator 11. The RF signal 12 may be a MCCW signal. The input of the calibration device 10 may be connected to an output of the RF signal generator 11 or to an input of the DUT (which is again connected to the RF signal generator 11) to obtain the RF signal 12.

[0067] The calibration device 10 further comprises a pulse generator 17, which is configured to generate a first LO signal 14 and a second LO signal 15, and to provide the first and the second LO signal 14, 15 to the mixer 13. The first and the second LO signal 14, 15 may be produced by a single clock signal (CLK) of the pulse generator 17, e.g., by deriving one LO signal from the other.

[0068] The calibration device 10 further comprises a mixer 13, which is configured to mix the RF signal 12 with the first LO signal 14 and the second LO signal 15, thereby obtaining an IF signal 16, which has discrete frequency lines and a smaller bandwidth than the RF signal 12. Accordingly, the RF signal 12 is down-converted or bandwidth compressed to the IF signal 16. Thus, the IF signal 16, or derivations of the IF signal 16 obtained by further processing the IF signal 16, having a bandwidth that allows measuring or analyzing without segmentation of the RF signal 12 or IF signal 16. The IF signal frequency lines may be referred to as tones, and each tone of the IF signal 16 may correspond to one of the frequency lines of the RF signal 12. The mixer 13 may logically combine the LO signals 14, 15 and the RF signal 12 to produce the IF signal 16.

[0069] FIG. 2 shows an exemplary calibration device 10, which comprises the mixer 13 specifically referred to as an AND mixer. The mixing of the RF signal 12 with the first LO signal 14 and the second LO signal 15 comprises a logical AND combination by the mixer 13 of the RF signal 12, the first LO signal 14, and the second LO signal 15. This also comprises logical AND combination of the first LO signal 14 and the second LO signal 15. The mixer 13 may process the signals directly by circuitry forming an AND-Gate to perform the AND combination.

[0070] FIG. 2 also shows that in the calibration device 10 the pulse generator 17, which is configured to generate the first LO signal 14 and the second LO signal 15 and to provide the first and second LO signal 14, 15 to the mixer 13, may be integrated with the mixer 13. Notably, the shown pulse generator 17 is an example, and various kinds of pulse generators 17 may be used in the calibration device 10. As shown, the pulse generator 17 and the mixer 13 may be integrated, for instance, on the same board or in the same chip.

[0071] The LO signals 14 and 15 may depend on each other, i.e., they may be generated by the same clock signal (CLK) of the pulse generator 17, and one may be derived from the other. For instance, the LO signals may be delayed inverses of each other. For example, the second LO signal 15 may be a negative and time-delayed copy of the first LO signal 14. This is illustrated in FIG. 3, which also shows that the AND combination of the first LO signal 14 and the second LO signal 15 results in a comb signal 30. The mixer 13 may effectively mix this comb signal 30 with the RF signal 12.

[0072] FIG. 2 shows further that the calibration device 10 may also comprise an amplifier 21, which may be also integrated with the mixer 13 and the pulse generator 17, and may amplify the IF signal 16 provided by the mixer 13. Other components, which are explained later, may additionally be integrated on the same board or chip.

[0073] The mixer 13 may generally be based on a Gilbert cell mixer architecture, but with modifications. The mixer 13 may have multiple stages, each stage comprising multiple transistors. Exemplary implementations are described below.

[0074] FIG. 3 shows in this respect a first exemplary implementation of the mixer 13. The mixer 13 of this example is composed of a first stage of transistors 31, 32 adapted to receive the RF signal 12 as an input, a second stage of transistors 33-36 connected to the first stage and adapted to receive the second LO signal 15 as an input, and a third stage of transistors 37-40 connected to the second stage and adapted to receive the first LO signal 14 as an input.

[0075] In the example, the first stage comprises a first transistor pair 31, 32, which is connected to a current source, wherein the first transistor pair 31, 32 is controlled by the RF signal 12 and is configured to provide a modulated current, which is modulated by the RF signal 12, to the second stage. As shown, the first transistor pair 31, 32 comprises a first transistor 31 and a second transistor 32, wherein opposite phases of the RF signal 12 are connected to control terminals of the first transistor 31 and the second transistor 32, respectively. Further, the input terminals of the first transistor 31 and the second transistor 32 are connected to each other and to the current source. The output terminals of the first transistor 31 and the second transistor 32 are connected to the second stage.

[0076] The second stage comprises a second transistor pair 33, 34 and a third transistor pair 35, 36, which are each connected to the first transistor pair 31, 32 and are each controlled by the second LO signal 15. The second transistor pair 33, 34 comprises a third transistor 33 and a fourth transistor 34, which are connected to each other by their input terminals. Opposite phases of the second LO signal 15 are connected to the control terminals of the third transistor 33 and the fourth transistor 34, respectively. The third transistor pair 35, 36 comprises a fifth transistor 35 and a sixth transistor 36, which are connected to each other by their input terminals. Opposite phases of the second LO signal 15 are connected to control terminals of the fifth transistor 35 and the sixth transistor 36, respectively. As shown, the input terminals of the third, fourth, fifth, and sixth transistor 33-36 are all connected to the first stage. In particular, the input terminals of the third transistor 33 and the fourth transistor 34 are connected to the output terminal of the first transistor 31, and the input terminals of the fifth transistor 35 and the sixth transistor 36 are connected to the output terminal of the second transistor 32. The output terminals of the third transistor 33 and the sixth transistor 36 are connected to the third stage. The output terminals of the fourth transistor 34 and the fifth transistor 35 are connected to a first supply voltage VCC.sub.2.

[0077] The third stage comprises a fourth transistor pair 37, 38 and a fifth transistor pair 39, 40, which are connected to the second transistor pair 33, 34 and the third transistor pair 35, 36 of the second stage, respectively. The fourth transistor pair 37, 38 comprises a seventh transistor 37 and an eighth transistor 38, which are connected to each other by their input terminals. Opposite phases of the first LO signal 14 are connected to control terminals of the seventh transistor 37 and the eighth transistor 38, respectively. The fifth transistor pair 39, 40 comprises a ninth transistor 39 and the tenth transistor 40, which are connected to each other by their input terminals. Opposite phases of the first LO signal 14 are connected to the control terminals of the ninth transistor 39 and the tenth transistor 40, respectively. The input terminals of the seventh, eighth, ninth, and tenth transistor 37-40 are all connected to the second stage. In particular, the input terminals of the seventh transistor 37 and the eighth transistor 38 are connected to the output terminal of the third transistor 33. The input terminals of the ninth transistor 39 and the tenth transistor 40 are connected to the output terminal of the sixth transistor 36. The output terminals of the seventh transistor 37 and the tenth transistor 40 are connected to the output of the mixer 13. The output terminals of the eighth transistor 38 and the ninth transistor 39 are connected to a second supply voltage VCC.sub.1.

[0078] Together, the second and the third stage of the mixer 13 are configured to mix the modulated current, which is provided by the first stage, with the second LO signal 15 and the first LO signal 14which is equivalent to mixing the RF signal 12 with the AND combination of the first LO signal 14 and the second LO signal 15, i.e., the comb signal 30thereby providing a pulse-modulated current as the IF signal 16 to the output of the mixer 13.

[0079] The connections of the transistors 34, 35, 38, and 39 to the respective supply voltages VCC.sub.1 and VCC.sub.2 may lead to a significant reduction of the RF-to-IF leakage in the mixer 13, and to a lower power consumption.

[0080] Notably the arrows indicated in FIG. 3 and FIG. 4, respectively, show current flows, which correspond to different switching states of the transistors in the second and third stage switched by the respective LO signals 15, 14 provided by the pulse generator 17.

[0081] FIG. 4 shows a second exemplary implementation of the mixer 13, which is in large parts similar to the first exemplary implementation shown in FIG. 3. Same elements in FIG. 3 and FIG. 4 are labelled with the same reference signs and are not repeatedly described.

[0082] In this example, the third stage further comprises a sixth transistor pair 41, 42 comprising an eleventh transistor 41 and a twelfth transistor 42, which are connected to each other by their control terminals. The control terminals of the eleventh transistor 41 and the twelfth transistor 42 are further connected to the first supply voltage VCC.sub.2. The output terminals of the eleventh transistor 41 and the twelfth transistor 42 are connected to the second supply voltage VCC.sub.1 and respectively to the output terminals of the eight transistor 38 and the ninth transistor 39 of the third stage. The input terminals of the eleventh transistor 41 and the twelfth transistor 42 are connected to the output terminals of the fourth transistor 34 and the fifth transistor 35, respectively.

[0083] The temperature differences may be minimized between the different transistors during operation of the mixer 13, due to an introduced asymmetry of the current flows indicated by the arrows. For example, the third transistor 33 and the fourth transistor 34 may have an operating temperature of 88 C. and 99 C., respectively, and the seventh transistor 37 and the eighth transistor 38 may have an operating temperature of 79 C. each during mixing the RF signal 12 with the LO signals 14, 15. The other transistors may behave similarly. Thus, an overall maximum temperature difference between transistors of different stages and pairs is 20 C. or lower. A difference of transistors of the same pair is limited to even 11 C. or lower.

[0084] In this disclosure, especially in the exemplary implementations of the mixer 13 shown in FIGS. 3 and 4, each transistor 31-40 may be a bipolar transistor or a FET. If a transistor is a bipolar transistor, then its input terminal is an emitter, its output terminal is a collector, and its control terminal is a base. If a transistor is a FET, its input terminal is a source, its output terminal is a drain, and its control terminal is a gate. Notably, input and output terminals of the transistors could be swapped and still work according to the solutions of this disclosure.

[0085] FIG. 5 shows a result of mixing the LO signals 15, 14 and the RF signal 12 in the mixer 13. FIG. 5 shows the RF signal 12 and the comb signal 30, which is the logical AND combination of the first LO signal 15 and the second LO signal 14. That is, the first LO signal 14 and the second LO signal 14 are selected such that the logical AND combination results in the comb signal 30. As shown in FIGS. 3 and 4, the second LO signal 15 may be the negative and time-delayed copy of the first LO signal 14.

[0086] The two LO signals 14 and 15 are particularly selected such that the comb signal 30 has equidistant frequency lines and has a higher bandwidth than the RF signal 12. The RF signal 12 may have an exemplary bandwidth of 8 GHz, while the comb signal 30 may have an exemplary bandwidth of 50 GHz. Each of the equidistant discrete frequency lines of the comb signal 30 is different to the discrete frequency lines of the RF signal 12 with regard to frequency. Generally, a discrete frequency line may correspond to a Dirac delta function, namely the respective narrow peaks associated with the Dirac delta functions.

[0087] The spectrum of the IF signal 16, which results from the mixing by the mixer 13, is also shown in FIG. 5. In this regard, FIG. 5 reveals that the wider bandwidth RF signal 12 provided by the signal generator 11 is fully represented by the IF signal 16 with the lower bandwidth. The lower bandwidth of the IF signal 16 can be processed at once without segmentation, while containing all the information in the broadband RF signal 12. The entire IF signal 12 and, therefore, the information encompassed by the entire RF signal 12 can be measured in a non-segmented manner, because the spectrum of the IF signal 16 is compressed in comparison to the RF signal 12, due to the mixing with the first LO signal 14 and the second LO signal 15. A compression ratio may be set depending on the frequencies of the RF signal 12 and the LO signals 14, 15 used.

[0088] In an example, the calibration device 10 comprises a user interface, via which a user is enabled to make settings of the calibration device 10. For instance, the user can be enabled to select the compression ratio or the frequencies of the signals. For instance, a frequency spacing of the discrete frequency lines of the comb signal 30 is selectable. The user may also select a certain operation mode of the calibration device 10 for performing the respective method of measuring the RF signal generator 11.

[0089] As shown in FIG. 5, each discrete frequency line of the RF signal 12 is associated with a corresponding discrete frequency line of the comb signal 30, thereby forming pairs. Each of the pairs has an internal frequency spacing f, 2f, 3f and so on, namely a frequency spacing between the discrete frequency lines of the RF signal 12 with respect to the corresponding discrete frequency line of the comb signal 30. The respective internal frequency spacing is illustrated due to the respective projection of the RF signal 12 within the spectrum of the comb signal 30 indicated by the dashed lines in FIG. 5. It becomes clear that the internal frequency spacing of each pair is different, as the internal frequency spacings increase linearly with increasing frequency, namely starting from f to Nf.

[0090] FIG. 6 shows a calibration setup according to this disclosure, wherein the calibration setup comprises the calibration device 10 and the RF signal generator 11, which is configured to output the RF signal 12 for the purpose of calibration. The RF (calibration) signal 12 may be established by the RF signal generator 11 based on a comb signal, for instance, in a calibration mode of the RF signal generator 11. For instance, the RF signal generator 11 may provide this RF signal 12 to a DUT 64, for example, via a RF device 63. The calibration device 10 receives the output RF signal 12 of the RF signal generator 11, wherein the RF signal 12 may be tapped at the RF device 63. Alternatively, the RF signal 12 may be tapped at an output connecter of the RF signal generator 11 directly. Alternatively, the RF signal 12 may be tapped at an input connecter of the DUT 64 that is connected with the signal generator 11, for instance via a cable or line. These different tap positions are indicated in FIG. 6 by dashed lines accordingly.

[0091] FIG. 6 also shows that the calibration device 10 may comprise a LNA 61 configured to amplify the RF signal 12 before providing it to the mixer 13. The LNA 61 may be adjustable, in order to adjust a signal strength of the RF signal 12 to the LO signals 15, 14. The LO signals 15, 14 are produced by the pulse generator 17, which may be operated based on a first clock signal 65 (CLK) received by the calibration device 10. The calibration device 10 may also comprise an amplifier to amplify the IF signal 16 provided by the mixer 13.

[0092] The calibration device 10 may also comprise or be connected to a processing unit, which may comprise an ADC 62. The ADC 62 may digitize the IF signal 16. The ADC 62 may have a low bandwidth. Generally, simplified components, like synthesizers and ADCs can be used in the processing unit, due to the reduced bandwidth of the IF signal 16, thereby reducing the overall costs of the calibration device 10 and calibration setup.

[0093] The calibration device 10 may also comprise an internal processor or a controller (not shown), which is configured to control the pulse generator 17 and/or the LNA 61, and/or the mixer 13.

[0094] The processor or processing unit may comprise circuitry configured to perform, conduct or initiate the various operations of the calibration device or processing unit described herein. The processor or processing unit may comprise hardware and/or may be controlled by software. The hardware may comprise analog circuitry or digital circuitry, or both analog and digital circuitry. The digital circuitry may comprise components such as application-specific integrated circuits (ASICs), FPGAs, digital signal processors (DSPs), or multi-purpose processors. The processor or processing unit may further comprise memory circuitry, which stores one or more instruction(s) that can be executed, in particular under control of the software. For instance, the memory circuitry may comprise a non-transitory storage medium storing executable software code which, when executed, causes the various operations of the calibration device 10 or processing unit described herein.

[0095] FIG. 7 shows an exemplary calibration device 10 according to this disclosure, which includes further optional components. Same elements in FIG. 7 and the previous figures are labelled with the same reference signs, and may not be described again to avoid redundancy.

[0096] For example, the calibration device 10 may comprise a first frequency divider 71 (e.g., a 2.sup.N divider with N=0 to 8) and a second frequency divider 72 (e.g., a 2.sup.M divider with M=0 to 4). The first frequency divider 71 is configured to receive the first clock signal 65 (CLK) input to the calibration device 10, and to convert the first clock signal 65 into a second clock signal 66. This second clock signal 66 is provided to the pulse generator 17, which is configured to generate the first LO signal 14 and the second LO signal 15 based on the second clock signal 66.

[0097] The first frequency divider 71 is further configured to provide the second clock signal 66 to the second frequency divider 72, and the second frequency divider 72 is configured to convert the second clock signal 66 into a third clock signal 70. This third clock signal 70 may be amplified by an amplifier 74 and an amplifier 75, and may be output by a clock output 76 from the calibration device 10. The third clock signal 70 may be further added to the IF signal 16. For example, the third clock signal 70 may be added by an adder 78 to the IF signal 16 that is provided by the mixer 13 (which may optionally be amplified before the adding), wherein the adding produces a modified IF signal 77.

[0098] The integrated frequency dividers 71, 72 may be used for a pilot tone generation, wherein the third clock signal 73 (including pulses or tones) may be used as pilot tones that are added to the IF signal 16 (which also include pulses or tones). The modified IF signal 77 may then be sampled, for instance, in the processing unit including the ADC 62, in order to reconstruct a phase of the second clock signal 66 provided by the first frequency divider 71, which is enabled by the added pilot tones.

[0099] The level or amplitude of the pilot tones (i.e., the tones of the third clock signal 70) may be adjustable, which may be achieved with the adjustable amplifier 74. This enables signal level matching to the (modified) IF signal 16 and/or to the ADC dynamic range. The divider ratios of the first frequency divider 71 and/or the second frequency divider 72 may be settable within a certain range. For example, the variable divider ratios may be used for pilot tone generation at different and/or multiple frequencies. Phase inaccuracies of the frequency dividers 71, 72 may be cancelled out, which may lead to a shorter setup and/or measurement time. The above-described enables the detection of absolute phase (not possible in conventional solutions without additional circuitry).

[0100] The calibration device 10 may further comprise a hold gate 73 connected to the output of the mixer 13. The hold gate 73 is configured to convert a current pulse of the IF signal 16 provided by the mixer 13 to a voltage, and to hold the voltage until the next current pulse of the IF signal 16 is output by the mixer 13. Thereby, the hold gate 73 may be configured to output an integrated IF signal 79, for example, a modulated voltage signal. As shown in FIG. 7, if the calibration device 10 includes the hold gate 73, the third clock signal 70 may be added by the adder 78 to the integrated IF signal 79 provided by the hold gate 73 (which could be amplified by an amplifier 79 before the adding), wherein the adding produces the modified IF signal 77.

[0101] The advantages of the hold gate 73 are shown in FIG. 8. As can be seen in FIG. 8 (a), the hold gate 73 may comprise a capacitor, which may be connected to the output of the mixer 13 and a supply voltage, respectively. Further, the hold gate 73 may comprise a switch connected in parallel to the capacitor. The switch may be controlled by the second clock signal 66.

[0102] In a conventional mixer, a current-voltage conversion is done with a resistor or a transimpedance amplifier, wherein the useful signal is very small to be further processed. The hold gate 73 (or hold circuit) of this disclosure provides an improvement in this respect, as it stores the current pulses from the mixer 13, i.e., of the IF signal 15 in the form of voltage, and then holds them, and then before the next current pulse comes, clears the stored voltage. This may correspond to an integrate and dump circuit. This may achieve a signal energy increase in the amount of the ratio of the hold time to the current pulse width. A simple way to realize this is to shift the reset clock for resetting the stored voltage by 90 to the second clock signal 66 that generates the pulses of the LO signals 15, 14 . . .

[0103] FIG. 8b shows signal voltages of the IF signal 16 (without hold gate 73) and the integrated IF signal 79 (with the hold gate 73), respectively. A clear gain can be observed.

[0104] FIG. 9 shows a method 90 according to this disclosure for measuring a RF signal generator 11. The method 90 may be performed by the calibration device 10, respectively, its mixer 13. The method 90 comprises a step 91 of receiving the RF signal 12 of the RF signal generator 11, and a step 92 of mixing the RF signal 12 with the first LO signal 14 and the second LO signal 15, wherein the IF signal 16 having the smaller bandwidth than the RF signal 12 is obtained. As already mentioned above, the RF signal 12 in this disclosure is generated and output by the RF signal generator 11 for the purpose of calibration, and may thus be referred to as a RF calibration signal. The RF signal 12 may be a MCCW signal or the like, as explained before.

[0105] In the claims as well as in the description of this disclosure, the word comprising does not exclude other elements or steps and the indefinite article a or an does not exclude a plurality. A single element may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

[0106] The present disclosure may reference quantities and numbers. Unless specifically stated, such quantities and numbers are not to be considered restrictive, but exemplary of the possible quantities or numbers associated with the present disclosure. Also in this regard, the present disclosure may use the term plurality to reference a quantity or number. In this regard, the term plurality is meant to be any number that is more than one.

[0107] The principles, representative embodiments, and modes of operation of the present disclosure have been described in the foregoing description. However, aspects of the present disclosure are not to be construed as limited to the particular embodiments disclosed. Further, the embodiments described herein are to be regarded as illustrative rather than restrictive.