METHOD FOR FORMING SEMICONDUCTOR DEVICE

Abstract

A method of forming a semiconductor device. A substrate having a fin structure is provided. A dummy gate is formed on the fin structure. A polymer block is formed adjacent to a corner between the dummy gate and the fin structure. The polymer block is subjected to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block. After subjecting the polymer block to the nitrogen plasma treatment, a seal layer is formed on the sidewall of the dummy gate and on the polymer block. An epitaxial layer is then grown on a source/drain region of the fin structure. The dummy gate is then replaced with a metal gate.

Claims

1. A method of forming a semiconductor device, comprising: providing a substrate having a fin structure; forming a dummy gate on the fin structure, wherein a polymer block is formed adjacent to a corner between the dummy gate and the fin structure; subjecting the polymer block to a nitrogen plasma treatment, thereby forming a nitridation layer in proximity to a sidewall of the dummy gate under the polymer block; after subjecting the polymer block to the nitrogen plasma treatment, forming a seal layer on the sidewall of the dummy gate and on the polymer block; growing an epitaxial layer on a source/drain region of the fin structure; and replacing the dummy gate with a metal gate.

2. The method according to claim 1, wherein the nitridation layer comprises a nitrided silicon oxide film.

3. The method according to claim 2, wherein the polymer block comprises a silicon oxide layer on the nitrided silicon oxide film.

4. The method according to claim 1, wherein the epitaxial layer comprises SiP.

5. The method according to claim 1, wherein the dummy gate is a dummy polysilicon gate.

6. The method according to claim 1, wherein the seal layer comprises a carbon-doped silicon oxynitride layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG. 1 to FIG. 6 are schematic diagrams showing a method for fabricating a semiconductor device according to an embodiment of the present invention, wherein FIG. 1 is a top view of the semiconductor device according to an embodiment of the present invention, and FIG. 2 to FIG. 6 are side perspective views of a semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION

[0023] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0024] Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0025] The present invention pertains to a semiconductor fin field effect transistor (FinFET) device and a manufacturing method thereof. As mentioned above, to form the FinFET device, a silicon layer on the surface of the substrate is patterned by etching to form a fin-shaped silicon structure, and then an insulating layer and dummy polysilicon gate are formed on the fin-shaped silicon structure. An ion implantation process and an anneal process may be performed to form the source/drain regions in the fin-shaped silicon structure. Subsequently, an epitaxial layer such as SiP is formed in the source/drain regions by using an epitaxial process. A replacement metal gate (RMG) process is then performed to replace the dummy polysilicon gate with a metal gate.

[0026] However, in the existing practice, when the dummy polysilicon gate is removed, the SiP epitaxial layer in the source/drain region may also be etched away, which results in hole defects in the source/drain region and reduction of yield. The present invention addresses this issue.

[0027] Please refer to FIG. 1 to FIG. 6, which are schematic diagrams of the manufacturing method of the semiconductor device 1 according to an embodiment of the present invention, wherein FIG. 1 is a top view of the semiconductor device 1 according to an embodiment of the present invention, FIG. 2 to FIG. 6 are side perspective views of the semiconductor device 1 according to an embodiment of the present invention.

[0028] As shown in FIG. 1 and FIG. 2, a substrate 100, for example, a semiconductor substrate is provided. A fin structure F, for example, a fin-like silicon structure is formed on the substrate 100. A gate dielectric layer 110 is then formed on the fin structure F. A dummy gate 120, for example, a dummy polysilicon gate is then formed on the gate dielectric layer 110. According to an embodiment of the present invention, the fin structure F is disposed above a trench isolation region SI.

[0029] At this point, a polymer block P, also known as fin corner oxide (FCO), is formed at the corner between the sidewall 120s of the dummy gate 120 and the fin structure F. The above-mentioned polymer block P may be mainly composed of silicon oxide formed by oxidation of residual silicon when the dummy polysilicon gate 120 is formed. Subsequently, during the removal step of the dummy gate 120, the etchant may etch the polymer block P and cause the SiP epitaxial layer in the source/drain region to be etched. A hole defect may be formed in the source/drain region.

[0030] As shown in FIG. 3, the polymer block P is subjected to a nitrogen plasma treatment NPT, nitrogen ions may penetrate through the polymer block P, and a nitride layer PN may be formed under the polymer block P and in proximity to the sidewall 120s of the dummy gate 120. According to an embodiment of the present invention, the nitridation layer PN includes a nitrided silicon oxide film. According to an embodiment of the present invention, the polymer block P may include a silicon oxide layer PO on the nitrided silicon oxide film.

[0031] As shown in FIG. 4, after the polymer block P is treated with nitrogen plasma, a sealing layer 130 is formed on the sidewall 120s of the dummy gate 120 and on the polymer block P. According to an embodiment of the present invention, the sealing layer 130 may include a carbon-doped silicon oxynitride (SiOCN) layer, but is not limited thereto.

[0032] As shown in FIG. 5, an epitaxial layer EP is then grown on a source/drain region 150 of the fin structure F. According to an embodiment of the present invention, the epitaxial layer EP may include SiP.

[0033] As shown in FIG. 6, an RMG process is performed to replace the dummy gate 120 with a metal gate 220. Since the above-mentioned RMG process is a well-known technology, its details will not be repeated. For example, the above-mentioned RMG process may include a dummy poly removal (DPR) step in which the dummy gate 120 is removed by etching. During the DPR step, the nitridation layer PN can resist etching, so the SiP epitaxial layer in the source/drain regions will not be etched away, and therefore no hole defects will be formed in the source/drain regions 150.

[0034] Structurally, it can be seen from FIG. 3 and FIG. 6 that a semiconductor device 1 of the present invention includes a substrate 100 having a fin structure F, a gate structure 220 covering the fin structure F, and a polymer block P at a corner between the gate structure 220 and the fin structure F, and a source/drain region 150 located on the fin structure F. The polymer block P includes a nitridation layer PN adjacent to a sidewall of the gate structure 220.

[0035] According to an embodiment of the present invention, as shown in FIG. 3, the nitridation layer PN includes a nitrided silicon oxide film. According to an embodiment of the present invention, the polymer block P includes a silicon oxide layer PO on the nitrided silicon oxide film.

[0036] According to an embodiment of the present invention, the gate structure 220 is a metal gate. According to an embodiment of the present invention, the source/drain region 150 includes a SiP epitaxial layer EP. According to an embodiment of the present invention, the fin structure F is disposed above a trench isolation region SI.

[0037] According to an embodiment of the present invention, the semiconductor device 1 further includes a seal layer 130 disposed on the sidewall of the gate structure 220 and on the polymer block P. According to an embodiment of the present invention, the seal layer 130 includes a carbon-doped silicon oxynitride layer.

[0038] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.