Abstract
Quantum computing systems require methods to control energies of qubits and couplers for quantum operations. Flux biasing of qubits and quantum couplers is provided for a superconducting quantum computer using single-flux-quantum (SFQ) technology. This method is applicable to a wide range of superconducting qubit structures and couplers, including transmons, fluxoniums, flux qubits, phase qubits and other superconducting qubits. This method enables arbitrary-amplitude time-varying flux biasing of qubits and couplers, due to a sequence of high-speed SFQ pulses. Several preferred embodiments are disclosed which provide high-fidelity control of fast single-qubit and multi-qubit operations.
Claims
1. A system for controlling a qubit having a qubit energy, comprising: a first circuit configured to receive at least one control signal, to generate at least one sequence of single-flux-quantum pulses, and to selectively integrate the sequence of single-flux-quantum pulses into an integrated magnetic flux in a loop in dependence on the at least one control signal; and a second circuit configured to determine at least one of the integrated magnetic flux, and a performance metric of a qubit coupled to the integrated magnetic flux, having an output.
2. The circuit according to claim 1, further comprising a third circuit configured to receive the output of the second circuit and to generate the at least one control signal.
3. The system according to claim 1, wherein the first circuit is a superconducting circuit configured to generate the at least one sequence of single flux quantum pulses from a Josephson junction at cryogenic temperatures.
4. The system according to claim 1, wherein the first circuit comprises a plurality of Josephson junctions, configured as to increase the integrated magnetic flux in the loop with a flux-on circuit, and to decrease the integrated magnetic flux in the loop with a flux-off circuit.
5. The system according to claim 1, wherein the first circuit comprises a pair of output ports configured to produce a first signal configured to increase the integrated magnetic flux and a second signal adapted to decrease the integrated magnetic flux.
6. The system according to claim 1, further comprising a qubit, whose state is represented by a phase and an amplitude a Bloch sphere, coupled to the integrated magnetic flux, wherein the phase and amplitude of the Bloch sphere are responsive to the integrated magnetic flux.
7. The system according to claim 5, wherein at least one of a microwave resonance, an energy, and a phase of the qubit is dependent on the integrated magnetic flux.
8. The system according to claim 1, further comprising a tunable qubit coupler for a qubit having at least one physical property tunable dependent on at least the integrated magnetic flux, wherein the integrated magnetic flux is coupled with the tunable qubit coupler to alter a property of the qubit.
9. The system according to claim 1, further comprising a switched qubit coupler configured to selectively control a presence and an absence of an interaction of a plurality of qubits.
10. The system according to claim 1, further comprising a frequency mixer and detector configured to receive an output of at least one qubit and to control the first circuit.
11. The system according to claim 1, wherein the qubit comprises a transmon qubit, and the first circuit is configured to, within a quantum calculation period of the qubit, define a first microwave resonant frequency of the qubit with the integrated magnetic flux, and subsequently define a second microwave resonant frequency of the qubit by changing the integrated magnetic flux, wherein the first microwave resonant frequency and the second microwave resonant frequency are different.
12. The system according to claim 1, wherein the first circuit further comprises a first input port configured to receive a reference frequency signal, a second input port configured to receive a microwave resonance signal from the qubit, and a comparing circuit configured to produce a comparison output configured to control the integrated magnetic flux to selectively change the integrated magnetic flux in response to the comparison output.
13. The system according to claim 1, wherein the first circuit is further configured to receive a signal representing a calculation state of the qubit, and control the first circuit dependent on the calculation state of the qubit.
14. The system according to claim 1, wherein the at least one sequence of single-flux-quantum pulses comprises a first sequence of single-flux-quantum pulses having a first amplitude, and a second sequence of single-flux-quantum pulses having a second amplitude.
15. The system according to claim 1, further comprising a superconducting digital circuit counter comprising Josephson junctions and being configured to count single-flux-quantum pulses and to determine whether a number of single-flux-quantum pulses has reached a target value representing a target integrated magnetic flux.
16. The system according to claim 1, further comprising a comparator configured to determine a relationship of the integrated magnetic flux to a target integrated magnetic flux.
17. The system according to claim 1, wherein the first circuit is configured to implement at least one of a frequency locked loop control with a detector configured to determine a relationship between a microwave frequency associated with the qubit and a reference microwave frequency.
18. A method for controlling a qubit having a qubit energy, comprising: generating at least one control signal dependent on at least one of an integrated magnetic flux, and a performance metric of a qubit coupled to the integrated magnetic flux; and integrating at least one sequence of single-flux-quantum pulses into the integrated magnetic flux in a loop selectively dependent on the at least one control signal.
19. The method according to claim 18, wherein a state of a qubit is represented by a phase and an amplitude a Bloch sphere, the qubit being coupled to the integrated magnetic flux, further comprising changing the phase and amplitude of the Bloch sphere responsive to changes of the integrated magnetic flux.
20. A control system for a transmon qubit, comprising: an inductive loop configured to integrate a series of single-flux-quantum pulses into an integrated magnetic flux; a coupling circuit configured to couple the integrated magnetic flux with the transmon qubit; a sensor configured to determine a resonance frequency of the transmon qubit; a control configured to control a value of the integrated magnetic flux dependent on the sensor output.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0288] FIG. 1 shows a SFQ flux biasing circuit.
[0289] FIG. 2 shows a SFQ flux biasing using chain of JTLs.
[0290] FIG. 3 shows a flux biasing using parallel JTLs.
[0291] FIG. 4 shows a simulation of flux biasing by adding or removing magnetic fluxons.
[0292] FIG. 5 shows an arbitrary-shape time-varying flux-biasing.
[0293] FIG. 6 shows a circuit for coarse flux biasing using flux pump.
[0294] FIG. 7 shows a combining coarse and fine tune biasing.
[0295] FIG. 8 shows a circuit to reset flux stored in the flux biasing circuit.
[0296] FIG. 9A shows a block diagram for single-qubit gate operation with time-variable flux biasing.
[0297] FIG. 9B shows a block diagram for single-qubit gate operation with time-and pulse rate-variable flux biasing.
[0298] FIG. 10A shows a block diagram for multi-qubit gate operation with time-variable flux biasing of qubits and couplers.
[0299] FIG. 10B shows a block diagram for multi-qubit gate operation with time-and pulse-rate-variable flux biasing of qubits and couplers.
[0300] FIG. 11 shows a single qubit operation combining SFQ pulses for single qubit control and flux biasing.
[0301] FIG. 12A shows a block diagram of a prototype SFQ flux bias circuit employing a counter.
[0302] FIG. 12B shows a block diagram of a prototype SFQ flux bias circuit employing feedback.
[0303] FIG. 12C shows a block diagram of a prototype SFQ flux bias circuit to produce net-zero flux bias pulses for fluxonium control.
[0304] FIG. 12D shows a block diagram of a prototype low-hardware-overhead SFQ flux bias circuit to produce net-zero flux bias pulses for fluxonium control.
[0305] FIG. 13 shows a schematic of an amplifying JTL.
[0306] FIGS. 14A-14B show a block diagram and circuit schematic of a relaxation oscillator flux pump.
[0307] FIG. 14C shows a graph of a simulation of operation of the relaxation oscillator where the dotted curve shows the voltage output, and the solid curve represents the total flux output.
[0308] FIG. 15 shows a block diagram of a programmable pulse counter.
[0309] FIG. 16A shows a top-level schematic of a prototype SFQ flux bias circuit.
[0310] FIG. 16B shows a schematic of the flux generating circuit from FIG. 16A.
[0311] FIG. 16C shows a schematic of the switch from FIG. 16B.
[0312] FIG. 16D shows a schematic of the synchronizer component of the switch from FIG. 16C.
[0313] FIG. 17 shows a circuit layout of a prototype SFQ flux bias circuit.
[0314] FIG. 18 shows a simulation of operation of the prototype SFQ flux bias circuit.
[0315] FIG. 19 shows experimental measurements of the prototype SFQ bias circuit.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0316] FIG. 1 shows a conceptual diagram of a preferred embodiment of a flux biasing circuit. This diagram comprises the flux biasing circuit itself, which generates a time-variable magnetic flux, inductively coupled to a superconducting qubit, or a superconducting coupler between two qubits (Qubit/Coupler). The inductive coupling comprises a transformer, generally without a magnetic core, with a primary inductance Lin, a secondary inductance Lout, and a mutual inductance M. The transformer lines preferably comprise a superconducting material, such as niobium or aluminum, at the cryogenic temperature of operation, so that they are essentially lossless with magnetic flux that is quantized as a multiple of the fluxon Po. Both the flux-biasing circuit and the qubit/coupler comprise a plurality of Josephson junctions. The flux biasing circuit and the qubit/coupler may be integrated circuits, which may be fabricated on the same chip, or alternatively they may be fabricated on separate chips that are coupled inductively in a flip-chip geometry.
[0317] FIG. 1 also comprises two digital SFQ generating circuits, which may be nominally identical, but which are connected to the primary inductance Lin with opposite polarities, so as to correspond to magnetic flux of opposite signs.
[0318] This conceptual diagram is further refined in FIG. 2 to include Josephson Transmission Lines (JTLs) in each of the two channels. The JTLs are used to transport and shape the SFQ pulses, and may also be configured in parallel to achieve current gain, as shown in FIG. 3. While the JTL itself propagates an SFQ pulse in series, the parallel output configuration functions as a digital pulse multiplier, increasing the total flux by a factor of n of the parallel unit cells.
[0319] FIGS. 4 and 5 show two examples of time-varying flux profiles that may be generated by such positive and negative fluxon generators. FIG. 4 shows a simple profile that rises linearly, remains constant, and then ramps down again, while FIG. 5 represents an arbitrary variation in time. The time axis is not specified in either case, but the characteristic ramp time can be anywhere from 10 ps to 1 ns or longer, since the individual SFQ pulses have intrinsic pulsewidth of order 1-2 ps. This may be compared to the period of a qubit resonance, which may be of order 100 ps. So, the flux bias variation may occur either within a single resonance period, or over a plurality of resonance periods. Note also that while the SFQ pulses comprise very high frequency components, the circuits can be configured to filter out the highest frequency components to yield a smooth flux profile. Such a smooth flux profile will also not excite quasiparticles in the quantum portion of the circuit, which would tend to reduce quantum coherence times.
[0320] A further embodiment of the flux biasing circuit is shown in FIGS. 6 and 7, and comprises a two-stage coarse and fine control. The coarse control may comprise a flux pump that multiplies the flux by a known factor. One embodiment of a flux pump is a SQUID relaxation oscillator, shown in FIGS. 14A-14C and described further below. The two-stage flux bias control permits high precision, high speed, and large dynamic range.
[0321] A further refinement is shown in FIG. 8, which resets the flux in the control loop to zero. This is achieved using a SQUID in series with the inductive storage loop. When a control SFQ pulse drives the SQUID above its critical current into its normal state, the loop becomes resistive, and the stored flux of either sign quickly escapes the loop.
[0322] The block diagram in FIG. 9A shows the various ways that SFQ digital control may be applied to qubit control. In a preferred embodiment, all of these blocks comprise superconducting circuits located at cryogenic temperatures. The block on the top is the Central Control Unit, which provides the centralized source for clock pulses for synchronization and sequential timing. These clock pulses are also SFQ pulses. SFQ control signals include flux bias for the qubit, but also include other SFQ pulse sequences that can be used to induce quantum transitions, for example. These include the blocks labeled SFQ Pattern Generation, SFQ Amplitude Control, and SFQ-Qubit Coupler. These are similar to prior-art circuits for SFQ control, but here they may be properly synchronized with the flux biasing circuits for improved control.
[0323] The block diagram on FIG. 9B shows another embodiment, in which the qubit is controlled exclusively using flux bias pulses (FBP). The shape of the pulses is controlled using blocks SFQ FBP Amplitude Control and SFQ FBP Ramp Control. Specific control functions for these blocks are generated by SFQ Flux Bias (FBP) Pattern Generation block.
[0324] FIGS. 10A and 10B take this one step further for two coupled qubits and beyond. The two tunable qubits linked by a coupler, shown in the center of the figure, comprise the superconducting quantum circuit itself. These may be linked to other qubits and couplers, as indicated on the bottom. The completely synchronized digital control at all levels enables new opportunities for precision control while minimizing decoherence of the quantum operation.
[0325] An illustrative example of these two types of SFQ control is shown in FIG. 11. The pulses at the bottom (corresponding to opposite polarities) provide a flux bias that first tunes, then detunes, the energy of the qubit, shown in the middle. The pulses on top represent the resonant pulse train coupled to induce a transition of the qubit, during the time that its energy is properly tuned.
[0326] In addition to presenting the concept and method of superconducting digital flux bias of qubits, portions of a preferred embodiment have been designed, simulated, fabricated, and demonstrated experimentally.
[0327] FIG. 12A shows a block diagram of a flux bias control circuit similar to that shown in FIG. 3. This circuit includes positive and negative flux generating circuits, each with an amplifying JTL (AJTL), a switch, and a counter. This also includes a single coupling inductor L1 that couples magnetic flux to a qubit or coupler, labeled Q, and a superconducting clock source that sets the generation rate of SFQ pulses.
[0328] Alternately, as shown in FIG. 12B, a flux bias control circuit similar to that shown in FIG. 3 is provided with a feedback input, based on a sensor measurement or a performance indicator dependent on the output of the qubit. This circuit also includes positive and negative flux generating circuits, each with an amplifying JTL (AJTL), a switch, a comparator for determining whether the magnetic flux is above or below the target value or setpoint, supplied by a controller, and an inverter for driving the opposite phase (Flux on vs. Flux off). The comparator may also have intrinsic complementary outputs. This also includes the single coupling inductor L1 that couples magnetic flux to the qubit or coupler, labeled Q, and a superconducting clock source that sets the generation rate of SFQ pulses. Not shown in 12B is an option for suppressing all pulses, for example when the sensor output or performance indicator demonstrates a sufficient proximity to the target that tuning is not required. Typically, this is produced by a digital control, a deadband control circuit, or hysteresis circuit, which advantageously may be implemented by adjusting the setpoint. The null tuning zone may be implemented by suppression of pulses or by presence of both Flux on and Flux off pulses. The former case reduces power dissipation. Typically, the comparator is implemented in digital logic, though an analog implementation is possible, so long as power dissipation is maintained at a low level. The comparator may be digital in amplitude and analog in time, and operate on phase relationships. For example, if the comparator is clocked, the output may be selectively dependent on whether one input precedes the clock and the other succeeds the clock. If both precede or succeed, then the comparator may produce a null output.
[0329] FIG. 12C shows an example of an SFQ circuit to produce net-zero flux bias pulse which can be used for fluxonium control within a single qubit cycle (Larmor period). The net-zero pulse consists of two opposite polarity triangular flux bias pulses applied to the qubit with interval t.sub.Z. The amplitude of each pulse is programmed using an SFQ counter, the carry signal of this counter triggers the polarity switch implemented using the toggle flip-flop (TFF). Nondestructive readout switches (ND) are used to control the beginning and completion of pulse generation.
[0330] FIG. 12D shows an example of a simplified SFQ circuit to produce net-zero flux bias pulse similar to one described in FIG. 12C. The complexity reduction is achieved by using a dc/SFQ converter which generates control SFQ pulses to set the interval t.sub.Z between the opposite polarity flux bias pulses. Although this scheme is simpler on the SFQ side, it requires a control signal for the dc/SFQ converter which can be generated by cryoCMOS or conventional room-temperature electronics.
[0331] The AJTL can be a parallel JTL with 6 JTL stages in parallel, as shown in FIG. 13. Alternatively, a flux pump based on a relaxation oscillator (ROS) could be used, as shown in FIGS. 14A-14C. FIG. 14A shows the block diagram of the full flux bias circuit with two ROS circuits for both positive and negative flux. FIG. 14B shows the schematic of ROS, built around a hysteretic Josephson junction Jm2. When this junction switches, it remains in the voltage stage for an extended period of time, typically generating hundreds of fluxons or more. A simulation of operation of the ROS is shown in FIG. 14C, where the oscillating dotted curve shows the voltage output, and the solid curve with a long tail represents the total flux output. This ROS flux bias circuit would be particularly useful for the coarse channel of a two-stage flux bias circuit, as suggested in FIGS. 6 and 7.
[0332] The counter can be a fixed frequency divider, based on a simple chain of N T-flip-flops (TFFs), well known in the prior art, which generates 2.sup.N SFQ pulses. Alternatively, a programmable counter such as that in FIG. 15 can be used, which can generate an arbitrary programmable number of SFQ pulses up to 2.sup.N. This also comprises a series of N TFFs (where N=6 in FIG. 14C), linked to a serially programmable non-destructive readout (NDRO) register.
[0333] Portions of the schematic hierarchy for a prototype flux bias control circuit based on FIGS. 12A-12D are shown in FIGS. 16A, 16B, 16C, and 16D. FIG. 16A shows the components of the overall bipolar flux control circuit, including the positive and negative flux channels (Flux ON and Flux OFF), two identical flux bias drivers (FB_DRV), a synchronizing clock generator with a splitter for clock distribution, and an output flux bias inductor LFB. This output inductor would couple flux to a qubit or coupler, but the quantum circuit is not included in this prototype demonstration circuit.
[0334] FIG. 16B provides a more detailed schematic of the flux bias driver FB_DRV, including a switch, a 16-bit counter, and an amplifying JTL, as shown in the blocks in FIG. 11. The switch is further expanded in FIG. 16C, comprising a synchronizer circuit SYNC and a storage register NDRO. Finally in FIG. 16D, the SYNC circuit is shown to comprise two D-flip-flops (DFF) that are well known in the prior art.
[0335] The circuits of FIGS. 16A-16D were laid out on chip using a standard integrated circuit design tool, and parts of this chip layout are shown in FIG. 17. This includes the Flux on and Flux off Bias Drivers, with components counter 171 (x16), switch 172, and JTL current amplifier 173.
[0336] The operation of the circuit in FIGS. 16A-16D was simulated, and several inputs and outputs are shown in FIG. 18. The plot on top shows several periods of the output current (and hence the flux bias) being ramped up and down. Below this is the clock signal, the alternating flux pulses from the left and right sides (positive and negative flux), and the trigger pulses for the two sides.
[0337] A chip based on the layout of FIG. 17 was fabricated using niobium Josephson junction technology, cooled to about 4 K, below the superconducting critical temperature, and tested. Preliminary results are shown in FIG. 19, which shows the clock inputs, the flux pump inputs, and a magnetic flux output as measured by a DC SQUID. Although this was a preliminary low-frequency test, the circuit demonstrated the expected functionality.
[0338] Similar superconducting circuits would be expected to exhibit similar performance at high speed, at reduced cryogenic temperatures in the mK range, with flux bias linked to a superconducting qubit or inter-qubit coupler.
