CIRCUIT FOR DOWNLINK/UPLINK OPERATIONAL MODE SWITCHING IN A TDD WIRELESS COMMUNICATION SYSTEM

Abstract

A circuit for downlink/uplink operational mode switching in a TDD wireless communication system comprises a field-effect transistor operatively connected to a power amplifier on the downlink path of a RF front-end apparatus in a TDD wireless communication system, a first voltage generator connected to a large-value first resistor, a second voltage generator connected to a second resistor, a large-value hold capacitor, and a sample-and-hold circuit configured to be switched between a reception configuration, wherein the first voltage generator is connected to the gate of the field-effect transistor and the large-value capacitor is connected to the first voltage generator through the first resistor, and a transmission configuration, wherein the gate of the field-effect transistor is connected to the hold capacitor and the hold capacitor is connected to the second voltage generator through the second resistor.

Claims

1) A circuit (C) for downlink/uplink operational mode switching in a TDD wireless communication system, comprising at least a field-effect transistor (RF FET) operatively connected to a power amplifier (PA) on the downlink path (DL) of a RF front-end apparatus in the TDD wireless communication system, the circuit comprising: a first voltage generator (Vgs.sub.OFF) connected to at least a large-value first resistor (R.sub.hold), a second voltage generator (V.sub.Gate) connected to a second resistor (R.sub.Gate); at least a large-value hold capacitor (C.sub.hold); and a sample-and-hold circuit configured to be switched between a reception (Rx) configuration, wherein said first voltage generator (Vgs.sub.OFF) is connected to the gate (G) of said field-effect transistor (RF FET) and said large-value capacitor (C.sub.hold) is connected to said first voltage generator (Vgs.sub.OFF) through said first resistor (R.sub.hold), and a transmission (Tx) configuration, and the gate (G) of said field-effect transistor (RF FET) is connected to said hold capacitor (C.sub.hold) and said hold capacitor (C.sub.hold) is connected to said second voltage generator (V.sub.Gate) through said second resistor (R.sub.Gate).

2) The circuit (C) according to claim 1, wherein said sample-and-hold circuit comprises a first electronic switch (SW1) connected to the gate (G) of the field-effect transistor (RF FET) and configured to be connected to said first voltage generator (VgsOFF) in said reception configuration and to said hold capacitor (C.sub.hold) in said transmission configuration.

3) The circuit (C) according to claim 2, wherein said sample-and-hold circuit comprises a second electronic switch (SW2) connected to said hold capacitor (C.sub.hold) and configured to be connected to said first voltage generator (Vgs.sub.OFF) through said first resistor (R.sub.hold) in said reception configuration and to said second voltage generator (V.sub.Gate) through said second resistor (R.sub.Gate) in said transmission configuration.

4) The circuit (C) according to claim 1, wherein said first voltage generator (Vgs.sub.OFF) is maintained to a constant value lower than a gate-source threshold voltage (Vgs.sub.th) of said field-effect transistor (RF FET).

5) The circuit (C) according to claim 1, wherein said hold capacitor (C.sub.hold) and said first resistor (R.sub.hold) are dimensioned by minimizing the variation (V.sub.ripple) of capacitor voltage value (V.sub.chold) overt time.

6) The circuit (C) according to claim 1, wherein said hold capacitor (C.sub.hold) and said first resistor (R.sub.hold) are dimensioned by maintaining the hold capacitor (C.sub.hold) voltage value (V.sub.chold) as closer as possible to gate-source voltage steady-state value (V.sub.gs_ss), which is defined as the voltage upper limit reached when the system is working in Tx configuration for an infinite period of time.

7) The circuit (C) according to claim 1, wherein said hold capacitor (C.sub.how and said first resistor (R.sub.hold) are dimensioned by minimizing the following equation, that describes the discharge phase of said hold capacitor (C.sub.hold) in said reception (Rx) configuration:
V.sub.ripple=(V.sub.chold−V.sub.gsOFF)*e.sup.−t.sup.UL.sup./(R.sup.hold.sup.*C.sup.hold.sup.) wherein: V.sub.ripple is the variation of said hold capacitor (C.sub.hold) voltage value (V.sub.chold); V.sub.chold is the hold capacitor (C.sub.hold) voltage value; Vgs.sub.OFF is the voltage value of said first voltage generator; t.sub.UL is the maximum duration of the UL period; R.sub.hold is the value of said first hold resistor; and C.sub.hold is the value of said hold capacitor.

8) The circuit according to claim 1, wherein said hold capacitor (C.sub.hold) and said first resistor (R.sub.hold) are dimensioned by minimizing the following equation, describing the charge phase of said hold capacitor (C.sub.holdh) during said transmission configuration:
V.sub.ripple=(V.sub.gs_SS−V.sub.chold)*(1−e.sup.−t.sup.DL.sup./(R.sup.gate.sup.*C.sup.hold.sup.)) wherein: V.sub.ripple is the variation of said hold capacitor (C.sub.hold) voltage value (V.sub.chold); V.sub.gs_SS is the to V.sub.gs steady-state value, which is defined as the voltage upper limit reached when the system is working in transmission configuration for an infinite period of time; V.sub.chold is the hold capacitor (C.sub.hold) voltage value, taken at the beginning of the downlink period; t.sub.DL is the minimum duration of the downlink period; R.sub.hold is the value of said first hold resistor; and C.sub.hold is the value of said hold capacitor.

9) A TDD wireless communication system (S), comprising at least downlink path (DL PATH) provided with at least a power amplifier (PA), at least an uplink path (UL PATH) provided with at least a low-noise amplifier (LNA), and at least an antenna (ANT) connected to said downlink path (DL PATH) and to said uplink path (UL PATH), wherein the TDD wireless communication system comprising: the circuit (C) for downlink/uplink operational mode switching according to claim 1, wherein said circuit (C) is operatively interposed between said power amplifier (PA) and said antenna (ANT), and at least an RF switch (RF SWITCH) placed in said uplink path (UL PATH) and connected to said circuit (C), wherein said RF switch is configured to be switched between said reception (Rx) configuration, wherein said at least an RF switch (RF SWITCH) is connected to said low-noise amplifier (LNA), and a transmission (Tx) configuration, wherein said at least an RF switch (RF SWITCH) is disconnected from said low-noise amplifier (LNA).

10) The circuit (C) according to claim 7, wherein t.sub.UL is the maximum duration of the UL period in the 3GPP standard for TDD applications.

11) The circuit according to claim 8, wherein t.sub.DL is the minimum duration of the downlink period in the 3GPP standard for TDD applications.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Other characteristics and advantages of the present invention will become better evident from the description of a preferred, but not exclusive embodiments of a circuit for downlink/uplink operational mode switching in a TDD wireless communication system, illustrated by way of an indicative but non-limiting example in the accompanying Figures, in which:

[0022] FIG. 1 shows a high-level standard TDD RF front end designed with a high-isolation RF switch at the antenna port, according to a known solution;

[0023] FIG. 2 illustrates a tracking thermal device according to a known solution;

[0024] FIG. 3 shows a high-level standard TDD RF front-end designed with a high-isolation RF switch at the antenna port, according to the invention;

[0025] FIG. 4 is a high-level electrical scheme of the switching circuit for RF LDMOS activation/deactivation, in the Rx operation mode configuration;

[0026] FIG. 5 shows an equivalent circuit in the Rx operational mode configuration;

[0027] FIG. 6 is a high-level electrical scheme of the switch circuit for RF LDMOS activation/deactivation, in the Tx operational mode configuration;

[0028] FIG. 7 shows an equivalent circuit in the Tx operational mode configuration.

EMBODIMENTS THE INVENTION

[0029] With particular reference to such illustrations, globally indicated with reference C is a circuit for downlink/uplink operational mode switching in a TDD wireless communication system.

[0030] The circuit C according to the invention allows to remove in a high-level TDD RF front end the RF switch at the antenna port and place it in the UL path before LNA, as shown in FIG. 3, hence addressing all issues of the known solutions.

[0031] Particularly, the circuit C is designed to act on the power amplifier LDMOS FET Gate voltage, while the Drain voltage is maintained constant.

[0032] From a high-level viewpoint, the circuit C according to the invention comprises: [0033] a voltage generator for setting the quiescent Drain current of the power amplifier LDMOS; [0034] a large-value resistor connected in series to the voltage generator; [0035] a sample-and-hold circuit comprising two analog switches driven by the synchronism signal of the TDD standard and a hold capacitor.

[0036] This circuit C allows for LDMOS power amplifier PA complete shut down in a very limited time interval, even if the embedded thermal tracking device needs a high resistor in series at the gate port of LDMOS for its correct functioning.

[0037] The resistor limits the current feeding the Gate port to change the LDMOS status (i.e. switching from on to off and vice versa), hence increasing the activation/deactivation time exceeding 3GPP standard's limits.

[0038] Moreover, a long commutation period potentially causes the reactive parasite effects of surrounding circuit components to be quite heavy, resulting in larger damped oscillations of the Drain current (whose module could be much larger than the maximum LDMOS current).

[0039] Focusing on a TDD scenario, RF LDMOS used to realize the power amplifier PA needs to be active only during Tx phase (DL period). One option to increase overall system efficiency, while removing possible source of thermal noise at the output of the power amplifier PA, is to turn off the RF LDMOS during RX phase (UL phase) by minimizing quiescent current, I.sub.DQ.

[0040] The challenge is to realize it using RF FET equipped with thermal tracking devices while keeping transitions latency from TX to RX phases lower than 1 μs, as required by 3GPP standard.

[0041] The invention proposed realizes the circuit C to address the issue above, its high-level electrical representation is shown in FIG. 4 and FIG. 6 for Rx and Tx operating mode, respectively.

[0042] The circuit C comprises at least a field-effect transistor RF FET operatively connected to a power amplifier PA on the downlink path (DL) of a RF front-end apparatus in a TDD wireless communication system.

[0043] Furthermore, the circuit C comprises: [0044] a first voltage generator Vgs.sub.OFF connected to at least a large-value first resistor R.sub.hold, [0045] a second voltage generator V.sub.Gate connected to a second resistor R.sub.Gate; [0046] at least a large-value hold capacitor C.sub.hold, [0047] a sample-and-hold circuit.

[0048] Particularly, the sample-and-hold circuit is configured to be switched between: [0049] a reception (Rx) configuration, wherein the first voltage generator Vgs.sub.OFF is connected to the gate G of the field-effect transistor RF FET and the large-value capacitor C.sub.hold is connected to the first voltage generator Vgs.sub.OFF through the first resistor R.sub.hold, and [0050] a transmission (Tx) configuration, wherein the gate (G) of the field-effect transistor RF FET is connected to the hold capacitor C.sub.hold and the hold capacitor C.sub.hold is connected to the second voltage generator V.sub.Gate through the second resistor R.sub.Gate.

[0051] According to preferred embodiment of the circuit C, the sample-and-hold circuit comprises a first electronic switch SW1 connected to the gate G of the field-effect transistor RF FET) and configured to be connected to the first voltage generator Vgs.sub.OFF in the reception configuration and to the hold capacitor C.sub.hold in the transmission configuration.

[0052] Furthermore, the sample-and-hold circuit comprises a second electronic switch SW2 connected to the hold capacitor C.sub.hold and configured to be connected to the first voltage generator Vgs.sub.OFF through the first resistor R.sub.hold in the reception configuration and to the second voltage generator V.sub.Gate through the second resistor R.sub.Gate in the transmission configuration.

[0053] Particularly, during the TDD RX phase (FIG. 4) the Gate G of the field-effect transistor RF FET is connected to the first voltage generator Vgs.sub.OFF through the first electronic switch SW1 driven by the TDD Synchronism Signal (TDD CRTL).

[0054] The first voltage generator VgsOFF is maintained to a constant value lower than the gate-source threshold voltage Vgs.sub.th of the field-effect transistor RF FET, which is defined as the voltage level corresponding to the field-effect transistor RF FET to be active (i.e. small amount of current flowing from Drain to Source).

[0055] In these conditions the field-effect transistor RF FET Drain current, I.sub.d, is close to zero.

[0056] The second electrical switch SW2 connects the large-value capacitor C.sub.hold to the first voltage generator Vgs.sub.OFF through the large-value first resistor R.sub.hold (hold resistor).

[0057] The first resistor R.sub.hold allows controlling the discharge time of the hold capacitor C.sub.hold that results several orders of magnitude larger that TDD frame period. In this way, V.sub.chold=Vgs.sub.ON is almost constant over entire RX phase when system is stable (i.e. out of transient initial phase), wherein V.sub.chold is voltage value over the hold capacitor C.sub.hold.

[0058] Advantageously, the presence of the first (hold) resistor R.sub.hold assures that even when the system is not fed by any signal (no TDD CTRL to pilot the sample-and-hold circuit) the circuit C will reach idle conditions in a defined amount of time, i.e. when the hold capacitor C.sub.hold completes its discharge phase, and the system does not remain in the last active state (either Tx or Rx).

[0059] During TX phase (see FIG. 6) the Gate of the field-effect transistor RF FET is connected to the large-value hold capacitor C.sub.hold through the first electronic switch SW1 driven by TDD Synchronism Signal (TDD CRTL). The second electrical switch SW2 connects the hold capacitor C.sub.hold to the second voltage generator, V.sub.Gate, through the second resistor, R.sub.Gate, of the proper size.

[0060] Particularly, the second voltage generator V.sub.Gate and the second resistor R.sub.Gate are connected in series and behaves as an equivalent current generator, allowing the transistor RF FET quiescent current, I.sub.D, to be kept constant over temperature.

[0061] To realize a proper dimensioning of the hold capacitor C.sub.hold and of the first hold resistor R.sub.hold, the first condition to be met is that the variation of capacitor voltage value V.sub.chold overt time, defined as V.sub.ripple, should be minimized. At the same time, the capacitor voltage value V.sub.chold should be as closer as possible to V.sub.gs stady-state value, V.sub.gs_SS, which is defined as the voltage upper limit reached when the system is working in Tx configuration for an infinite period of time.

[0062] The voltage variation V.sub.ripple is computed through the equation that describes the discharge phase of the hold capacitor C.sub.hold when in Rx operating configuration. In this case, the sample-and-hold circuit realizes a configuration equivalent to the one shown in FIG. 5, and the voltage variation V.sub.ripple is defined by:

V.sub.ripple=(V.sub.chold−V.sub.gsOFF)*e.sup.−t.sup.UL.sup./(R.sup.hold.sup.*C.sup.hold.sup.)

where t.sub.UL is the maximum duration of the UL period in the 3GPP standard for TDD applications, i.e. worst-case condition, and V.sub.chold is the value taken at the beginning of the UL period.

[0063] Given V.sub.chold and Vgs.sub.OFF, the aim is to minimize the voltage variation V.sub.ripple for an optimized choice of the hold capacitor C.sub.hold and of the hold resistor R.sub.hold.

[0064] Preferably, the hold capacitor C.sub.hold should take a much-larger value (e.g. 10.sup.5 times more) than the transistor RF FET inherent input capacity, to disregard the parasite effects that may take place during the commutation phase. As described above, the voltage variation V.sub.ripple should also meet a second requirement, hence the hold capacitor C.sub.hold and the first resistor R.sub.hold should be optimized to minimize the equation below, describing the charge phase of the hold capacitor C.sub.hold during the transmission (Tx) configuration:

V.sub.ripple=(V.sub.gs_SS−V.sub.chold)*(1−e−.sup.t.sup.DL.sup./(R.sup.gate.sup.*C.sup.hold.sup.))

where t.sub.DL is the minimum duration of the DL period in the 3GPP standard for TDD applications, and V.sub.chold is the voltage value taken at the beginning of the DL period.

[0065] If V.sub.chold is close to V.sub.gs_SS, then the quiescent current actually drown by RF FET is very close to the nominal expected I.sub.q.

[0066] In the transmission configuration, the sample-and-hold circuit realizes a configuration equivalent to the one shown in FIG. 7.

[0067] Considering the circuit C layout and functioning principle explained above, during the time intervals when the transistor RF FET is supposed to be ON (i.e. TX periods), the Gate measures a low dynamic impedance due to the large-value capacitor, C.sub.hold, connected in parallel.

[0068] Similarly, during the time intervals when the transistor RF FET is supposed to be OFF (i.e. RX periods), the Gate still measures a low dynamic impedance, this time due to the connection to the first voltage generator, V.sub.gsOFF.

[0069] In this way, transistor RF FET switching latency is short enough to comply with the limits defined by the standard, while assuring a precise thermal compensation over temperature of the quiescent current, I.sub.D.

[0070] Moreover, achieving a short commutation latency between Tx/Rx phases minimizes the potential damaging impacts of reactive parasite effects of surrounding circuit components.

[0071] The TDD wireless communication system S according to the invention, showed in FIG. 3, comprises a downlink path DL PATH provided with at least a power amplifier PA, at least an uplink path UL PATH provided with at least a low-noise amplifier LNA, and at least an antenna ANT connected to the downlink path DL PATH and to the uplink path UL PATH.

[0072] The system S further comprises the circuit C for downlink/uplink operational mode switching as disclosed above, wherein the circuit C is operatively interposed between said power amplifier PA and said antenna ANT.

[0073] Furthermore, the system S comprises an RF switch placed in the uplink path UL PATH and connected to the circuit C, configured to be switched between the reception (Rx) configuration, wherein it is connected to said low-noise amplifier LNA, and the transmission (Tx) configuration, wherein it is disconnected from said low-noise amplifier LNA.

[0074] Particularly, in the transmission (Tx) configuration, the RF switch is connected to a resistor R.

[0075] With respect to the know system, the benefits introduced in the new system S by the new circuit C proposed allows then to remove the RF switch at the antenna port and place it in the UL path before LNA, as shown in FIG. 3.

[0076] Therefore, the circuit according to the invention allows to comply with stringent time requirements defined by the 3GPP standard for TDD operational mode switching latency.

[0077] The invention proposed realizes a solution a solution to control an LDMOS transistor equipped with an embedded thermal tracking device used in RF front end circuit to realize PA stages for TDD applications.

[0078] Particularly, the circuit according to the invention allows to reduce the overall cost of the used components. Requirements for RF switch isolation can be reduced thanks to the introduction of the invention proposed that allows transistor RF FET to be completely turned off.

[0079] Furthermore, the circuit according to the invention allows to reduce the loss in the DL path efficiency. Particularly, the introduction of the invention proposed avoids the introduction of an RF switch after the PA in the DL path, hence reducing DL I.L. and increasing overall system efficiency.

[0080] The circuit according to the invention further lets to improve the system reliability. The RF switch is placed on the UL path hence dealing with lower power levels and increasing system reliability.

[0081] Furthermore, the circuit according to the invention allows to reduce the power consumption. Particularly, the RF FET transistor is completely turned off in Rx phase, with quiescent current maintained almost zero.