Active inductive simulator and impedance multiplier

Abstract

A tunable grounded positive and negative active inductor simulator and impedance multiplier circuit and a method for implementing the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit are described. The circuit includes one second generation voltage-mode conveyor circuit (VCII+), a voltage source configured to generate an output current, a first impedance, a second impedance and an operational transconductance amplifier OTA. The first impedance is connected between the voltage source and the positive VCII+ input terminal, Y. The second impedance is connected between the second output terminal and a ground terminal. The OTA is configured to have a transconductance gain. The circuit is configured to be tuned by a selection of values for the first and second impedances.

Claims

1. A tunable inductor simulator and impedance multiplier circuit, comprising: only one second-generation voltage-mode conveyor (VCII+), only one operational transconductance amplifier (OTA) and only two passive elements selected from the group consisting of a first impedance Z.sub.1 and a second impedance Z.sub.2; wherein the one second generation voltage-mode conveyor circuit (VCII+) is configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain ; and a voltage gain ; a voltage source V.sub.s, configured to generate an output current at a frequency s; wherein the first impedance Z.sub.1 is connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z.sub.1, comprises a resistor R.sub.1, in parallel with a capacitor C.sub.1; wherein the second impedance Z.sub.2 is connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z.sub.2 comprises a resistor R.sub.2 in parallel with a capacitor C.sub.2; and wherein the operational transconductance amplifier OTA is configured to have a transconductance gain g.sub.m, wherein the OTA includes a positive OTA input terminal, a negative OTA input terminal, an OTA output terminal, and a current bias I.sub.B input terminal, wherein: the positive OTA input terminal is connected to one of the first output terminal Z and the ground terminal; the negative OTA input terminal is connected to one of the first output terminal Z and the ground terminal; and the OTA output terminal is connected to the first impedance Z.sub.1, wherein the active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R.sub.1, a value for C.sub.1, a value for R.sub.2 and a value for C.sub.2.

2. The inductor simulator and impedance multiplier circuit of claim 1, wherein: the OTA is configured to generate an output current I.sub.o; the positive VCII+ input terminal is configured to receive an input current I.sub.y, equal to the difference between I.sub.s and I.sub.0; the first output terminal Z is configured to generate a voltage V.sub.z; the second output terminal X is configured to generate a voltage V.sub.x across the second impedance Z.sub.2 and a current i.sub.x through the second impedance Z.sub.2, wherein i.sub.x=I.sub.y and V.sub.z=V.sub.x; the output current I.sub.o is given by I.sub.o=I.sub.x Z.sub.2 g.sub.m=I.sub.y Z.sub.2 g.sub.m; and a voltage at the positive VCII+ input terminal Y is given by V.sub.y, where V.sub.y=0.

3. The inductor simulator and impedance multiplier circuit of claim 2, wherein: the positive OTA input terminal is connected to the first output terminal Z; the negative OTA input terminal is connected to the ground terminal, such that an input impedance Z.sub.in of the VCII+ is given by $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$ where Z.sub.2g.sub.m is 1.

4. The inductor simulator and impedance multiplier circuit of claim 3, wherein: a tunable positive active inductor simulator is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by $Z_{in}=s{C}_2\frac{R_1}{20I_B}=sL$ where $L=C_2\frac{R_1}{20I_B};$ and a value of the inductor L is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

5. The inductor simulator and impedance multiplier circuit of claim 3, wherein: a tunable positive capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by $Z_{in}=\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$ in which the capacitance C.sub.1 is multiplied by (1+20R.sub.2I.sub.B); and an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

6. The inductor simulator and impedance multiplier circuit of claim 3, wherein: a tunable positive resistance multiplier is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by $Z_{in}=\frac{R_1}{\left(1-20R_2{I}_B\right)},$ in which R.sub.1 is multiplied by $\frac{1}{\left(1-20R_2{I}_B\right)},$ where 020R.sub.2I.sub.B<1; and an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

7. The inductor simulator and impedance multiplier circuit of claim 2, wherein: the positive OTA input terminal is connected to the ground terminal; the negative OTA input terminal is connected to the first output terminal Z; and an input impedance Z.sub.in of the VCII+ is given by $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$ where Z.sub.2g.sub.m>1.

8. The inductor simulator and impedance multiplier circuit of claim 7, wherein: a tunable negative active inductor simulator is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by $Z_{in}=-s{C}_2\frac{R_1}{20I_B}=-sL$ where $L=C_2\frac{R_1}{20I_B};$ and a value of the inductor L is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

9. The inductor simulator and impedance multiplier circuit of claim 7, wherein: a tunable negative active capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by $Z_{in}=-\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$ in which the capacitance C.sub.1 is multiplied by (20R.sub.2I.sub.B); and an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

10. The inductor simulator and impedance multiplier circuit of claim 8, wherein: a tunable negative resistance multiplier is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by $Z_{in}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$ in which R.sub.1 is multiplied by $-\frac{1}{\left(1-20R_2{I}_B\right)},$ where 020R.sub.2I.sub.B<1; and an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) A more complete appreciation of this disclosure and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:

(2) FIG. 1 is a high-level diagram illustrating an exemplary configuration of a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit, according to aspects of the present disclosure;

(3) FIG. 2 is an exemplary internal structure of a voltage-mode conveyor, according to aspects of the present disclosure;

(4) FIG. 3 is a schematic diagram illustrating an exemplary configuration of a tunable grounded negative active inductor simulator and resistance multiplier circuit, according to aspects of the present disclosure;

(5) FIG. 4A illustrates a circuit diagram of a high pass filter (HPF) based on an active inductor simulator, according to aspects of the present disclosure;

(6) FIG. 4B illustrates a circuit diagram of a low pass filter (LPF) based on a capacitance multiplier, according to aspects of the present disclosure;

(7) FIG. 4C illustrates a circuit diagram of the HPF based on a resistance multiplier, according to aspects of the present disclosure;

(8) FIG. 5 illustrates a frequency response of the HPF using the active inductor simulator, according to aspects of the present disclosure;

(9) FIG. 6 illustrates a transient response of the HPF using the active inductor simulator, according to aspects of the present disclosure;

(10) FIG. 7 shows a frequency range of the active inductor simulator, according to aspects of the present disclosure;

(11) FIG. 8 illustrates a frequency response of the LPF based on the capacitance multiplier, according to aspects of the present disclosure;

(12) FIG. 9 illustrates a transient response of the LPF based on the capacitance multiplier, according to aspects of the present disclosure;

(13) FIG. 10 illustrates a frequency response of the HPF based on the resistance multiplier, according to aspects of the present disclosure;

(14) FIG. 11A illustrates the transient response of the HPF for a bias current I.sub.B=0.2 mA, according to aspects of the present disclosure;

(15) FIG. 11B illustrates the transient response of the HPF for a bias current I.sub.B=1 mA, according to aspects of the present disclosure;

(16) FIG. 11C illustrates the transient response of the HPF for a bias current I.sub.B=2 mA, according to aspects of the present disclosure;

(17) FIG. 12A illustrates the frequency response of the HPF for the bias current I.sub.B=0.2 mA, according to aspects of the present disclosure; and

(18) FIG. 12B illustrates the frequency response of the HPF for the bias current I.sub.B=2 mA, according to aspects of the present disclosure.

DETAILED DESCRIPTION

(19) In the drawings, like reference numerals designate identical or corresponding parts throughout the several views. Further, as used herein, the words a, an and the like generally carry a meaning of one or more, unless stated otherwise.

(20) Furthermore, the terms approximately, approximate, about, and similar terms generally refer to ranges that include the identified value within a margin of 20%, 10%, or preferably 5%, and any values therebetween.

(21) Aspects of this disclosure are directed to a grounded positive and negative active inductor simulator (AIS) and impedance multiplier circuit. The grounded positive and negative active inductor simulator and impedance multiplier circuit can be configured as any one of an active inductor simulator, a capacitance multiplier, a positive resistance multiplier, a negative resistance multiplier, a negative active inductor simulator, and a negative capacitance multiplier by choosing the values of Z.sub.1 and Z.sub.2. The described circuit includes only one second-generation voltage-mode conveyor (VCII+), one transconductance amplifier, OTA, and two passive elements.

(22) In various aspects of the disclosure, non-limiting definitions of one or more terms that are used in the document are provided below.

(23) The term second-generation voltage-mode conveyor (VCII) is defined as a dual circuit of a second-generation current conveyor (CCII), which provides the possibility of processing signals in the current domain while providing output signals in the voltage form. The VCII includes Y and X ports (input terminals) and Z port (output terminal). Y is a low-impedance current input port and X is a high-impedance current output port. For VCII, B is a current gain between the Y and X ports and is a voltage gain between the X and Z ports. V.sub.x and V.sub.z are the voltages at the X and Z ports, respectively. I.sub.V and I.sub.x are the input current to the Y port and output current at the X port, respectively.

(24) The term plus type VCII (VCII+) is defined as a second-generation voltage-mode conveyor (VCII) in which current in the X terminal flows in the same direction with respect to that related to the Y terminal. The VCII+ has + (positive current gain).

(25) The term negative type VCII (VCII) is defined as a second-generation voltage-mode conveyor (VCII) in which current in the X terminal. The VCII has (positive current gain).

(26) The term impedance simulator is defined as a circuit that simulates an input impedance that may be one of inductive, capacitive and active (resistance). The impedance simulator is used for simulating the impedance of an electronic equipment under different power consumption platforms.

(27) The term capacitance multiplier is defined as an electronic circuit that increases the value of a reference capacitor by a predefined multiplication factor, achieving a higher equivalent capacitance level in an IC form. The capacitor multipliers support design of complex integrated circuits possible that otherwise would be challenging with actual capacitors.

(28) The term impedance multiplier is defined as a circuit that effectively magnifies the impedance presented by an external load. An example of impedance multiplier is an impedance doubler, which doubles the effective impedance of the external load. The impedance multiplier circuit includes an input impedance having a defined value of impedance and a circuit coupled to this input impedance for multiplying its value by a multiplication factor.

(29) FIG. 1 is a high-level diagram illustrating an exemplary configuration of a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit 100 (hereinafter referred to as the circuit 100). Referring to FIG. 1, the circuit 100 includes a second generation voltage-mode conveyor circuit (VCII+) 110, a voltage source V.sub.s, an operational transconductance amplifier (OTA) 120 and two passive components: a first impedance Z.sub.1, and a second impedance Z.sub.2.

(30) The second generation voltage-mode conveyor circuit (VCII+) 110 includes a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X. In an aspect, the VCII+ 110 has a current gain , and a voltage gain . The voltage source V.sub.s is configured to generate an output current I.sub.s at a frequency s.

(31) The first impedance Z.sub.1 is electrically connected between the voltage source V.sub.s and the positive VCII+ input terminal Y. An internal circuit of the first impedance Z.sub.1 includes a resistor R.sub.1 and a capacitor C.sub.1, where the resistor R.sub.1 is connected in parallel to the capacitor C.sub.1.

(32) The second impedance Z.sub.2 is electrically connected between the second output terminal X, and a ground terminal. An internal circuit of the second impedance Z.sub.2 has a resistor R.sub.2 and a capacitor C.sub.2, where the resistor R.sub.2 is connected in parallel to the capacitor C.sub.2.

(33) The operational transconductance amplifier (OTA) 120 is an amplifier whose differential input voltage produces an output current. For example, the OTA 120 is a voltage controlled current source (VCCS). In an aspect, the OTA 120 includes an additional input for a current to control a transconductance of the OTA 120. In an example, the OTA 120 has a transconductance gain g.sub.m. The OTA 120 includes a positive OTA input terminal 125, a negative OTA input terminal 130, an OTA output terminal 135, and a current bias I.sub.B input terminal. In an aspect, the positive OTA input terminal 125 is connected to one of the first output terminal Z and the ground terminal. The negative OTA input terminal 130 is connected to one of the first output terminal Z and the ground terminal. The OTA output terminal 135 is connected to the first impedance Z.sub.1.

(34) In an aspect, the grounded positive and negative active inductor simulator and impedance multiplier circuit 100 is configured to be tuned by a selection of a value for R.sub.1, a value for C.sub.1, a value for R.sub.2 and a value for C.sub.2.

(35) In an aspect, the OTA 120 is configured to generate an output current I.sub.o. In an example, the output current I.sub.o is given by I.sub.o=I.sub.x Z.sub.2 g.sub.m=I.sub.y Z.sub.2 g.sub.m. The positive VCII+ input terminal Y is configured to receive an input current I.sub.y. In an example, the I.sub.y is equal to the difference between I.sub.s and I.sub.0. A voltage at the positive VCII+ input terminal Y is given by V.sub.y, where V.sub.y=0. The first output terminal Z is configured to generate a voltage V.sub.z. The second output terminal X is configured to generate a voltage V.sub.x across the second impedance Z.sub.2. The second output terminal X is configured to generate a current ix through the second impedance, Z.sub.2, wherein i.sub.x=I.sub.y and V.sub.z=V.sub.x.

(36) In one example configuration, the positive OTA input terminal 125 is electrically connected to the first output terminal Z, and the negative OTA input terminal 130 is connected to the ground terminal. In such configuration, an input impedance Z.sub.in of the VCII+ 110 is given by

(37) $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m is 1.

(38) In an aspect, the circuit 100 is configured to operate as a tunable positive active inductor simulator by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(39) $Z_{in}=s{C}_2\frac{R_1}{20I_B}=sL$
where

(40) $L=C_2\frac{R_1}{20I_B}.$
In an aspect, a value of the inductor L can be tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

(41) In an aspect, the circuit 100 is configured to operate as a tunable positive capacitance multiplier by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(42) $Z_{in}=\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance C.sub.1 is multiplied by (1+20R.sub.2I.sub.B). In an aspect, an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

(43) In an aspect, the circuit 100 is configured to operate as a tunable positive resistance multiplier by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(44) $Z_{in}=\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(45) $\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1. In an aspect, an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(46) In one example configuration, the positive OTA input terminal 125 is connected to the ground terminal. The negative OTA input terminal 130 is connected to the first output terminal Z. The input impedance Z.sub.in of the VCII+ is given by

(47) $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m>1.

(48) In an aspect, the circuit 100 is configured to operate as a tunable negative active inductor simulator by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(49) 0$Z_{in}=-s{C}_2\frac{R_1}{20I_B}=-sL$
where

(50) $L=C_2\frac{R_1}{20I_B}.$
In an aspect, a value of the inductor L is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

(51) In an aspect, the circuit 100 is configured to operate as a tunable negative active capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(52) $Z_{in}=-\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (20R.sub.2I.sub.B). In an aspect, an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

(53) In an aspect, the circuit 100 is configured to operate as a tunable negative resistance multiplier by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(54) $Z_{in}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(55) $-\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1. In an aspect, an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(56) A relationship between voltage and currents terminals of VCII+ 110 is represented as:

(57) $\begin{array}{cc}{i}_x=i_y,V_z=V_x,V_y=0,& \left(1\right)\end{array}$
where is a current gain and is a voltage gain.

(58) The terminal characteristics of the VCII+ 110 are high impedance at X node (input terminal) and low impedance at Y and Z nodes (output terminals).

(59) With reference to FIG. 1, the input impedance of the circuit 100 is given by:

(60) $\begin{array}{cc}{Z}_{in}=\frac{V_s}{I_s}=\frac{V_s}{I_y-I_o},& \left(2\right)\end{array}$$\begin{array}{cc}{i}_0=V_Z{g}_m=i_x{Z}_2{g}_m=-i_y{Z}_2{g}_m.& \left(3\right)\end{array}$

(61) As, i.sub.y=V.sub.s/Z.sub.1, the input impedance is given as:

(62) $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$
where, g.sub.m=20I.sub.B is the OTA transconductance and I.sub.B is the OTA bias current.

(63) From equation (4), the circuit 100 can be used to implement the tunable grounded active inductor and capacitance multiplier as follows:

(64) I. Implementation as the Active Inductor Simulator (AIS)

(65) If Z.sub.1=R.sub.1, and

(66) $Z_2=\frac{1}{{\mathrm{sC}}_2},$
the input impedance is given by:

(67) $\begin{array}{cc}{Z}_{in}=s{C}_2\frac{R_1}{20I_B}=\mathrm{sL},& \left(5\right)\end{array}$
where

(68) 0$L=C_2\frac{R_1}{20I_B}.$

(69) Equation (5) implements the tunable AIS, and the value of the inductance is controlled using R.sub.1 and I.sub.B.

(70) II. Implementation as the Capacitance Multiplier

(71) If

(72) $Z_1=\frac{1}{{\mathrm{sC}}_1}$
and Z.sub.2=R.sub.2, then the input impedance is given by:

(73) $\begin{array}{cc}{Z}_{in}=\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)}.& \left(6\right)\end{array}$

(74) The original capacitance (C.sub.1) is multiplied by (1+20R.sub.2I.sub.B) and can be tuned using R.sub.2 and I.sub.B.

(75) FIG. 2 is an internal structure of a voltage-mode conveyor 200, according to aspects of the present disclosure. For example, the voltage-mode conveyor 200 is a second-generation voltage conveyor (VCII). The VCII 200 includes a current buffer 210 and a voltage buffer 220. The current buffer 210 is set up between the Y and X terminals, and the voltage buffer 220 set up between the X and Z terminals. Unlike a CCII, the Y terminal of the VCII 200 is a low impedance current input port with an ideal value of zero, X is a high impedance current output port (terminal) with an ideal value of infinite, and Z is a low impedance voltage output port with an ideal value of zero. The relationship between port voltages and currents is expressed as:

(76) $\begin{array}{cc}\left[\begin{array}{c}{i}_x\\ V_z\end{array}\right]=\left[\begin{array}{cc}& 0\\ 0& \end{array}\right]\left[\begin{array}{c}{i}_y\\ V_x\end{array}\right]& \left(7\right)\end{array}$
where VCII+ and VCII are identified by + and , respectively (where should be close to 1). For example, a VCII can act as a positive VCII+ and a negative VCII. The function of the VCII is either positive or negative based on whether a current in the X terminal flows in the same direction (positive, VCII+) or in the opposite direction (negative, VCII) with respect to that related to the Y terminal.

(77) The voltage gain of the voltage buffer 220 is (AV=). In an example, the value of a is unity. As the Y terminal has an extremely low input impedance, the Y terminal can be considered as a virtual ground node. The main features of VCII 200 can be summarized as firstly, unlike other active blocks, a current summing operation can be easily performed at the current input low impedance Y port. Secondly, having a low impedance voltage output Z port allows the employment of the VCII 200 in a voltage mode workflow, giving the flexibility to easily perform current mode operations to the designer. Thirdly, positive and negative voltage gains are simply obtained by employing a VCII+ and a VCII, respectively.

(78) FIG. 3 is a schematic diagram illustrating an exemplary configuration of a tunable grounded negative active inductor simulator and resistance multiplier circuit 300 (hereinafter referred to as the circuit 300). For example, the circuit 300 can be configured to implement any one of a tunable positive resistance multiplier, a tunable negative resistance multiplier, a negative active inductor simulator and a negative capacitance multiplier. Referring to FIG. 3, the circuit 300 includes a second generation voltage-mode conveyor circuit (VCII+) 310, a voltage source V.sub.s, a first impedance Z.sub.1, a second impedance Z.sub.2, and an operational transconductance amplifier (OTA) 320. The construction of circuit 300 is substantially similar to that of the circuit 100, and thus the construction is not repeated here in detail for the sake of brevity.

(79) With reference to FIG. 3, the input impedance Z.sub.in is given by:

(80) $\begin{array}{cc}{Z}_{in}=\frac{Z_1}{1-Z_2{g}_m}.& \left(8\right)\end{array}$
I. Implementation as a Positive Resistance Multiplier

(81) From Equation 8, if Z.sub.2g.sub.m<1, then Z.sub.1 will be scaled up and if Z.sub.1=R.sub.1 (the resistance to be scaled up), Z.sub.2=R.sub.2, then the input impedance is given by:

(82) $\begin{array}{cc}{Z}_{in}=\frac{R_1}{\left(1-20R_2{I}_B\right)}.& \left(9\right)\end{array}$

(83) In an aspect, a value of the 20R.sub.2I.sub.B lies between 0 and 1.

(84) II. Implementation as a Negative Resistance Multiplier

(85) From Equation 8, if Z.sub.2g.sub.m>1, then a negative tunable resistance multiplier is obtained.

(86) If Z.sub.1=R.sub.1 (the resistance to be scaled up), Z.sub.2=R.sub.2, then the input impedance is given by:

(87) $\begin{array}{cc}{Z}_{in}=\frac{R_1}{\left(-20R_2{I}_B\right)}.& \left(10\right)\end{array}$
III. Implementation as a Negative Active Inductor Simulator

(88) If Z.sub.1=R.sub.1 and,

(89) $Z_2=\frac{1}{{\mathrm{sC}}_2},$
Z.sub.2=g.sub.m>1, then a negative active inductor is obtained and is given by:

(90) $\begin{array}{cc}{Z}_{in}=-s{C}_2\frac{R_1}{20I_B}.& \left(11\right)\end{array}$
IV. Implementation as the Negative Capacitance Multiplier

(91) If

(92) $Z_1=\frac{1}{{\mathrm{sC}}_1},$
and Z.sub.2=R.sub.2, Z.sub.2g.sub.m>1, then the input impedance is given by:

(93) 0$\begin{array}{cc}{Z}_{in}=-\frac{1}{s{C}_1\left(20R_2{I}_B\right)}.& \left(12\right)\end{array}$

(94) The following examples are provided to illustrate further and to facilitate the understanding of the present disclosure.

(95) Experimental Data and Analysis

(96) First Experiment: Determining the functionality of the tunable grounded positive and negative active inductor simulator and impedance multiplier circuit 100.

(97) To confirm the functionality of the circuit 100, the active inductor simulator (AIS) and the capacitor multiplier were used in the design of a high pass filter (HPF) and a low pass filter (LPF) respectively. The resistance multiplier was also used in the designing of the HPF.

(98) Experiments were performed using a multisim professional tool (developed by National Instruments, located at NI. 11500 N Mopac Expwy, Austin, TX 78759-3504, USA). The multisim tool is an industry standard SPICE simulation and circuit design software for analog, digital, and power electronics in education and research. The multisim tool integrates industry standard SPICE simulation with an interactive schematic environment to instantly visualize and analyze electronic circuit behavior. The circuit 100 was experimentally tested by using an AD844 as the VCII+ 110. The AD844 is fabricated by Analog Devices, located at One Analog Way Wilmington, MA 01887, USA. In an example, an LM13700 is used as OTA 120. The LM13700 is fabricated by Texas Instruments, located at 12500 TI Blvd., Dallas, Texas 75243, USA. In an example, the circuit 100 is powered with V.sub.cc=V.sub.ss=5V.

(99) FIG. 4A illustrates a circuit diagram of the HPF 410 using the AIS. An RL circuit acts as the HPF 410 as shown in FIG. 4A. In the circuit, the resistor R is a series component and the equivalent inductor L.sub.eq is a shunt component. For confirming the functionality of the AIS, the high pass filter circuits shown in FIG. 4A was simulated with R=1 k and the active impedance parameters were R.sub.1=10 k, and C.sub.2=1 nF.

(100) FIG. 4B illustrates a circuit diagram of a LPF 420 based on the capacitance multiplier. The resistor R is the series component and an equivalent capacitor C.sub.eq is the shunt component. The resistor R is placed in series with the power source and the equivalent capacitor C.sub.eq is placed in parallel to that same power source. An RC circuit as shown in FIG. 4B forms the LPF 420 because of the reactive properties of the capacitor C.sub.eq. The equivalent capacitor C.sub.eq offers very high resistance or impedance to low frequency signals. Conversely, the equivalent capacitor C.sub.eq offers lower resistance as the frequency of the signal increases. Thus, the equivalent capacitor C.sub.eq offers very low impedance to a very high frequency signal. As the equivalent capacitor C.sub.eq offers low impedance to high-frequency signals, high frequency signals normally go through the equivalent capacitor C.sub.eq, as the equivalent capacitor C.sub.eq represents a low-impedance path. Thus, high-frequency signals pass via the capacitor path, while low-frequency signals do not take the capacitor path. Instead, the low-frequency signals are transmitted to output.

(101) FIG. 4C illustrates a circuit diagram of a HPF 430 based on the resistance multiplier. Two passive elements, that is, equivalent resistor R.sub.eq and capacitor C are connected in series combination to allow the frequencies higher than the cut-off frequency of a signal. The output voltage is obtained across the equivalent resistor R.sub.eq by applying input voltage across the capacitor C.

(102) FIG. 5 shows the frequency response 500 of the HPF 410 based on the AIS. During simulation, the value of resistance R was set to 1 k. The active inductor (AI) parameters were: R.sub.1=10 k, and C.sub.2=1 nF. The OTA bias current I.sub.B was varied from 0.2 mA to 2 mA. The inductance was varied from 0.5 mH-to-5 mH. Curve 502 represents the frequency response of the HPF 410, when value of bias current I.sub.B was 0.2 mA. Curve 504 represents the frequency response of the HPF 410, when value of bias current I.sub.B was 2 mA. Curves 506 and 508 represent the intermediate frequency response of the HPF 410. It is reflected from the FIG. 5, that the described AIS is working accurately.

(103) FIG. 6 shows the transient response 600 of the HPF 410 based on the AIS. As known, after an external excitation is applied, the transient response is a response of a circuit that fades out with time. The transient response is followed by a steady state response, which is the behavior of the circuit for a long time. In an example, a transient analysis of the HPF 410 was carried out using 300 kHz input signal with 1V amplitude and the bias current I.sub.B of 1 mA. Curve 602 represents an input voltage supplied to the HPF 410. Curve 604 represents an output voltage. It is reflected from the FIG. 6, that the described AIS is working accurately.

(104) FIG. 7 shows a frequency range 700 of the AIS. Curve 702 represents an ideal inductance frequency response of the HPF 410. Curve 704 represents a simulated inductance frequency repose in the HPF 410. The active inductor simulator was configured to work in the range of 100 Hz to 1 MHz as shown in FIG. 7. The frequency range may be changed by varying the value of the capacitance used.

(105) FIG. 8 is an exemplary illustration 800 of the frequency response of the LPF 420 based on the capacitance multiplier. To test the functionality of the described capacitance multiplier, the described capacitance multiplier was used in the design of an RC low pass filter 420 with R=1 k, R.sub.1=10 k and C=1 nF. The bias current I.sub.B of the OTA was varied from 0.2 mA to 2 mA. Curve 802 represents the frequency response of the LPF 420, when value of bias current I.sub.B was 0.2 mA. Curve 804 represents the frequency response of the LPF 420, when value of bias current I.sub.B was 2 mA. Curves 806 and 808 represent the intermediate frequency response of the LPF 420. FIG. 8 illustrates that the LPF 420 works properly with tunable 3 dB frequency. Curves 806, 808, and 810 represent the intermediate frequency response of the LPF 420.

(106) FIG. 9 shows the transient response 900 of the LPF 420 based on the capacitance multiplier. In an example, a transient analysis of the LPF 420 was performed. Curve 902 represents an input voltage supplied to the LPF 420. Curve 904 represents a bias current I.sub.B=2 mA. FIG. 9 illustrates that the capacitance multiplier performs accurately. Curves 906, 908, and 910 represent the intermediate frequency response of the LPF 420.

(107) FIG. 10 shows the frequency response 1000 of the HPF 430 based on the resistance multiplier. To test the functionality of the described resistance multiplier, the described resistance multiplier is used in the design of an RC HPF 430. The HPF 430 has Z.sub.1=R.sub.1=100, is the resistor to be scaled up and Z.sub.2=R.sub.2=100 and I.sub.B can be varied such that the denominator is not zero. Curve 1002 represents the frequency response of HPF 430, when value of bias current I.sub.B was 0.2 mA. Curve 804 represents the frequency response of the HPF 430, when value of bias current I.sub.B was 2 A. Curves 1006, 1008, and 1010 represent the intermediate frequency response of the HPF 430.

(108) FIG. 11A-FIG. 11C illustrate the transient response of the HPF 410 for different bias current I.sub.B. To verify the functionality of the circuit 100 experimentally, the AIS of the present disclosure was used in the design of a tunable HPF with R=1 k and the active impedance parameters R.sub.1=10 k and C.sub.2=1 nF (measured 1.2 nF). In an aspect, the transient response for different bias currents using 15 mV signal at the 3 dB frequency are shown in FIG. 11A-FIG. 11C.

(109) FIG. 11A is an exemplary illustration 1100 of the transient response of the HPF 410 when the bias current I.sub.B=0.2 mA. Curve 1102 represents the input voltage supplied to the HPF 410. Curve 1104 represents the output voltage.

(110) FIG. 11B is an exemplary illustration 1110 of the transient response of the HPF 410 for bias current I.sub.B=1 mA. Curve 1112 represents the input voltage and curve 1114 represents the output voltage.

(111) FIG. 11C is an exemplary illustration 1120 of the transient response of the HPF 410 for bias current I.sub.B=2 mA. Curve 1122 represents the input voltage and curve 1124 represents the output voltage.

(112) The HPF circuit 410 using AIS was simulated for total harmonic distortion (THD) using different bias currents (For example, I.sub.B=0.2 mA, 1 mA, and 2 mA). The observed THD was 0.484%, 0.019%, and 0.005% respectively which is within the acceptable range. The frequency response was also carried out for the bias current of 0.2 mA. FIG. 12A is an exemplary illustration of the frequency response of the HPF 410 for bias current I.sub.B=0.2 mA. Curve 1210 represents the frequency response of the HPF 410 with respect to gain of the HPF 410.

(113) FIG. 12B is another exemplary illustration of the frequency response of the HPF for bias current I.sub.B=0.2 mA. Curve 1220 represents the frequency response of the HPF 410 with respect to phase of the HPF 410. It can be observed from FIG. 12A-FIG. 12B that there is a small deviation, due to parasitic effects on the low frequency side.

(114) The performance of the present circuit 100 is compared with the existing circuits and is summarized in Table 1. It can be observed from the comparison table that the present circuit 100 is efficient in comparison to all cited existing circuits.

(115) TABLE-US-00001 TABLE 1 Summary of performance comparison Number of passive elements No. of # of R Impedance/ active # of C Simulated building Grounded (Floating) Frequency (AIS, R Circuits block elements Power Technology range & C used: (ABB) G(F) G(F) supply m (Hz) multiplier) Conventional 1 VCII 0.9 0.18 (2) 1 1 KHz-10 AIS only simulated MHz inductor with reduced series resistors using a single VCII+ Conventional 3 CFOA NA NA 2(1) 1(0) 1 Hz-1 AIS only simulated MHz inductors with reduced parasitic impedance effects Conventional 1 CFOA 15 NA 1(1) 0(1) NA AIS only lossless and lossy grounded inductor simulators Conventional 2CFOA 5 NA active device based grounded inductor simulator and universal filter Conventional 1 E-VCII 0.3 0.18 0 (1) 80 Hz-40 C extremely KHz multiplier Low power only temperature insensitive electronically tunable VCII- Based Grounded Capacitance Multiplier 1 INIC, 0.75 0.13 0(2) 1(0) 100 Hz-50 AIS Conventional 1 VNIC MHz simulated grounded inductor based on two NICs, two resistors and a grounded capacitor Conventional 1 MD 0.75 0.13 0(2) 1(0) AIS Inverting VCC Voltage Buffer Based Lossless Grounded Inductor Simulators Present circuit 1 VCII 5 NA 1(1) 1 100 Hz-10 All 100 and 1 MHz OTA

(116) The first embodiment is illustrated with respect to FIG. 1-FIG. 4C. The first embodiment describes a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit 100. The circuit 100 includes a second generation voltage-mode conveyor circuit (VCII+) 110, a voltage source V.sub.s, a first impedance Z.sub.1, a second impedance Z.sub.2, and an operational transconductance amplifier OTA 120. The second generation voltage-mode conveyor circuit (VCII+) 110 is configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X. The VCII+ 110 has a current gain , and a voltage gain . The voltage source V.sub.s is configured to generate an output current I.sub.s,| at a frequency s. The first impedance Z.sub.1 is connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z.sub.1, includes a resistor R.sub.1, in parallel with a capacitor, C.sub.1. The second impedance Z.sub.2 is connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z.sub.2, includes a resistor R.sub.2, in parallel with a capacitor C.sub.2. The OTA 120 is configured to have a transconductance gain g.sub.m, wherein the OTA includes a positive OTA input terminal 125, a negative OTA input terminal 130, an OTA output terminal 135, and a current bias I.sub.B, input terminal. The positive OTA input terminal 125 is connected to one of the first output terminal Z and the ground terminal. The negative OTA input terminal 130 is connected to one of the first output terminal Z and the ground terminal. The OTA output terminal 135 is connected to the first impedance Z.sub.1. The grounded positive and negative active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R.sub.1, a value for C.sub.1, a value for R.sub.2 and a value for C.sub.2.

(117) In an aspect, the OTA 120 is configured to generate an output current I.sub.o. The positive VCII+ input terminal Y is configured to receive an input current I.sub.y, equal to the difference between I.sub.s and I.sub.0. The first output terminal Z is configured to generate a voltage, V.sub.z. The second output terminal X is configured to generate a voltage V.sub.x, across the second impedance Z.sub.2, and a current i.sub.x, through the second impedance Z.sub.2, wherein i.sub.x=I.sub.y and V.sub.z=V.sub.x. The output current I.sub.o is given by I.sub.o=I.sub.x Z.sub.2 g.sub.m=I.sub.y Z.sub.2 g.sub.m, and a voltage at the positive VCII+ input terminal Y, is given by V.sub.y, where V.sub.y=0.

(118) In an aspect, the positive OTA input terminal 125 is connected to the first output terminal Z. The negative OTA input terminal 130 is connected to the ground terminal, such that an input impedance Z.sub.in, of the VCII+ is given by

(119) $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m is 1.

(120) In an aspect, a tunable positive active inductor simulator is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(121) $Z_{in}={\mathrm{sC}}_2\frac{R_1}{20I_B}=\mathrm{sL}$
where

(122) $L=C_2\frac{R_1}{20I_B},$
and a value of the inductor, L, is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

(123) In an aspect, a tunable positive capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(124) $Z_{in}=\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (1+20R.sub.2I.sub.B), and an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

(125) In an aspect, a tunable positive resistance multiplier is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(126) $Z_{in}=\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(127) $\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, and an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(128) In an aspect, the positive OTA input terminal 125 is connected to the ground terminal, the negative OTA input terminal 130 is connected to the first output terminal Z, and an input impedance Z.sub.in, of the VCII+ is given by

(129) $Z_{in}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m>1.

(130) In an aspect, a tunable negative active inductor simulator is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by Z

(131) $Z_{in}=-s{C}_2\frac{R_1}{20I_B}=-\mathrm{sL}$
where

(132) $L=C_2\frac{R_1}{20I_B},$
and a value of the inductor, L, is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

(133) In an aspect, a tunable negative active capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by Z

(134) 0$Z_{in}=-\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance C.sub.1 is multiplied by (20R.sub.2I.sub.B), and an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

(135) In an aspect, a tunable negative resistance multiplier is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by Z

(136) $Z_{\mathrm{in}}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(137) $-\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, and an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(138) The second embodiment is illustrated with respect to FIG. 1-FIG. 4C. The second embodiment describes a method for implementing a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit 100. The method includes selecting one second generation voltage-mode conveyor circuit VCII+ 110, configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain, ; and a voltage gain, . The method includes connecting a first impedance Z.sub.1, to the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z.sub.1, includes a resistor R.sub.1, in parallel with a capacitor C.sub.1. The method includes connecting a voltage source V.sub.s to the first impedance Z.sub.1, wherein the voltage source V.sub.s is configured to generate an output current I.sub.s at a frequency s. The method further includes connecting a second impedance Z.sub.2 between the second output terminal X, and a ground terminal.

(139) The method further includes selecting one operational transconductance amplifier OTA 120 configured to have a transconductance gain g.sub.m, wherein the OTA 120 includes a positive OTA input terminal 125, a negative OTA input terminal 130, and an OTA output terminal 135. The method further includes connecting the positive OTA input terminal 125 to one of the first output terminal Z, and the ground terminal, connecting the negative OTA input terminal 130 to one of the first output terminal Z, and the ground terminal, connecting the OTA output terminal 135 to the first impedance Z.sub.1, such that: the OTA is configured to generate an output current I.sub.o, the positive VCII+ input terminal is configured to receive an input current I.sub.y, equal to the difference between I.sub.s and I.sub.0. The first output terminal Z is configured to generate a voltage V.sub.z. The second output terminal X is configured to generate a voltage V.sub.x, across the second impedance Z.sub.2, and a current i.sub.x, through the second impedance Z.sub.2, wherein i.sub.x=I.sub.y and V.sub.z=V.sub.x. The output current I.sub.o is given by I.sub.o=I.sub.x Z.sub.2 g.sub.m=I.sub.y Z.sub.2 g.sub.m, and a voltage at the positive VCII+ input terminal Y is given by V.sub.y, where V.sub.y=0.

(140) The method further includes connecting the positive OTA input terminal 125 to the first output terminal Z, and connecting the negative OTA input terminal 130 to the ground terminal, such that an input impedance, Z.sub.in, of the VCII+ is given by Z

(141) $Z_{\mathrm{in}}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m is 1.

(142) The method further includes configuring a tunable positive active inductor simulator by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(143) $Z_{in}=s{C}_2\frac{R_1}{20I_B}=sL$
where

(144) $L=C_2\frac{R_1}{20I_B},$
and tuning a value of the inductor, L, by selecting the value of C.sub.2 and the value of R.sub.1.

(145) The method further includes configuring a tunable positive capacitance multiplier by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(146) $Z_{in}=\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (1+20R.sub.2I.sub.B), and tuning an amount of multiplication of C.sub.1 by selecting the value of R.sub.2.

(147) The method further includes configuring a tunable positive resistance multiplier by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(148) $Z_{in}=\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(149) $\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, and tuning an amount of multiplication of R.sub.1 by selecting the value of R.sub.2.

(150) The method further includes connecting the positive OTA input terminal 125 is connected to the ground terminal, connecting the negative OTA input terminal 130 is connected to the first output terminal, Z, such that an input impedance, Z.sub.in, of the VCII+ is given by

(151) $Z_{\mathrm{in}}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m>1.

(152) The method further includes a tunable negative active inductor simulator is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(153) 0$Z_{\mathrm{in}}=-{\mathrm{sC}}_2\frac{R_1}{20I_B}=-\mathrm{sL}$
where

(154) $L=C_2\frac{R_1}{20I_B},$
and a value of the inductor, L, is tuned by the selection of the value of C.sub.2 and the value of R.sub.1.

(155) The method further includes a tunable negative active capacitance multiplier is configured by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(156) $Z_{\mathrm{in}}=-\frac{1}{{\mathrm{sC}}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (20R.sub.2I.sub.B), and an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2.

(157) The method further includes a tunable negative resistance multiplier is configured by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(158) $Z_{\mathrm{in}}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(159) $-\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, and an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(160) The third embodiment is illustrated with respect to FIG. 1-FIG. 4C. The third embodiment describes a system for configuring a tunable grounded positive and negative active inductor simulator and impedance multiplier circuit 100. The system includes one second generation voltage-mode conveyor circuit (VCII+) 110, configured with a positive VCII+ input terminal Y, a first output terminal Z, and a second output terminal X, wherein the VCII+ has a current gain ; and a voltage gain , a voltage source V.sub.s, configured to generate an output current I.sub.s, at a frequency s, a first impedance Z.sub.1, connected between the voltage source and the positive VCII+ input terminal Y, wherein an internal circuit of the first impedance Z.sub.1, comprises a resistor R.sub.1, in parallel with a capacitor C.sub.1, a second impedance Z.sub.2, connected between the second output terminal X, and a ground terminal, wherein an internal circuit of the second impedance Z.sub.2, comprises a resistor R.sub.2, in parallel with a capacitor C.sub.2, and an operational transconductance amplifier OTA 120, configured to have a transconductance gain g.sub.m, wherein the OTA 120 includes a positive OTA input terminal 125, a negative OTA input terminal 130, an OTA output terminal 135, and a current bias I.sub.B, input terminal, wherein: the positive OTA input terminal is connected to one of the first output terminal Z and the ground terminal, the negative OTA input terminal is connected to one of the first output terminal, Z and the ground terminal, and the OTA output terminal is connected to the first impedance Z.sub.1, wherein the grounded positive and negative active inductor simulator and impedance multiplier circuit is configured to be tunable by a selection of a value for R.sub.1, a value for C.sub.1, a value for R.sub.2 and a value for C.sub.2. The OTA is configured to generate an output current, I.sub.o. The positive VCII+ input terminal is configured to receive an input current I.sub.y, equal to the difference between I.sub.s and I.sub.0. The first output terminal Z is configured to generate a voltage V.sub.z. The second output terminal X is configured to generate a voltage V.sub.x, across the second impedance Z.sub.2, and a current i.sub.x, through the second impedance, Z.sub.2, wherein i.sub.x=I.sub.y and V.sub.z=V.sub.x. The output current I.sub.o is given by I.sub.o=I.sub.x Z.sub.2 g.sub.m=I.sub.y Z.sub.2 g.sub.m, and a voltage at the positive VCII+ input terminal Y, is given by V.sub.y, where V.sub.y=0. The positive OTA input terminal is connected to the first output terminal Z and the negative OTA input terminal is connected to the ground terminal, an input impedance Z.sub.in, of the VCI+ is given by

(161) $Z_{\mathrm{in}}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m is 1. The system is configured to implement any one of: a tunable positive active inductor simulator by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(162) $Z_{\mathrm{in}}={\mathrm{sC}}_2\frac{R_1}{20I_B}=\mathrm{sL}$
where

(163) $L=C_2\frac{R_1}{20I_B},$
and a value of the inductor, L, is tuned by the selection of the value of C.sub.2 and the value of R.sub.1, a tunable positive capacitance multiplier by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(164) $Z_{\mathrm{in}}=-\frac{1}{{\mathrm{sC}}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (1+20R.sub.2I.sub.B), wherein an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2, and a tunable positive resistance multiplier by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(165) $Z_{\mathrm{in}}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(166) 0$\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, wherein an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2; and when the positive OTA input terminal is connected to the ground terminal, the negative OTA input terminal is connected to the first output terminal, Z, such that an input impedance, Z.sub.in, of the VCII+ is given by

(167) $Z_{\mathrm{in}}=\frac{Z_1}{1+Z_2{g}_m},$
where Z.sub.2g.sub.m>1, the system is configured to implement any one of: a tunable negative active inductor simulator by setting Z.sub.1=R.sub.1, C.sub.1=0, R.sub.2=0 and Z.sub.2=1/sC.sub.2, such that the input impedance is given by

(168) $Z_{\mathrm{in}}=-{\mathrm{sC}}_2\frac{R_1}{20I_B}=-\mathrm{sL}$
where

(169) $L=C_2\frac{R_1}{20I_B},$
wherein a value of the inductor, L, is tuned by the selection of the value of C.sub.2 and the value of R.sub.1, a tunable negative active capacitance multiplier by setting Z.sub.1=1/sC.sub.1, R.sub.1=0, Z.sub.2=R.sub.2, and C.sub.2=0, such that the input impedance is given by

(170) $Z_{in}=-\frac{1}{s{C}_1\left(1+20R_2{I}_B\right)},$
in which the capacitance, C.sub.1, is multiplied by (20R.sub.2I.sub.B), wherein an amount of multiplication of C.sub.1 is tuned by the selection of the value of R.sub.2, and a tunable negative resistance multiplier by setting Z.sub.1=R.sub.1, C.sub.1=0, Z.sub.2=R.sub.2, C.sub.2=0, such that the input impedance is given by

(171) $Z_{in}=-\frac{R_1}{\left(1-20R_2{I}_B\right)},$
in which R.sub.1 is multiplied by

(172) $-\frac{1}{\left(1-20R_2{I}_B\right)},$
where 020R.sub.2I.sub.B<1, wherein an amount of multiplication of R.sub.1 is tuned by the selection of the value of R.sub.2.

(173) Obviously, numerous modifications and variations of the present disclosure are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the disclosure may be practiced otherwise than as specifically described herein.