SYSTEM AND METHOD OF OPERATING A SYSTEM

Abstract

In a system and method of operating a system that includes a controller and a first bus participant and a successor, the bus participant and successor each has a circuit arrangement arranged between an output and an input, a first resistor is arranged between the output and the supply voltage terminal, a second resistor is arranged between the input and a ground terminal, a third resistor can be arranged between the input and the supply voltage terminal by a first controllable semiconductor switch, and a fourth resistor can be arranged between the output and the supply voltage terminal by a second controllable semiconductor switch.

Claims

1-14. (canceled)

15. A system, comprising: a first bus participant; a successor; and a controller connected to the first bus participant by a data bus; wherein the first bus participant includes a first circuit arrangement between an output of the first bus participant and an input of the first bus participant; wherein the successor includes a second circuit arrangement between an output of the successor and an input of the successor; wherein the first and second circuit arrangements are of identical and/or similar configuration; wherein the first and second circuit arrangements have a supply voltage terminal; wherein the first circuit arrangement has a voltage sensing device adapted to sense a voltage applied to the output of the first circuit arrangement; wherein a first resistor is arranged between the output of the first bus participant arrangement and the supply voltage terminal of the first bus participant; wherein a second resistor is arranged between the input of the successor and a ground terminal; wherein a first controllable semiconductor switch is adapted to selectively connect a third resistor between the input of the first bus participant and the supply voltage terminal of the successor, such that the third resistor is arranged in parallel with the first resistor, when connecting the successor to the first bus participant; and wherein a second controllable semiconductor switch is adapted to selectively connect a fourth resistor between the output of the first bus subscriber and the supply voltage terminal of the successor, such that the fourth resistor is arranged in parallel with the third resistor, when connecting the successor to the first bus participant.

16. The system according to claim 15, wherein the successor is arranged as a second bus participant.

17. The system according to claim 15, wherein the controller is serially connected to the first bus participant by the data bus.

18. The system according to claim 15, wherein the data bus includes a CAN bus and/or an RS485 bus.

19. The system according to claim 15, wherein the output of the first bus participant is connected to ground.

20. The system according to claim 15, wherein the input of the successor is adapted to connect to the output of the first bus participant.

21. The system according to claim 15, wherein the successor includes a voltage detection device adapted to detect a voltage applied to the input of the successor and/or ground.

22. The system according to claim 21, wherein the successor includes a voltage detection device adapted to detect a voltage applied to the output of the successor and/or ground.

23. The system according to claim 15, wherein the first bus participant includes a voltage detection device adapted to detect a voltage applied to the input of the first bus participant and/or ground.

24. The system according to claim 15, wherein a first protection circuit against voltages that are excessively low and/or excessively high is arranged at the input of the first bus participant and/or the successor, and a second protective circuit against voltages that are excessively low and/or excessively high is arranged at the output of the first bus participant and/or the successor.

25. The system according to claim 15, wherein a first capacitor is arranged between ground and the input of the first bus participant and/or of the successor, and a second capacitor is arranged between ground and the output of the first bus participant and/or of the successor.

26. The system according to claim 24, wherein the first protection circuit includes a first resistor arranged between the input of the first bus participant and/or of the successor and a first diode, the first diode is arranged between the first resistor and the supply voltage terminal of the first bus participant and/or of the successor, such that current is supplied to the supply voltage terminal through the first diode, when a voltage which is higher than the supply voltage is applied to the input.

27. The system according to claim 26, wherein a second diode is arranged between the first resistor and ground, such that current is supplied to ground through the second diode, when a negative voltage is applied to the input.

28. The system according to claim 24, wherein the second protection circuit includes a resistor arranged between the output and a third diode, the third diode is arranged between the resistor and the supply voltage terminal, such that current is supplied to the supply voltage terminal through the third diode, when a voltage higher than the supply voltage is applied to the output.

29. The system according to claim 28, wherein a fourth diode is arranged between the resistor and ground, such that current is supplied to ground through the fourth diode, when a negative voltage is applied to the output.

30. The system according to claim 15, wherein first and second controllable semiconductor switches of the first circuit arrangement are integrated in a first component.

31. The system according to claim 30, wherein first, second, third, and fourth diodes of the first circuit arrangement are integrated in a second component.

32. The system according to claim 31, wherein the first circuit arrangement includes a printed circuit board upon which the first and the second component are assembled.

33. The system according to claim 31, wherein the first circuit arrangement includes a printed circuit board upon which the first and the second component are assembly by SMD technology.

34. A method for operating a system that includes a controller, a first bus participant, and a successor, the controller being connected and/or serially connected to the first bus participant by a data bus, a CAN bus, and/or a RS485 bus, the first bus participant including an activatable output and an activatable input, the successor also including an activatable output and an activatable input, each output having a first or second resistance value to a supply voltage terminal depending on an activation, each input, depending on activation, having a third or fourth resistance value to ground of the successor, comprising: detecting a voltage present at the output of the first bus participant and recognizing, depending on the detected voltage, and taking into account an activation state of the output of the first bus participant: whether the output is open and no successor is connected to the first bus participant; whether a successor is connected to the first bus participant, which has no supply voltage; whether a successor, which is supplied with a supply voltage and the input of which is activated, is connected to the first bus participant; whether a successor is connected to the first bus participant, and the successor is supplied with a supply voltage and the input of which is not activated; and whether a terminating plug is connected to the first bus participant and the output is electrically connected to ground.

35. The method according to claim 34, where a decision is made as to whether the detected voltage is contained in a first, second, third, or fourth voltage range, the first voltage range being above the second voltage range, the second voltage range being above the third voltage range, the third voltage range being above the fourth voltage range; wherein the first voltage range encodes information that no successor is connected to the first bus participant and that the output is open; where the third voltage range encodes information that a successor which has no supply voltage is connected to the first bus participant; wherein a further voltage range encodes information that a successor is connected to the first bus participant, the successor is supplied with a supply voltage, and the input of which is activated; wherein the second voltage range encodes information that a successor is connected to the first bus participant, the successor is supplied with a supply voltage, and whose input is not activated; wherein the fourth voltage range encodes information that a termination plug is connected to the first bus participant, and that the output is electrically connected to ground.

36. The method according to claim 34, wherein depending on the detected voltage and depending on an activation state of the output of the first bus device, a respective state and/or an error state is reported by the first bus participant or an assignment of an address is requested and/or receipt of the address is acknowledged by the successor.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG. 1 schematically illustrates a bus system including a controller 1 and serially arranged bus participants 2, e.g., inverters, and a terminating plug.

[0033] FIG. 2 schematically illustrates two bus participants 2, in which the output OUT of a first bus participant 2 is connected to the input IN of a second bus participant 2.

[0034] FIG. 3 schematically illustrates a circuit arrangement between the input IN and the output OUT in a bus participant 2.

DETAILED DESCRIPTION

[0035] As schematically illustrated in FIGS. 1 to 3, an output OUT of the controller 1 is connected to an input IN of a first of the bus participants 2, which in turn is connected to another bus participant 2. A terminating plug 3 is connected directly to its output OUT or one or more bus participants 2 provided in series, and the terminating plug 3 is connected to the last of the bus participants.

[0036] Each bus participant 2 has a circuit arrangement between its input IN and its output OUT.

[0037] As shown in FIG. 2, this circuit arrangement has a resistor R4 arranged between the output OUT of the bus participant 2 and a terminal carrying an upper potential of a supply voltage U_REF. This upper potential is only present if a corresponding supply voltage source is present.

[0038] In addition, this circuit arrangement has a resistor R2, which is arranged between the input IN of the bus participant 2 and ground, e.g., a terminal carrying a lower potential of a supply voltage U_REF.

[0039] The two resistors R2 and R4 are, for example, selected to be of equal size.

[0040] Moreover, the circuit arrangement has a voltage sensing device, which senses the voltage applied to the resistor R2. If no voltage supply is present, the voltage sensing device has the input resistor of the voltage sensing device connected in parallel with resistor R2, such that the voltage divider formed by resistor R4 and resistor R2 together with the input resistor steps down the voltage further, than when the input resistor is absent.

[0041] The voltage detection device detects the voltage applied to IN_UC.

[0042] An input protection circuit is formed by a capacitor C1, a resistor R5, a resistor R6, and a diode bridge device V2. For this purpose, the capacitor C1 is arranged between the input of the voltage sensing device and ground, such that a short circuit for high frequency is formed and the voltage to be measured smoothed.

[0043] The diode bridge arrangement V2 has two series circuits connected in parallel with one another, and each of the series circuits has two diodes connected in series. The series circuits are powered by the supply voltage, and the diodes are arranged in the reverse direction, when the upper potential is above ground.

[0044] The output OUT is connected to the junction node of the two diodes of the first series circuit via the resistor R5. Between this connection node and ground, a series circuit is formed by the two resistors R6 and R2.

[0045] The input IN is connected to the connection node, to which the two resistors R6 and R2 are connected.

[0046] An output protection circuit is formed by a capacitor C2, a resistor R7, a resistor R8, and the diode bridge device V2, e.g., the second series circuit of the diode bridge device V2. For this purpose, the capacitor C2 is arranged between the input of the voltage sensing device and ground, such that a short circuit for high frequency is formed and the voltage to be measured smoothed.

[0047] The output OUT is connected to the junction node of the two diodes of the first series circuit via the resistor R7. Resistor R8 is located between this connection node and the second capacitor C2. The output OUT is connected to the supply voltage via the resistor R4.

[0048] By controlling a second controllable semiconductor switch T2, e.g., a transistor, the output OUT is connected to the supply voltage via the resistor R3. Since the resistor R3 is connected in parallel with the resistor R4, the effective resistance between the output OUT and the supply voltage is, in each case, halved for the same dimensioning. When connecting the subsequent bus subscriber 2, i.e., the output OUT with the input IN of the subsequent bus subscriber 2, the voltage divider formed by the series connection of the parallel circuit formed by the resistors R3 and R4 with the resistor R2 of the subsequent bus subscriber 2 steps down the supply voltage to two thirds of the supply voltage.

[0049] If the terminating plug 3 is connected to the output OUT, i.e., the output OUT is directly electrically connected to ground, a voltage of 0 volts, or at least close to 0 volts, is detected. Thus, the terminating plug 3 can be identified.

[0050] However, if no subsequent bus participant 2 is connected to the output OUT and the output OUT is therefore open, the bus participant 2 can transmit this information to its predecessor by connecting the input IN to the supply voltage via the resistor R1 by controlling a first controllable semiconductor switch T1, e.g., a transistor. Thus, the voltage divider formed with the resistor R4 of the predecessor results in a stepped-down voltage at input IN of two-thirds of the supply voltage, when the predecessor has yet to activate its second transistor T2. However, its second transistor T2 has been activated, a stepdown to three quarters of the supply voltage occurs due to the voltage divider. This is because the voltage divider is formed from a series circuit, and the resistor R2 of the bus subscriber is connected in series with the parallel circuit, which has the resistors R1 of the bus subscriber and the resistors R3 and R4 of the predecessor.

[0051] Thus, by controlling the first controllable semiconductor switch T1 of the predecessor of a bus participant 2, an address assignment to the bus participant 2 may be initiated.

[0052] By activating the second controllable semiconductor switch T2 of the bus participant 2 and then connecting the successor to the bus participant 2, whereby the first controllable semiconductor switch T1 of the successor is activated, three quarters of the supply voltage at the output OUT of the bus participant 2 can therefore be produced. When the first controllable semiconductor switch T1 of the successor is not activated, two thirds of the supply voltage can be produced at the output OUT. This allows for the connection of the successor to the bus participant 2 to be identified. Since the bus participants 2 are connected to one another by a data link, which leads to the controller 1, it is possible to determine whether a successor has been additionally connected, whereupon the controller 1 assigns an address, i.e., a bus address, to the successor as the new additional bus participant 2.

[0053] The control of the first controllable semiconductor T1 can be implemented at the output IN_UC_N, and the control of the second controllable semiconductor switch T2 can be implemented at the output OUT_UC_N.

[0054] If the resistors R1, R2, R3, R4, R6, R7 are of the same values, the following behavior results:

[0055] If no successor is connected to bus participant 2, the full supply voltage can be detected at the output OUT of bus participant 2, i.e., a voltage of a first voltage value range.

[0056] If a successor is connected to bus participant 2 and supplied with a supply voltage, two thirds of the supply voltage can be detected at the output OUT of bus participant 2, i.e., a voltage of a second voltage value range. The controllable semiconductor switches T1 and T2 are not controlled.

[0057] If a successor is connected to bus participant 2, but not supplied with a supply voltage, then half the supply voltage is detectable at the output OUT of bus participant 2, i.e., a voltage of a third voltage value range.

[0058] If a successor is connected to bus participant 2 and provided with a supply voltage, then two thirds of the supply voltage can be detected at the output OUT of bus participant 2 by controlling the second controllable semiconductor switch T2 of the bus participant, i.e., a voltage of a second voltage value range, when semiconductor switch T2 is activated, i.e., when it is set to the conductive state. When detecting this voltage, the successor is ready to receive, and awaits the address sent by the controller 1, e.g., as a broadcast. In this manner, the successor is assigned its address, i.e., its bus address.

[0059] If a vanishingly small voltage, e.g., zero, is detectable at the output of bus participant 2, a terminating plug 3 has been detected. The vanishingly small voltage is therefore of a fourth range of voltage values.

[0060] In addition, it is possible for the successor to activate its first controllable semiconductor switch T1 and thus generate at its input IN, i.e., also at the output OUT of the bus subscriber, two thirds of the supply voltage, i.e., a voltage of the second voltage range, if the second controllable semiconductor switch T2 of the bus participant has yet to be activated, or three quarters of the supply voltage, i.e., a voltage, which is between the second voltage range and the first voltage range, if the second controllable semiconductor switch T2 of the bus participant has been activated.

[0061] The first voltage range is above the second voltage range.

[0062] The second voltage range is above the third voltage range.

[0063] The third voltage range is above the fourth voltage range.

[0064] If the resistors R1, R2, R3, R4, R6, R7 are of the same values, different voltage values result, whereby only the arrangement and the voltage range are relevant for the functioning of the system described herein.

[0065] The four diodes V2 of the circuit arrangement are, for example, arranged, such that they can be integrated in a common component. Likewise, the first and second controllable semiconductor switches are arranged in an integrated manner in a common component. Therefore, the circuit arrangement may be achieved by a printed circuit board, which is equipped with the two components and the resistors, especially by using SMD technology. Additionally, the resistors are also integrated in a common third component, such that the circuit arrangement can be produced in a very compact fashion.

LIST OF REFERENCE CHARACTERS

[0066] 1 Control

[0067] 2 Bus participants, e.g., inverters

[0068] 3 Termination plug

[0069] R1 Third resistor

[0070] R2 Second resistor

[0071] R3 Fourth resistor

[0072] R4 First resistor

[0073] R5 Resistance

[0074] R6 Resistor

[0075] C1 Capacitor

[0076] C2 Capacitor

[0077] C3 Capacitor

[0078] T1 First controllable switch

[0079] T2 Second controllable switch

[0080] IN Input

[0081] OUT Output

[0082] IN_UC control input

[0083] OUT_UC control input

[0084] U_Ref supply voltage