WAFER LEVEL PROXIMITY SENSOR AND METHOD OF MAKING SAME

Abstract

Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate wafer to form a bonded wafer sandwich, and then selectively thinning the silicon substrate wafer and silicon cap wafer. The silicon substrate wafer is thinned first, and an interconnect structure of through-silicon vias is formed within the thinned silicon substrate wafer. The silicon cap wafer is then thinned to expose openings facing an area of the thinned silicon substrate wafer where a photosensitive region is location and facing an area of the thinned silicon substrate wafer where an emitter die is to be installed. After emitter die installation, the openings in the thinned silicon cap wafer are filled with a transparent material. The thinned silicon cap wafer further includes an opaque light barrier to block light transmission between the openings.

Claims

1. A method, comprising: at each of a plurality of integrated circuit areas for a silicon integrated circuit substrate wafer, forming at least one photosensitive region and at least one front connection pad; forming a plurality of first trenches and a plurality of second trenches in a silicon cap wafer; providing an opaque light barrier at the silicon cap wafer to block light transmission through the silicon cap wafer between the first and second trenches; wafer-to-wafer bonding of the silicon cap wafer to the silicon integrated circuit substrate wafer to form a bonded wafer sandwich, where an opening of each first trench in the silicon cap wafer faces a corresponding photosensitive region of the silicon integrated circuit substrate wafer and wherein an opening of each second trench in the silicon cap wafer faces a corresponding front connection pad of the silicon integrated circuit substrate wafer; then, performing a back grind to thin the silicon integrated circuit substrate wafer of the bonded wafer sandwich; forming through silicon vias in the thinned silicon integrated circuit substrate wafer, wherein at least some of the through silicon vias are electrically connected to said at least one photosensitive region in each of the plurality of integrated circuit areas; then, performing a back grind to thin the silicon cap wafer and expose the openings of the first and second trenches; installing a light emitter integrated circuit die in the opening for each second trench mounted to the thinned silicon integrated circuit substrate wafer and electrically connected to said at least one front connection pad; filling the openings of the first and second trenches with a transparent material; and cutting through the bonded wafer sandwich between adjacent integrated circuit areas in a singulation operation to produce a plurality of individual wafer level micro-sensor modules.

2. The method of claim 1, wherein providing the opaque light barrier comprises lining sidewalls and a bottom of each first trench and each second trench with an opaque material layer.

3. The method of claim 1, wherein providing the opaque light barrier comprises forming a trench in an upper surface of the silicon cap wafer between the first and second trenches, and filling the trench with an opaque material to form an opaque material block between the first and second trenches.

4. The method of claim 1, wherein providing the opaque light barrier comprises forming an annular trench in an upper surface of the silicon cap wafer around each of the first and second trenches, and filling the annular trench with an opaque material to form an opaque material ring around each of the first and second trenches.

5. The method of claim 1, further comprising: covering each photosensitive region with a protective layer before wafer-to-wafer bonding; and removing the protective layer after performing the back grind to thin the silicon cap wafer.

6. The method of claim 1, further comprising, after filling the openings of the first and second trenches with the transparent material, covering an upper surface of the thinned silicon cap wafer with a patterned layer of opaque material that includes apertures over each of the transparent material filled openings of the first and second trenches.

7. A device, comprising: an integrated circuit substrate including at least one photosensitive region and at least one front connection pad; a silicon cap wafer-bonded to the integrated circuit substrate, said silicon cap including a first opening extending through a thickness of the silicon cap at said at least one photosensitive region and further including a second opening extending through the thickness of the silicon cap at an area where said at least one front connection pad is located; wherein said silicon cap further includes an opaque light barrier to block light transmission through the silicon cap wafer between the first and second openings; a light emitter integrated circuit die mounted to the integrated circuit substrate at said area in the second opening and electrically connected to said at least one front connection pad; and a transparent material fill in each of the first and second openings.

8. The device of claim 7, wherein said opaque light barrier comprises an opaque material layer lining sidewalls of each first opening and each second opening.

9. The device of claim 7, wherein said opaque light barrier comprises a trench in an upper surface of the silicon cap between the first and second openings, and an opaque material fill in the trench to form an opaque material block between the first and second openings.

10. The device of claim 7, wherein said opaque light barrier comprises an annular trench in an upper surface of the silicon cap surrounding each of the first and second openings, and an opaque material fill in each annular trench to form an opaque material ring surrounding each of the first and second openings.

11. The device of claim 7, further comprising a patterned layer of opaque material covering an upper surface of the silicon cap, said patterned layer of opaque material including apertures over each of the first and second openings that are filled with transparent material.

12. A smart phone that includes the device of claim 7.

13. A touch screen for an electronic device, wherein the touch screen integrates the device of claim 7.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0012] For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

[0013] FIG. 1 is a cross-sectional view of a conventional time of flight (ToF) proximity micro-sensor module;

[0014] FIG. 2 is a cross-sectional view of a conventional wafer level ToF proximity micro-sensor module;

[0015] FIGS. 3A-3C are cross-sectional views of a wafer level ToF proximity micro-sensor module;

[0016] FIGS. 4A-4K shows steps of a method for manufacturing the wafer level ToF proximity micro-sensor module of FIG. 3A; and

[0017] FIGS. 5 and 6 each show a process step as a replacement for the process step of FIG. 4C in connection with manufacturing the micro-sensor module 300 shown in FIGS. 3B and 3C, respectively.

DETAILED DESCRIPTION

[0018] In the following description, certain specific details are set forth in order to provide a thorough understanding of various aspects of the disclosed subject matter. However, the disclosed subject matter may be practiced without these specific details. In some instances, well-known structures and methods of semiconductor processing comprising embodiments of the subject matter disclosed herein have not been described in detail to avoid obscuring the descriptions of other aspects of the present disclosure.

[0019] Reference throughout the specification to forming layers may entail the use of conventional thin film deposition techniques for depositing insulating and/or conductive and/or semiconductive materials, including such processes as chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), metal organic chemical vapor deposition (MOCVD), plasma-enhanced chemical vapor deposition (PECVD), plasma vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), electroplating, electro-less plating, and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. For example, in some circumstances, a description that references CVD may alternatively be done using PVD, or a description that specifies electroplating may alternatively be accomplished using electro-less plating.

[0020] Reference throughout the specification to conventional photolithography techniques, known in the art of semiconductor fabrication for patterning various thin films, may include a spin-expose-develop process sequence typically followed by an etch process. Alternatively or additionally, photoresist can also be used to pattern a hard mask, e.g., a silicon nitride hard mask, which, in turn, can be used to pattern an underlying film.

[0021] Reference throughout the specification to conventional etching techniques known in the art of semiconductor fabrication for selective removal of polysilicon, silicon nitride, silicon dioxide, metals, photoresist, polyimide, or similar materials includes such processes as wet chemical etching, reactive ion (plasma) etching (RIE), washing, wet cleaning, pre-cleaning, spray cleaning, chemical-mechanical planarization (CMP) and the like. Specific embodiments are described herein with reference to examples of such processes. However, the present disclosure and the reference to certain deposition techniques should not be limited to those described. In some instances, two such techniques may be interchangeable. For example, stripping photoresist may entail immersing a sample in a wet chemical bath or, alternatively, spraying wet chemicals directly onto the sample.

[0022] Reference is now made to FIG. 3A which shows a cross-sectional view of a wafer level ToF proximity micro-sensor module 300. The wafer level proximity micro-sensor module 300 is fabricated as an integrated sensor package. Details of the wafer level manufacturing process are provided below and illustrated in FIGS. 4A-4K. Briefly, a silicon integrated circuit substrate wafer 302 and a silicon cap wafer 304 are processed separately. The separate wafers 302, 304 are then bonded to form a bonded wafer sandwich. Upper and lower surfaces of the bonded wafer sandwich are then processed further, and finally, the bonded wafer sandwich is singulated into the individual proximity micro-sensor modules 300.

[0023] The module 300 includes a sensor integrated circuit die 312 formed from the silicon integrated circuit substrate wafer 302. The sensor integrated circuit die 312 includes a first photosensitive region 316 and a second photosensitive region 318. Through silicon vias 313 form an electrical connection network 310 for electrically connecting front connection pads 306 of the sensor integrated circuit die 312 to a redistribution layer on the back side of the sensor integrated circuit die 312 which includes rear connection pads 308. An emitter integrated circuit die 314 is mounted to the front surface of the sensor integrated circuit die 312 and electrically connected to the front connection pads 306. The module 300 further includes a silicon cap 324 mounted to the sensor integrated circuit die 312. Openings are provided in the silicon cap 324 generally vertically aligned with the locations of the first photosensitive region 316 for the sensor integrated circuit die 312 and the photoemission region 320 of the emitter integrated circuit die 314. Sidewalls of the openings are lined with a layer 350 of opaque material (for example, a black oxide, a metal or other suitable material for blocking infrared light) to address issues with light cross-talk between the photosensitive regions. The layer 350 may be molded within the openings or deposited using a conformal deposition or plating process. Each of the openings is filled with a transparent material (such as, for example, a transparent epoxy) forming a transparent optical element 328.

[0024] The module 300 may further include a patterned layer 352 of opaque material (for example, a black oxide, a metal or other suitable material for blocking infrared light) on the top surface of the silicon cap 324 to block light intrusion into the silicon cap 324. The layer 352 may be molded to the top surface or deposited using a conformal deposition or plating process. The patterning of the opaque material layer 352 (performed using the molding operation or a lithography operation) defines optical apertures 354 aligned with the vertically aligned with the locations of the first photosensitive region 316 for the sensor integrated circuit die 312 and the photoemission region 320 of the emitter integrated circuit die 314.

[0025] Reference is now made to FIG. 3B which shows a cross-sectional view of a further embodiment of the wafer level ToF proximity micro-sensor module 300. Like references in FIGS. 3A and 3B refer to same parts. The embodiment in FIG. 3B differs from the embodiment in FIG. 3A in that the light cross-talk blocking function within the silicon cap 324 is provided in FIG. 3B by an opaque material block 354 (for example, a black oxide, a metal or other suitable material for blocking infrared light) positioned between the openings filled with the transparent optical elements 328a, 328b. The block 354 may be formed by filling a channel or opening in the silicon cap 324 with an opaque material. Again, this can be achieved by molding within openings or deposition using a conformal deposition or plating process.

[0026] Reference is now made to FIG. 3C which shows a cross-sectional view of another embodiment of the wafer level ToF proximity micro-sensor module 300. Like references in FIGS. 3A, 3B and 3C refer to same parts. The embodiment in FIG. 3C differs from the embodiments in FIGS. 3A and 3B in that the light cross-talk blocking function within the silicon cap 324 is provided in FIG. 3C by an opaque material ring 356 (for example, a black oxide, a metal or other suitable material for blocking infrared light) surrounding each of the openings filled with the transparent optical elements 328a, 328b. The ring 356 may be formed by filling an annular channel or opening in the silicon cap 324 with an opaque material. Again, this can be achieved by molding within openings or deposition using a conformal deposition or plating process.

[0027] In operation, light is emitted from the photoemission region 320 of the emitter integrated circuit die 314. A portion of this light is internally reflected within the transparent optical element 328a and detected by the second photosensitive region 318. It will be noted that the light barrier formed by the opaque material layer 350, opaque material block 354 or opaque material ring 356 blocks propagation of the emitted light through the silicon cap 324 towards the first photosensitive region 316. A further portion of the light propagates through the transparent optical element 328a to outside of the micro-sensor module 300 to illuminate a target object. Light reflected by the target object returns to the micro-sensor module 300, passes through the transparent optical element 328b, and is detected by the first photosensitive region 316. It will be noted that the light barrier formed by the opaque material layer 350, opaque material block 354 or opaque material ring 356 blocks propagation of the returned reflected emitted light through the silicon cap 324 towards the second photosensitive region 318. The sensor integrated circuit die 312 measures the difference in time between sensing of the internally refracted light by second photosensitive region 318 and the sensing by the first photosensitive region 316 of the returned light reflected by the target object, and then calculates the distance from micro-sensor module 300 to the target object as a function of the measured difference in time.

[0028] Reference is now made to FIGS. 4A-4K which show steps of a method of manufacturing the micro-sensor module 300 of FIG. 3A. These processing steps may further be used, with modification as described herein and shown in FIGS. 5 and 6, in connection with manufacturing the micro-sensor module 300 of FIGS. 3B and 3C.

[0029] FIG. 4Aa silicon integrated circuit substrate wafer 302 is fabricated using conventional techniques well known to those skilled in the art. The thickness of the wafer 302 may, for example, be in a range of 50-100 m. The wafer includes a plurality of integrated circuit areas 402 which are each fabricated to include front connection pads 306, a first photosensitive region 316 and a second photosensitive region 318. Sufficient vacant space is provided between adjacent integrated circuit areas 402 to permit singulation. Although the photosensitive regions 316, 318 and the front connection pads 306 are illustrated as being located at the upper surface of the silicon integrated circuit substrate wafer 302, it will be understood that this is by way of a simplified illustration, it being understood by those skilled in the art that the photosensors for the photosensitive regions 316, 318 are typically located at or within the semiconductor material of the wafer 302 and the front connection pads 306 are typically located in the metallization interconnect levels, which extend over the semiconductor material, of the wafer 302. The photosensitive regions 316, 318 may, for example, be formed by an array of photosensors (such as photodiodes or single photon avalanche diodes (SPADs)).

[0030] FIG. 4Busing conventional photolithographic processing techniques, an array of trenches 404a, 404b are etched in a silicon cap wafer 304. The wafer 304 may, for example, have a thickness in a range of 200-300 m. A chemical etching process may be used to open trenches 404 to a suitable depth. In a referred implementation, the trenches 404 have suitably sized rectangular or square profiles. The profiles may include, for example, rounded corners. The depth of the etched openings for trenches 404a, 404b is controlled to be less than the wafer 304 thickness. The size of the etched opening for trench 404a is controlled to exceed an area occupied by the second photosensitive region 318, certain ones of the front connection pads 306 and a space to be occupied by the emitter integrated circuit die 314 mounted to those certain ones of the front connection pads. The size of the etched opening for trench 404b is controlled to exceed an area occupied by the first photosensitive region 316. Sufficient space is provided between certain adjacent trenches 404 to permit singulation.

[0031] FIG. 4Ca layer 406 of opaque material is deposited on the sidewalls and bottoms of the trenches 404a, 404b. The material may, for example, comprise a black oxide, a metal or other suitable material for blocking infrared light. The layer 406 may be formed, for example, using a molding process or a conformal deposition or a plating process. A planarization process may be used to remove portions of the layer 406 on the top surface of the wafer 304. As discussed below, the process step shown in FIG. 5 or 6 could instead be used at this point of the method of manufacturing.

[0032] FIG. 4Dthe silicon cap wafer 304 is then flipped over and mounted to the upper surface of the silicon integrated circuit substrate wafer 302. Wafer-to-wafer bonding may be used to effectuate this mounting to form a bonded wafer sandwich. The bonding may, for example, utilize an adhesive (for example, epoxy) material. Alternatively, a molecular bonding process may be used. When mounting the silicon cap wafer 304 to the silicon integrated circuit substrate wafer 302, care is taken to align the opening for each trench 404a to the area of the silicon integrated circuit substrate wafer 302 where the second photosensitive region 318, certain ones of the front connection pads 306 and the space to be occupied by the emitter integrated circuit die 314 mounted to those certain ones of the front connection pads are located. Furthermore, when mounting the silicon cap wafer 304 to the silicon integrated circuit substrate wafer 302, care is taken to align the opening for each trench 404b to the area of the silicon integrated circuit substrate wafer 302 where the first photosensitive region 316 is located.

[0033] FIG. 4Ea back grinding process is then applied to thin the silicon integrated circuit substrate wafer 302 of the bonded wafer sandwich to define the thickness for the sensor integrated circuit die 312. The thinned thickness of wafer 302 is selected to suit subsequent processing operations (see, the step of FIG. 4F, for example) and is less than original wafer thickness. It will be noted that the full thickness of the silicon cap wafer 304 is present at this point of the manufacturing process to provide rigidity to the bonded wafer sandwich during the back grind performed on the silicon integrated circuit substrate wafer 302.

[0034] FIG. 4Fthrough-silicon vias 313 and the rear connection pads 308 of the electrical connection network 310 are then formed in the thinned silicon integrated circuit substrate wafer 302 of the bonded wafer sandwich. The electrical connection network 310 may also include a redistribution layer on the back surface of the thinned silicon integrated circuit substrate wafer 302. The through-silicon vias 313 extend completely through the thinned thickness of the silicon integrated circuit substrate wafer 302 from the rear connection pads 308 to the front connection pads 306. The through-silicon vias 313 may be formed using any suitable through-silicon via fabrication process as is known to those skilled in the art. It will be noted that the full thickness of the silicon cap wafer 304 remain present at this point of the manufacturing process to provide rigidity to the bonded wafer sandwich during the through-silicon via fabrication process.

[0035] The presence of the full thickness of the silicon cap wafer 304 during the manufacturing steps of FIGS. 4E and 4F is important since it minimizes the risk of damaging the silicon integrated circuit substrate wafer 302 of the bonded wafer sandwich.

[0036] FIG. 4Ga back grinding process is then applied to thin the silicon cap wafer 304 of the bonded wafer sandwich to define the thickness of the silicon cap 324 and expose the openings for trenches 404a, 404b. The thinned thickness of wafer 304 is selected to suit subsequent processing operations and is less than original wafer thickness. For the case of the implementations shown in FIGS. 5 and 6, this back grind on the silicon cap wafer 304 of the bonded wafer sandwich would further reach the opaque material filled trenches 430, 432 providing the block 354 and rings 356, respectively.

[0037] It will be noted that a protective material layer (schematically shown by a dot-dash line) may be deposited to cover and protect each of the photosensitive regions 316, 318 in conjunction with the substrate wafer 302 fabrication in the manufacturing step shown in FIG. 4A. This protective material layer serves to protect the regions 316, 318 damage or contamination as a result of performing the back grind of the manufacturing step shown in FIG. 4G. At any suitable point following the FIG. 4G back grind and before the subsequent filling of the openings for trenches 430, 432 in the manufacturing step of FIG. 4I below, this protective material layer may be removed through a selective etch or clean process. The protective material layer may, for example, comprise a water soluble layer that is easily removed. Alternatively, a layer of organic material may be used.

[0038] FIG. 4Hemitter integrated circuit dies 314 are then mounted to the upper surface of the silicon integrated circuit substrate wafer 302 in the exposed openings for the trenches 404a and electrically connected to the front connection pads 306. The emitter integrated circuit dies 314 may, for example, comprise semiconductor-based vertical cavity surface-emitting laser (VCSEL) diodes. Although not specifically illustrated, the electrical connection my be made using soldering and/or wire bonding to the front connection pads 306.

[0039] FIG. 4Ithe exposed openings for the trenches 404a and 404b are then filled with a transparent material (such as a transparent epoxy) to form the transparent optical elements 328. After filling, a planarization process may be performed to remove excess transparent material located on the top surface of the thinned silicon cap wafer 304.

[0040] FIG. 4Ja patterned layer 352 of opaque material is then deposited on the top surface of the silicon cap 324 and partially covering the transparent optical elements 328. This layer 352 may, for example, comprise a black oxide, a metal or other suitable material for blocking infrared light. The layer 352 may be formed by molding or deposition. The patterning of the opaque material layer 352 (through the molding process or a lithographic process) defines optical apertures 354 aligned with the vertically aligned with the locations of the first photosensitive region 316 for the sensor integrated circuit die 312 and the photoemission region 320 of the emitter integrated circuit die 314. Additionally, solder balls are attached to the rear connection pads 308. The solder balls may be arranged, for example, in ball grid array pattern

[0041] FIG. 4Ka singulation, or dicing, process 460 is then performed on the thinned bonded wafer sandwich to cut through the stacked and thinned wafers between the integrated circuit areas 402 and produce individual wafer level proximity micro-sensor modules 300. It will be noted that attachment of solder balls may instead be performed after singulation.

[0042] Additionally, an optical filter layer and/or optical lens may be mounted to extend over each optical aperture 354.

[0043] Reference is now made to FIG. 5 which shows a process step as a replacement for the process step of FIG. 4C in connection with manufacturing the micro-sensor module 300 shown in FIG. 3B. Here, instead of using the opaque layer 406 lining the openings for the trenches 404a and 404b, a trench 430 is formed in the upper surface of the silicon cap wafer 304 between the openings for the trenches 404a and 404b, and this trench 430 is filled with an opaque material to form the block 354. The opaque material may, for example, comprise for example, a black oxide, a metal or other suitable material for blocking infrared light. Preferably, the opaque material is provided using a molding process. A trench etch and fill process could instead be used.

[0044] Reference is now made to FIG. 6 which shows a process step as a replacement for the process step of FIG. 4C in connection with manufacturing the micro-sensor module 300 shown in FIG. 3C. Here, instead of using the opaque layer 406 lining the openings for the trenches 404a and 404b, trenches 432a, 432b are formed in the upper surface of the silicon cap wafer 304 annularly surrounding the openings for the trenches 404a and 404b, respectively. These trenches 432a, 432b are filled with an opaque material to form the rings 356. The opaque material may, for example, comprise for example, a black oxide, a metal or other suitable material for blocking infrared light. Preferably, the opaque material is provided using a molding process. A trench etch and fill process could instead be used.

[0045] In a preferred implementation, the micro-sensor module 300 is a component of a electronic device such as a smart phone. More specifically, the micro-sensor module 300 may, for example, be integrated into or with a touch screen of the electronic device.

[0046] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.