RRAM STRUCTURE AND METHOD OF FABRICATING THE SAME

Abstract

An RRAM structure includes a bottom electrode, a resistive switching layer, a top electrode, a spacer and a conductive line. The bottom electrode is a first cylinder. The resistive switching layer includes a second cylinder and a three-dimensional disk. A first bottom of the second cylinder directly contacts a top surface of the three-dimensional disk. The top electrode is a third cylinder. The third cylinder includes a top base, a second bottom base and a sidewall. The first cylinder is embedded within the second cylinder and the three-dimensional disk. The second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk. The spacer surrounds and directly contacts a side surface of the three-dimensional disk. The conductive line encapsulates the top base and the sidewall of the third cylinder.

Claims

1. A resistive random access memory (RRAM) structure, comprising: a bottom electrode, wherein the bottom electrode is a first cylinder; a resistive switching layer comprising a second cylinder and a three-dimensional disk, wherein a first bottom base of the second cylinder directly contacts a top surface of the three-dimensional disk; a top electrode, wherein the top electrode is a third cylinder, wherein the third cylinder comprises a top base, a second bottom base and a sidewall, the first cylinder is embedded within the second cylinder and the three-dimensional disk, the second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk; a spacer surrounding and directly contacting a side surface of the three-dimensional disk; and a conductive line encapsulating the top base and the sidewall of the third cylinder.

2. The RRAM structure of claim 1, wherein a diameter of the top surface of the three-dimensional disk is larger than a diameter of the first bottom base.

3. The RRAM structure of claim 1, wherein the spacer completely covers the side surface of the three-dimensional disk.

4. The RRAM structure of claim 1, wherein the spacer covers and contacts the sidewall of the third cylinder.

5. The RRAM structure of claim 1, further comprising: a first dielectric layer; a conductive plug embedded within the first dielectric layer; a second dielectric layer covering the first dielectric layer and the conductive plug; and a third dielectric layer covering the second dielectric layer, wherein the bottom electrode penetrates the second dielectric layer and directly contacts the conductive plug, the resistive switching layer and the spacer are disposed on the second dielectric layer, the third dielectric layer surrounds the spacer and the third dielectric layer directly contacts the conductive line.

6. The RRAM structure of claim 1, wherein the resistive switching layer comprises an oxygen atom storage layer and a current formation layer, the current formation layer is disposed on the oxygen atom storage layer, the oxygen atom storage layer comprises tantalum oxide (TaO.sub.x, x<2.5), and the current formation layer comprises tantalum pentoxide (Ta.sub.2O.sub.5).

7. The RRAM structure of claim 1, wherein the conductive line comprises copper, aluminum or tungsten.

8. The RRAM structure of claim 1, wherein the bottom electrode comprises tantalum, titanium, titanium nitride or tantalum nitride.

9. The RRAM structure of claim 1, wherein the top electrode comprises iridium, titanium nitride or tantalum nitride.

10. The RRAM structure of claim 1, wherein the spacer comprises silicon nitride.

11. A fabricating method of a resistive random access memory (RRAM) structure, comprising: forming a bottom electrode, a resistive switching layer and a top electrode in sequence, wherein the bottom electrode is a first cylinder, the resistive switching layer comprises a second cylinder and a three-dimensional disk, the top electrode is a third cylinder, and the third cylinder includes a top base, a second bottom base and a sidewall forming a spacer surrounding the resistive switching layer; and forming a conductive line encapsulating and directly contacting the top base and the sidewall of the third cylinder.

12. The fabricating method of an RRAM structure of claim 11, wherein a first bottom base of the second cylinder directly contacts a top surface of the three-dimensional disk, the first cylinder is embedded within the second cylinder and the three-dimensional disk, the second cylinder is embedded within the third cylinder and the second bottom base of the third cylinder directly contacts the top surface of the three-dimensional disk.

13. The fabricating method of an RRAM structure of claim 11, wherein steps of forming the bottom electrode, the resistive switching layer and the top electrode comprise: forming a dummy material layer; etching the dummy material layer to form a hole; forming the bottom electrode to fill in the hole; removing the dummy material layer; forming a resistive switching material layer and a top electrode material layer in sequence to cover the bottom electrode; and patterning the top electrode material layer and the resistive switching material layer to form the top electrode and the resistive switching layer.

14. The fabricating method of an RRAM structure of claim 13, further comprising: after forming the top electrode, the resistive switching layer and the bottom electrode, forming a spacer material layer covering the top electrode, the resistive switching layer and the bottom electrode; and etching the spacer material layer to form the spacer.

15. The fabricating method of an RRAM structure of claim 13, further comprising: after forming the spacer, forming a dielectric layer to cover the top electrode, the resistive switching layer, the bottom electrode and the spacer; etching the dielectric layer to expose the top electrode; and forming the conductive line to cover the top electrode.

16. The fabricating method of an RRAM structure of claim 11, wherein the resistive switching layer comprises an oxygen atom storage layer and a current formation layer, the current formation layer is disposed on the oxygen atom storage layer, the oxygen atom storage layer comprises tantalum oxide (TaO.sub.x, x<2.5), and the current formation layer comprises tantalum pentoxide (Ta.sub.2O.sub.5).

17. The fabricating method of an RRAM structure of claim 11, wherein the conductive line comprises copper, aluminum or tungsten.

18. The fabricating method of an RRAM structure of claim 11, wherein the bottom electrode comprises tantalum, titanium, titanium nitride or tantalum nitride.

19. The fabricating method of an RRAM structure of claim 11, wherein the top electrode comprises iridium, titanium nitride or tantalum nitride.

20. The fabricating method of an RRAM structure of claim 11, wherein the spacer comprises silicon nitride.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1 depicts a three-dimensional diagram of an RRAM according to a preferred embodiment of the present invention.

[0009] FIG. 2 depicts an exploded view of FIG. 1.

[0010] FIG. 3 depicts a three-dimensional diagram of an RRAM structure according to a preferred embodiment of the present invention.

[0011] FIG. 4 to FIG. 10 are schematic diagrams of a fabricating process of an RRAM structure according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION

[0012] FIG. 1 depicts a three-dimensional diagram of an RRAM according to a preferred embodiment of the present invention. FIG. 2 depicts an exploded view of FIG. 1. FIG. 3 depicts a three-dimensional diagram of an RRAM structure according to a preferred embodiment of the present invention.

[0013] As shown in FIG. 1 and FIG. 2, an RRAM 100 includes a bottom electrode BE, a resistive switching layer R, a top electrode TE and a spacer S. The bottom electrode BE is a solid first cylinder 10. The resistive switching layer R includes a second cylinder 12 and a three-dimensional disk 14. The second cylinder 12 has an accommodating space 12d for accommodating the bottom electrode BE, and a first bottom base 12 of the second cylinder 12 directly contacts a top surface 14b of the three-dimensional disk 14. The diameter of the top surface 14b of the three-dimensional disc 14 is greater than the diameter of the first bottom base 12a. The top electrode TE is a third cylinder 16. The third cylinder 16 includes a top base 16b, a second bottom base 16a and a sidewall 16c, and the third cylinder 16 also has an accommodating space 16d. The first cylinder 10 passes through the three-dimensional disk 14 and is embedded in the accommodating space 12d of the second cylinder 12. The second cylinder 12 is embedded in the accommodating space 16d of the third cylinder 16. The second bottom base 16a of the third cylinder 16 directly contacts the top surface 14b of the three-dimensional disk 14. The spacer S surrounds and directly contacts a side surface 14c of the three-dimensional disk 14, and part of the sidewall 16c of the third cylinder 16. That is to say, the spacer S entirely covers a sidewall of the resistive switching layer R aligning with the top electrode TE and an interface between the resistive switching layer R and the top electrode TE. In this way, the resistive switching layer R is kept from being exposed to the environment, thus oxidation of the resistive switching layer R can be prevented and moisture can also be kept from getting into the resistive switching layer R. As shown in FIG. 3, a conductive line ML is disposed on the top electrode TE of the RRAM 100. In details, the conductive line ML encapsulates the top base 16b and the sidewall 16c of the third cylinder 16.

[0014] The bottom electrode BE includes tantalum, titanium, titanium nitride, tantalum nitride or other metal materials. The top electrode TE includes iridium, titanium nitride, tantalum nitride or other metal materials. The resistive switching layer R includes tantalum oxide, nickel oxide, hafnium oxide or other transition metal oxides. The spacer S includes silicon nitride. The conductive line ML includes copper, aluminum, tungsten or other metals or alloys.

[0015] FIG. 4 to FIG. 10 are schematic diagrams of a fabricating process of an RRAM structure according to a preferred embodiment of the present invention. The fabrication method of the RRAM 100 and the RRAM structure 200 shown in FIG. 1 to FIG. 3 will be described with reference to FIG. 4 to FIG. 10, wherein elements which are substantially the same as those in FIG. 1 to FIG. 3 are denoted by the same reference numerals; an accompanying explanation is therefore omitted.

[0016] As shown in FIG. 4, a dielectric layer 18a and a dielectric layer 18b are provided. The dielectric layer 18b covers the dielectric layer 18a, and a metal line 20 is disposed within the dielectric layer 18a. A conductive plug 22 is disposed in the dielectric layer 18b, and the conductive plug 22 contacts the metal line 20. Next, a dielectric layer 18c is formed to cover the dielectric layer 18b and contacts the conductive plug 22. The dielectric layer 18c can be nitrogen-doped carbide. Later, a dummy material layer 24 is formed to cover and contact the dielectric layer 18c. The dielectric layer 18a and the dielectric layer 18b may include silicon oxide, silicon nitride or other insulating materials. The metal line 20 and the conductive plug 22 may include copper, aluminum, tungsten or other conductive materials. The dummy material layer 24 includes silicon oxide.

[0017] Then, the dummy material layer 24 is etched to form a hole 24a, the hole 24a is preferably in a shape of a cylinder. Afterwards, a bottom electrode material layer (not shown) is formed to cover the dummy material layer 24 and fill in the hole 24a. Subsequently, the bottom electrode material layer is planarized to remove the bottom electrode material layer outside the hole 24a. Now, the bottom electrode material layer remaining in the hole 24a serves as the bottom electrode BE. As shown in FIG. 5, the dummy material layer 24 is removed. Now, the bottom electrode BE protrudes from the dielectric layer 18c. Afterwards, a resistive switching material layer R1 and a top electrode material layer TE1 are sequentially formed to conformally cover the bottom electrode BE and the dielectric layer 18c. According to a preferred embodiment of the present invention, the resistive switching material layer R1 includes an oxygen atom storage material layer 26a and a current formation material layer 28a, the current formation material layer 28a is disposed on the oxygen atom storage material layer 26a. In details, the oxygen atom storage material layer 26a includes tantalum oxide (TaO.sub.x, x<2.5), and the current formation material layer 28a includes tantalum pentoxide (Ta.sub.2O.sub.5).

[0018] As shown in FIG. 6, the top electrode material layer TE1 and the resistive switching material layer R1 are patterned to form a top electrode TE and a resistive switching layer R. The oxygen atom storage material layer 26a after patterning becomes an oxygen atom storage layer 26, and the current formation material layer 28a after patterning becomes a current formation layer 28a. It is added that: in FIG. 1 and FIG. 2, in order to make the illustrations clear and concise, the resistive switching layer R is shown as a single layer. In fact, in the embodiment of the present invention, the resistive switching layer R preferably includes the oxygen atom storage layer 26 and the current formation layer 28 shown in FIG. 6. Furthermore, when viewing from a sectional view, the top electrode TE forms an inverted U shape, and the resistive switching layer R forms a square wave shape. The square wave shape includes an inverted U shape with a rectangular respectively connecting to two ends of the inverted U shape. The rectangular extends toward a lateral direction X, and the lateral direction X is parallel to a top surface of the dielectric layer 18c.

[0019] As shown in FIG. 7, a spacer material layer S1 is formed to cover the top electrode TE, the resistive switching layer R and the bottom electrode BE. As shown in FIG. 8, the spacer material layer S1 is etched to form a spacer S. The height of the spacer S should not less than a vertical sidewall of the rectangular at the end of the inverted U shape of the resistive switching layer R. Preferably, the height of the spacer S needs to be greater than the thickness of the resistive switching layer R. That is, the spacer S needs to completely cover the vertical sidewall of the rectangular at the end of the inverted U shape of the resistive switching layer R. According to a preferred embodiment of the present invention, the spacer S can further extend to contact the sidewall of the top electrode TE. In other words, the spacer S completely covers the interface between the resistive switching layer R and the top electrode TE. Now, an RRAM 100 of the present invention is completely. As shown in FIG. 9, a dielectric layer 18d is formed to cover the top electrode TE, the resistive switching layer R, the bottom electrode BE and the spacer S. The dielectric layer 18d is preferably silicon oxide. As shown in FIG. 10, the dielectric layer 18d is etched to expose the top electrode TE. In details, the dielectric layer 18d is etched to form a trench (not shown), so that the top electrode TE is exposed through the bottom of the trench. Next, a conductive line ML is formed to fill the trench and cover the top electrode TE. When viewing from a sectional view, the conductive line ML contacts the inverted U shape formed by the top electrode TE. Now, an RRAM structure 200 of the present invention is completely. Moreover, the etching depth of the dielectric layer 18d can be adjusted according to different requirements. It is noteworthy that when etching the dielectric layer 18d, because the material of the spacer S and the material of the dielectric layer 18d are different, the spacer S is not etched during the etching process. Therefore, even the top electrode TE is completely exposed in the etching process, the spacer S can still protect the resistive switching layer R from been damaged during the etching process. In a preferred embodiment of the present invention, after etching the dielectric layer 18d to form the trench, the thickness of the remaining dielectric layer 18d at the bottom of the trench is still greater than the height of the spacer S to keep the spacer S from exposing through the dielectric layer 18d at the bottom of the trench. However, in other embodiments, the dielectric layer 18d may be etched to expose a portion of the spacer S.

[0020] In the present invention, the conductive line ML covers the top base 16b and the sidewall 16c of the third cylinder 16 formed by the top electrode TE, so that the contact area between the top electrode TE and the conductive line ML increases. In this way, during a forming process of the RRAM 100, current is increased, and the forming process of the RRAM 100 can be performed more quickly. In addition, conductive filaments can be formed between the circumference of the second cylinder 12 and the bottom electrode BE and between the bottom electrode BE and a first top base 12b of the second cylinder 12. Therefore, as the total amount of conductive filaments increase, the resistance of the low resistance state of the RRAM 100 is smaller than the resistance of the low resistance state of the general RRAM. In this way, the resistance difference between the high resistance state and the low resistance state of the RRAM 100 of the present invention can be increased, and the retention and read/write endurance of the RRAM 100 can be increased.

[0021] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.