FRONT CONTACT SOLAR CELL WITH FORMED EMITTER

Abstract

A bipolar solar cell includes a backside junction formed by an N-type silicon substrate and a P-type polysilicon emitter formed on the backside of the solar cell. An antireflection layer may be formed on a textured front surface of the silicon substrate. A negative polarity metal contact on the front side of the solar cell makes an electrical connection to the substrate, while a positive polarity metal contact on the backside of the solar cell makes an electrical connection to the polysilicon emitter. An external electrical circuit may be connected to the negative and positive metal contacts to be powered by the solar cell. The positive polarity metal contact may form an infrared reflecting layer with an underlying dielectric layer for increased solar radiation collection.

Claims

1-20. (canceled)

21. A method of fabricating a solar cell having a silicon substrate with a front surface facing the sun to collect solar radiation during normal operation and a back surface opposite the front side, the method comprising: forming a tunnel oxide over both the front and back surfaces of the substrate; forming a polysilicon region on each of the tunnel oxides over both the front and back surfaces of the substrate; removing the polysilicon region and tunnel oxide formed on the front surface of the substrate; and diffusing a first dopant into the silicon substrate to form a diffusion region within the silicon substrate, the diffusion region proximate the front surface of the substrate.

22. The method of claim 21, further comprising: doping the polysilicon region over the back surface of the substrate with a second dopant, wherein the first and second dopants have opposite polarities.

23. The method of claim 21, wherein diffusing a first dopant comprises: diffusing the first dopant into a first region of the diffusion region; and diffusing the first dopant into a second region of the diffusion region, wherein the first region has a lower sheet resistance than the second region.

24. The method of claim 23, further comprising: forming a front metal contact over the front surface of the substrate, wherein the metal contact is in contact with the first region.

25. The method of claim 23, wherein the front metal contact is formed using a printing process.

26. The method of claim 23, wherein the first region is formed from a different dopant source than the second region.

27. The method of claim 24, wherein the front metal contact is narrower than the first region.

28. The method of claim 23, wherein the first region has a circular shape.

29. The method of claim 21, wherein the silicon substrate is an N-type silicon substrate.

30. The method of claim 21, wherein forming a polysilicon region comprises forming a polysilicon layer to a thickness of about 1000 to 2000 Angstroms by CVD.

31. The method of claim 22, wherein doping the polysilicon region comprises diffusing the second dopant into the polysilicon region.

32. The method of claim 21, wherein removing the polysilicon region and tunnel oxide comprises texturing the front surface of the substrate.

33. The method of claim 22, wherein texturing the front surface of the substrate comprises a wet etch process.

34. The method of claim 22, wherein texturing the front surface of the substrate forms random pyramids on the front surface.

35. The method of claim 21, further comprising forming a rear metal contact over the back surface of the substrate, wherein the rear metal contact is in contact with the polysilicon region over the back surface.

36. The method of claim 21, wherein forming a tunnel oxide comprises thermally growing a tunnel oxide layer to a thickness of about 10 to 50 Angstroms.

37. The method of claim 21, further comprising forming an edge isolation region on the back surface of and near an edge of the substrate, wherein the edge isolation region electrically isolates the polysilicon region and the tunnel oxide from the edge of the substrate.

38. The method of claim 37, wherein forming an edge isolation region comprises forming a trench through the polysilicon region and the tunnel oxide.

39. The method of claim 21, further comprising after removing the polysilicon region and tunnel oxide, forming a silicon nitride layer over the front surface of the substrate.

40. The method of claim 39, further comprising etching the silicon nitride layer to form holes in the silicon nitride layer.

Description

DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 schematically shows a cross-section of a solar cell in accordance with an embodiment of the present invention.

[0008] FIG. 2 is a plan view schematically showing the front side of the solar cell of FIG. 1.

[0009] FIG. 3 is a plan view schematically showing the backside of the solar cell of FIG. 1.

[0010] FIG. 4, which comprises FIGS. 4A-4M, schematically illustrates the fabrication of the solar cell of FIG. 1 in accordance with an embodiment of the present invention.

[0011] The use of the same reference label in different figures indicates the same or like components. The figures are not drawn to scale.

DETAILED DESCRIPTION

[0012] In the present disclosure, numerous specific details are provided, such as examples of apparatus, process parameters, materials, process steps, and structures, to provide a thorough understanding of embodiments of the invention. Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

[0013] FIG. 1 schematically shows a cross-section of a solar cell 100 in accordance with an embodiment of the present invention. The solar cell 100 has a front side where a metal contact 102 is located and a backside on a same side as the metal contact 110. The front side faces the sun during normal operation to collect solar radiation.

[0014] In the example of FIG. 1, the solar cell 100 includes a backside junction formed by a P-type doped polysilicon emitter 108 serving as a P-type diffusion region and an N-type silicon substrate 101 servings as an N-type diffusion region. The N-type silicon substrate 101 may comprise a long lifetime (e.g., 2 to 5 ms) N-type silicon wafer and may have a thickness of about 100 to 250 m as measured from the backside surface to a tip of the textured front side surface of the substrate. The front side surface of the substrate 101 is randomly textured (labeled as 113) and includes N-type doped regions 105 and 106 formed in the substrate. The N-type doped region 105 provides low front surface recombination and improves lateral conductivity whilst not compromising the blue response of the solar cell. The region 106, which may be a phosphorus diffusion, provides low contact resistance and minimizes contact recombination. The region 106 is also referred to as an N-dot because, in one embodiment, it forms a dot-shape to minimize the area of heavily diffused regions on the front surface. The N-type doped region 105 may have a sheet resistance of 100 to 500/sq, whilst the n-type doped region 106 may have a sheet resistance of 10 to 50/sq.

[0015] An antireflective coating (ARC) of silicon nitride layer 103 is formed on the textured front side surface of the substrate 101. The texture front side surface and the silicon nitride layer 103 help improve solar radiation collection efficiency. A passivating oxide 124 may comprise silicon dioxide thermally grown to a thickness of about 10 to 250 Angstroms on the front side surface of the substrate 101.

[0016] In one embodiment, the polysilicon emitter 108 is formed on a tunnel oxide layer 107. The polysilicon emitter 108 may be formed by forming a layer of polysilicon using Chemical Vapor Deposition (CVD), such as Low Pressure CVD (LPCVD) or Plasma Enhanced CVD (PECVD), and thermal anneal. The polysilicon emitter 108 may have a sheet resistance of 100/sq, and a thickness of 1000 to 2000 Angstroms. The tunnel oxide layer 107 may comprise silicon dioxide thermally grown to a thickness of about 10 to 50 Angstroms on the backside surface of the substrate 101. A metal contact 110 electrically connects to the polysilicon emitter 108 through contact holes 123 formed through a dielectric comprising a silicon dioxide layer 109. The metal contact 110 provides a positive polarity terminal to allow an external electrical circuit to be coupled to and be powered by the solar cell 100. The silicon dioxide layer 109 provides electrical isolation and allows the metal contact 110 to serve as an infrared reflecting layer for increased solar radiation collection. In one embodiment, the metal contact 110 comprises silver having a conductance of about 5-25 m.Math.cm and a thickness of about 15-35 m.

[0017] On the front side of the solar cell 100, the metal contact 102 electrically connects to the region 106 through a contact hole 120 formed through the silicon nitride layer 103. The metal contact 102 provides a negative polarity terminal to allow an external electrical circuit to be coupled to and be powered by the solar cell 100. In one embodiment, the metal contact 102 comprises silver having a sheet resistance of about 5 m.Math.cm and a thickness of about 15 m. The pitch between adjacent metal contacts 102 may be about 1 to 4 mm. In one embodiment, the metal contacts 102 are spaced at 400 to 1000 m along each metal contact 102 (see FIG. 2).

[0018] In the example of FIG. 1, the edge isolation trench 111 is formed through the silicon dioxide layer 109, the polysilicon emitter 108, and a portion of the substrate 101 to provide edge electrical isolation.

[0019] FIG. 2 is a plan view schematically showing the front side of the solar cell 100. In the example of FIG. 2, two bus bars 201 run parallel on the front side of the substrate 101. The contact holes 120, in which the metal contacts 102 are formed, may each have a diameter of about 50 to 200 m. A plurality of metal contacts 102 is formed perpendicular to the bus bars 201. Each metal contact 102 may have a width of about 60-120 m.

[0020] FIG. 3 is a plan view schematically showing the backside of the solar cell 100. In the example of FIG. 3, two bus bars 301, which are electrically coupled to metal contacts 110, run parallel on the backside. In practice, the bus bars 201 and 301 will be electrically connected to corresponding bus bars of adjacent solar cells to form an array of solar cells.

[0021] Solar cells have gained wide acceptance among energy consumers as a viable renewable energy source. Still, to be competitive with other energy sources, a solar cell manufacturer must be able to fabricate an efficient solar cell at relatively low cost. With this goal in mind, a process for manufacturing the solar cell 100 is now discussed with reference to FIGS. 4A-4M.

[0022] FIG. 4, which comprises FIGS. 4A-4M, schematically illustrates the fabrication of the solar cell 100 in accordance with an embodiment of the present invention.

[0023] In FIG. 4A, an N-type silicon substrate 101 is prepared for processing into a solar cell by undergoing a damage etch step. The substrate 101 is in wafer form in this example, and is thus typically received with damaged surfaces due to the sawing process used by the wafer vendor to slice the substrate 101 from its ingot. The substrate 101 may be about 100 to 200 microns thick as received from the wafer vendor. In one embodiment, the damage etch step involves removal of about 10 to 20 m from each side of the substrate 101 using a wet etch process comprising potassium hydroxide. The damage etch step may also include cleaning of the substrate 101 to remove metal contamination.

[0024] In FIG. 4B, tunnel oxides 402 and 107 are formed on the front and back surfaces, respectively, of the substrate 101. The tunnel oxides 402 and 107 may comprise silicon dioxide thermally grown to a thickness of about 10 to 50 Angstroms on the surfaces of the N-type silicon substrate 101. A layer of polysilicon is then formed on the tunnel oxides 402 and 107 to form the polysilicon layer 401 and the polysilicon emitter 108, respectively. Each of the polysilicon layer 401 and the polysilicon emitter 108 may be formed to a thickness of about 1000 to 2000 Angstroms by CVD.

[0025] In FIG. 4C, a P-type dopant source 461 is formed on the polysilicon emitter 108. As its name implies, the P-type dopant source 461 provides a source of P-type dopants for diffusion into the polysilicon emitter 108 in a subsequent dopant drive-in step. A dielectric capping layer 462 is formed on the P-type dopant source 461 to prevent dopants from escaping from the backside of the solar cell during the drive-in step. In one embodiment, the P-type dopant source comprises BSG (borosilicate glass) deposited to a thickness of about 500 to 1000 Angstroms by atmospheric pressure CVD (APCVD) and has a dopant concentration of 5 to 10% by weight, while the capping layer 462 comprises undoped silicon dioxide formed to a thickness of about 2000 to 3000 Angstroms also by APCVD.

[0026] In FIG. 4D, the edge isolation trench 111 is formed near the edge of the substrate 101 on the backside. The trench 111 is relatively shallow (e.g., 10 m deep into the substrate 101) and provides edge electrical isolation. In one embodiment, the trench 111 is formed by cutting through the capping layer 462, the P-type dopant source 461, the polysilicon emitter 108, the tunnel oxide 107, and into a shallow portion of the substrate 101 using a laser.

[0027] In FIG. 4E, exposed regions on the front surface of the substrate 101 is randomly textured to form the textured surface 113. In one embodiment, the front surface of the substrate 101 is textured with random pyramids using a wet etch process comprising potassium hydroxide and isopropyl alcohol.

[0028] In FIG. 4F, an N-type dopant source 412 is formed on regions of the textured surface 113 where contact holes 120 (see FIG. 1) will be subsequently formed to allow subsequently formed metal contacts 102 to electrically connect to the substrate 101. As its name implies, the N-type dopant source 412 provides a source of N-type dopants for diffusion into the front side of the substrate 101. In one embodiment, the N-type dopant source 412 is formed by inkjet printing the dopant material directly onto the substrate 101.

[0029] In one embodiment, the N-type dopant source 412 comprises silicon dioxide doped with phosphorus. Only one N-type dopant source 412 is shown in FIG. 4F for clarity of illustration. In practice, there are several dot-shaped N-type dopant sources 412, one for each region where a contact hole 120 is to be formed (see FIG. 2). This allows formation of several dot shaped N-type doped regions 106 (see FIG. 1) after a subsequently performed drive-in step now discussed with reference to FIG. 4G.

[0030] In FIG. 4G, a dopant drive-in step is performed to diffuse N-type dopants from the N-type dopant source 412 into the substrate 101 to form the N-type dope region 106, to diffuse P-type dopants from the P-type dopant source 461 to the polysilicon emitter 108, and to diffuse N-type dopants into the front side of the substrate 101 to form the N-type doped region 105. Silicon dioxide layer 109 represents layers 461 and 462 after the drive-in step. The polysilicon emitter 108 also becomes a P-type doped layer after the drive-in step. The N-type doped region 105 may be formed by exposing the sample of FIG. 4G to phosphorus in a diffusion furnace, for example. The use of the N-type dopant source 412 allows for a more controlled and concentrated N-type diffusion to the N-type doped region 106. The thin thermal silicon dioxide layer 124 may be grown on the textured surface 113 during the drive-in process.

[0031] The drive-in step to dope the polysilicon emitter 108 on the backside and to form the N-type doped regions 105 and 106 on the front side may be formed in-situ, which in the context of the present disclosure means a single manual (i.e., by fabrication personnel) loading of the substrate 101 in a furnace or other single chamber or multi-chamber processing tool. In one embodiment, the drive-in step is performed in a diffusion furnace. The preceding sequence of steps leading to the drive-in step allows for in-situ diffusion, which advantageously helps in lowering fabrication cost.

[0032] It is to be noted that the step of using an N-type dopant source 412 to diffuse dopants into the N-type doped region 106 may be omitted in some applications. That is, in an alternative process, the formation of the N-type dopant source 412 in FIG. 4F may be omitted. In that case, the N-type doped regions 105 and 106 will be both doped by introduction of an N-type dopant in the diffusion furnace during the drive-in step. All other process steps disclosed herein remain essentially the same.

[0033] In FIG. 4H, the antireflective coating of silicon nitride layer 103 is formed over the textured surface 113 after removal of the N-type dopant source 412. Besides being an antireflective coating, the silicon nitride layer 103 also advantageously serves as a dielectric, enabling the selective contacts to be formed on the front surface to reduce front surface recombination. The silicon nitride layer 103 may be formed to a thickness of about 450 Angstroms by PECVD, for example.

[0034] In FIG. 4I, a front contact mask 420 is formed on the silicon nitride layer 103 to create a pattern 421 defining the contact holes 120 (see FIG. 1). The mask 420 may comprise an acid resistance organic material, such as a resist, and formed using a printing process, such as screen printing or inkjet printing.

[0035] In FIG. 4J, a back contact mask 422 is formed on the silicon dioxide layer 109 to create patterns 423 defining the contact holes 123 (see FIG. 1). Similar to the mask 420, the mask 422 may comprise an organic material formed using a printing process.

[0036] In FIG. 4K, contact holes 120 and 123 are formed by removing exposed portions of the silicon nitride layer 103 and the silicon dioxide 109 in a contact etch step. In one embodiment, the contact holes 120 are formed by using a selective etch process that removes exposed portions of the silicon nitride layer 103 and stops on the substrate 101. The same etch process removes exposed portions of the silicon dioxide 109 and stops on the polysilicon emitter 108. In one embodiment, the etch process comprises a BOE (buffered oxide etch).

[0037] In FIG. 4L, the metal contact 110 is formed on the silicon dioxide layer 109 to fill the contact holes 123 and make electrical connection to the polysilicon emitter 108. The metal contact 110 may be formed using a printing process. The metal contact 110 may comprise silver, which, together with the silicon dioxide layer 109, makes an excellent backside infrared reflector. Other metals may also be used as a metal contact 110, such as aluminum, for example.

[0038] In FIG. 4M, the metal contact 120 is formed on the silicon nitride layer 103 to fill the contact holes 120 and make electrical connection to the substrate 101. The metal contact 120 may comprise silver and formed using a printing process.

[0039] Formation of the metal contacts 110 and 102 may be followed by a firing step. The firing step is applicable when using screen printed silver paste as metal contacts, but not when using other processes or metals. The solar cell 100 may then be visually inspected and tested.

[0040] While specific embodiments of the present invention have been provided, it is to be understood that these embodiments are for illustration purposes and not limiting. Many additional embodiments will be apparent to persons of ordinary skill in the art reading this disclosure.