ADIABATIC CIRCUITS FOR COLD SCALABLE ELECTRONICS

Abstract

A system and method comprising a cryogenic adiabatic circuit in a cryogenic environment and a clock generator at a higher temperature, the circuit's clock lines can be connected across the temperature gradient to the clock generator, where the clock generator runs below the frequency that would yield power dissipation equal to the static dissipation of a functionally equivalent CMOS circuit at room temperature, resulting in lower power for the function than possible at room temperature irrespective of the speed of operation.

Claims

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21. A system comprising: a transistor circuit comprising logic and cells that store information; a Josephson junction circuit wherein the information can be moved between the transistor circuit and the Josephson junction circuit.

22. The system of claim 21 further comprising: a qubit-containing payload, wherein the information is transferred to the payload.

23. The system of claim 21 further comprising: an external processor connected to the transistor circuit, the external processor configured in a room temperature environment, wherein the external processor can load and update the information in the transistor circuit.

24. The system of claim 21 wherein the transistor circuit comprises an adiabatic circuit.

25. The system of claim 24 further comprising: at least one clock and power supply configured in a room temperature environment, wherein the at least one clock and power supply is operably connected to the transistor circuit, wherein both power and time synchronization are provided to the transistor circuit.

26. The system of claim 22 further comprising: a multiplexer, wherein information in the transistor circuit can be moved with different access rates.

27. The system of claim 21, wherein the Josephson junction circuit comprises configurable logic, wherein the configurable logic is configured by the information.

28. The system of claim 27 further comprising: an alternative branch wire, wherein information on the alternative branch wire will influence configuration of the configurable logic.

29. The system of claim 28 further comprising: a configuration buffer configured to store configurations that can be switched like classical or quantum subroutines.

30. The system of claim 28 wherein information on the alternative branch wire identifies an error detected by a quantum error correction code.

31. The system of claim 22 further comprising: a second Josephson junction circuit; a microwave carrier transmission line configured as an input to the second Josephson junction circuit; a modulated signal transmission line configured as an output of the second Josephson junction circuit, wherein the second Josephson junction circuit modulates information on the microwave carrier transmission line to yield information on the modulated signal transmission line based on the information, and wherein a modulated signal is transferred to a qubit.

32. The system of claim 21 wherein the Josephson junction circuit is configured as a single-flux quantum (SFQ) circuit.

33. The system of claim 21 further comprising: at least one transistor, wherein a leakage current of the at least one transistor is rebalanced for cryogenic operation.

34. The system of claim 22 wherein the transistor circuit comprises a tapped adiabatic SRAM, wherein information in the SRAM is transferred to the payload via taps.

35. The system of claim 21 further comprising: a semiconductor FET that either passes or blocks an SFQ pulse based on the information.

36. A system comprising: a transistor circuit configured to include logic and cells that store information; and a payload configured in a cryogenic environment, wherein the information is transferred to the payload.

37. The system in claim 36 wherein the payload contains qubits.

38. The system of claim 36 further comprising: at least one clock and power supply configured in a room temperature environment, wherein the at least one clock and power supply is operably connected to the transistor circuit, wherein both power and time synchronization are provided to the transistor circuit.

39. The system of claim 36 further comprising: an external processor connected to the transistor circuit, the external processor configured in a room temperature environment, wherein the external processor can load and update the information in the transistor circuit.

40. A system comprising: an adiabatic circuit; an external processor connected to the adiabatic circuit, the external processor configured in a room temperature environment, wherein the external processor can load and update control signal values stored in the adiabatic circuit; at least one capacitive node connected to an output of the adiabatic circuit thereby producing an AC/DC cryogenic control signal; and at least one of a superconductor FET wherein the control signal connects to a gate of the superconductor FET and a semiconductor FET wherein the control signal connects to a gate of the semiconductor FET.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying figures, in which like reference numerals refer to identical or functionally-similar elements throughout the separate views and which are incorporated in and form a part of the specification, further illustrate the embodiments and, together with the detailed description, serve to explain the embodiments disclosed herein.

[0045] FIG. 1A depicts a diagram illustrating the task associated with the disclosed embodiments;

[0046] FIG. 1B depicts an energy delay plot for logic devices associated with the disclosed embodiments;

[0047] FIG. 2 depicts a system for cold, scalable electronics used for computational tasks, in accordance with the disclosed embodiments;

[0048] FIG. 3A depicts a transmission gate symbol, in accordance with the disclosed embodiments;

[0049] FIG. 3B depicts a transmission gate schematic, in accordance with the disclosed embodiments;

[0050] FIG. 3C depicts a 2LAL shift register stage, in accordance with the disclosed embodiments;

[0051] FIG. 3D depicts a 2LAL AND gate, in accordance with the disclosed embodiments;

[0052] FIG. 3E depicts a 2LAL shift register circuit with a room temperature clock driver, in accordance with the disclosed embodiments;

[0053] FIG. 4 depicts a power versus frequency chart, in accordance with the disclosed embodiments;

[0054] FIG. 5 depicts a current versus voltage chart for transistors at various temperatures, illustrating the strategy for optimizing transistor design, in accordance with the disclosed embodiments;

[0055] FIG. 6A depicts a baseline CMOS hybrid, in accordance with the disclosed embodiments;

[0056] FIG. 6B depicts an adiabatically scaled semiconductor-superconductor hybrid, in accordance with the disclosed embodiments;

[0057] FIG. 7 depicts the architecture of a memory-like shift register component, in accordance with the disclosed embodiments;

[0058] FIG. 8A depicts an analog or digital control signal generator implemented as a semiconductor-superconductor hybrid, in accordance with the disclosed embodiments;

[0059] FIG. 8B depicts a method for implementing digital control signals, in accordance with the disclosed embodiments;

[0060] FIG. 9 depicts modifications to an adiabatic memory to make digital control signals, in accordance with the disclosed embodiments;

[0061] FIG. 10A depicts a voltage to Josephson-level current interface via a superconductor FET, in accordance with the disclosed embodiments;

[0062] FIG. 10B depicts a voltage to Josephson-level current interface via an SFQ pulse interrupter, in accordance with the disclosed embodiments;

[0063] FIG. 10C depicts a voltage to Josephson-level current interface via a pass gate, in accordance with the disclosed embodiments;

[0064] FIG. 11 depicts a semiconductor-superconductor hybrid FPGA, in accordance with the disclosed embodiments;

[0065] FIG. 12 depicts a controlled microwave pulse modulation system, in accordance with the disclosed embodiments;

[0066] FIG. 13 depicts a semiconductor-superconductor hybrid subsystem that can be rapidly reconfigured, in accordance with the disclosed embodiments;

[0067] FIG. 14 depicts a block diagram of a computer system which is implemented in accordance with the disclosed embodiments;

[0068] FIG. 15 depicts a graphical representation of a network of data-processing devices in which aspects of the present embodiments may be implemented; and

[0069] FIG. 16 depicts a computer software system for directing the operation of the data-processing system depicted in FIG. 14, in accordance with an embodiment.

DETAILED DESCRIPTION

[0070] The particular values and configurations discussed in the following non-limiting examples can be varied, and are cited merely to illustrate one or more embodiments and are not intended to limit the scope thereof.

[0071] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings, in which illustrative embodiments are shown. The embodiments disclosed herein can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments to those skilled in the art. Like numbers refer to like elements throughout.

[0072] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

[0073] Throughout the specification and claims, terms may have nuanced meanings suggested or implied in context beyond an explicitly stated meaning. Likewise, the phrase “in one embodiment” as used herein does not necessarily refer to the same embodiment and the phrase “in another embodiment” as used herein does not necessarily refer to a different embodiment. It is intended, for example, that claimed subject matter include combinations of example embodiments in whole or in part.

[0074] In general, terminology may be understood at least in part from usage in context. For example, terms, such as “and,” “or,” or “and/or,” as used herein may include a variety of meanings that may depend at least in part upon the context in which such terms are used. Typically, “or” if used to associate a list, such as A, B or C, is intended to mean A, B, and C, here used in the inclusive sense, as well as A, B or C, here used in the exclusive sense. In addition, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

[0075] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0076] The embodiments disclosed herein make use of cryogenic adiabatic transistor circuits that can expand the range of applications of cold electronics and increase the performance of those applications at scale. An exemplary overview of the embodiments is illustrated in FIG. 2, which illustrates a system 200 for cold scalable electronics.

[0077] Cold, scalable electronics are required for computational tasks that include a scalable information processing payload that only functions correctly when cold. As used herein, the phrase “cold electronics,” or the phrase “cold, scalable electronics” refer to systems where the payload requires an absolute temperature of 10% or less than the warmest stage in the system. Examples of such scalable information processing payloads include, but are not limited to sensors, qubits, and cryogenic computing components.

[0078] The disclosed embodiments, directed cryogenic adiabatic transistor circuits, provide new ways to create and apply cryogenic versions at a given temperature T, and with the ability to trade speed for energy efficiency over orders of magnitude.

[0079] In an embodiment, cryogenic adiabatic transistor circuits can be applied as the memory-like part of a hybrid with another technology such as Josephson junctions or cryo CMOS. The embodiments further include a series of architectural structures that use the adiabatic technology to buffer data (e.g. FPGA configurations and digitized waveforms) for use by faster logic technology, providing better scalability in accordance with the disclosed embodiments.

[0080] FIG. 2 thus illustrates architecture of a system 200 used to perform the function of equation (1), distributed over stage 1 205, stage 2 210, and stage 3 215, and a scalable, cryogenic payload function q(N). An objective of the disclosed embodiments is to achieve the best performance of f(N)=(f.sub.300°f.sub.4°f.sub.0.015°p)(N) at any scale N, with performance including performance per unit of energy (e.g. Joules). Since the overall task is scalable, data transfer bandwidth between stages can be scalable. The architecture can further include a power supply 220, an input/output 225, and a cooling system 230 which may comprise a refrigerator, cryocooler, or other such apparatus, in which case performance includes the energy of both the circuit and the cooling system 230.

[0081] FIGS. 3A-3E illustrate operational schematics of two-level adiabatic logic (2LAL) adiabatic circuits, in accordance with the disclosed embodiments. 2LAL is based on transmission gates 305.

[0082] A transmission gate 305 comprises an n-type 310 and a p-type FET 311 connected at their respective sources and drains. A schematic of a transmission gate 305 is illustrated in FIG. 3B. This two-transistor structure acts like a single-pole-single-throw switch, connecting the A side 306 and B side 307, when P 308 is true, and like an open circuit when P 308 is false. All signals in 2LAL are dual rail, meaning every A is accompanied by a −A elsewhere in the circuit, so the schematic for a transmission gate 305, comprises two pairs of transistors with inverted signals on the sources and drains.

[0083] One phase of a 2LAL shift register 320 is illustrated in FIG. 3C. A 2LAL shift register can comprises four repetitions of the two transmission gate structure shown in FIG. 3C, the repetitions differing by advancing phases of a four-phase clock. A logic family can be built around 2LAL, with a 2LAL AND function 325 illustrated in FIG. 3D

[0084] FIG. 3E shows, a schematic of a 2LAL logic system 350 which includes the four combined clock and power supply waveforms 355-358, notably generated in a room temperature environment 365 and transported to the circuit 375 through superconducting wires 360 (where the signal is in an environment cold enough for superconductivity).

[0085] In FIG. 3E the circuit 375 comprises one of four phases of a shift register 320, illustrated schematically. It should be appreciated that the circuit 375 can more generally comprise any member of the 2LAL logic family. Since the 2LAL logic family contains a universal gate set, only four wires 360 are required between the room-temperature signal generator and the cryogenic environments 370 irrespective of the complexity of the logic. In other embodiments, additional wires can be added for I/O and/or if special voltages are required. It should be appreciated that other adiabatic logic families, such as split level change recovery logic (SCRL), use different numbers of combined clock and power supply signals, and can be considered part of the disclosure provided herein.

[0086] As disclosed herein, cryogenic operation can make adiabatic transistor circuits practical for applications relevant to cold electronics. Adiabatic transistor circuits can use voltage-based signaling on wires, which act as capacitors. The signal energy is ½CV.sup.2. The difference between these circuits and CMOS is whether this energy is turned into heat in a cryogenic environment, where it is subject to refrigeration overhead, or at room temperature where it is not.

[0087] FIG. 4 illustrates a chart 400 of standard CMOS inverters and the same transistors wired into an adiabatic shift register of the 2LAL circuit design as described herein. On a log-log scale, the curves show power dissipation of standard CMOS declines as a function of clock period, or inverse clock frequency, with slope −1 (linear) while 2LAL has slope −2 (quadratic).

[0088] Unlike CMOS circuits' DC power supply, adiabatic circuits' combined clock and power supply waveforms 355 have smooth ramps of slope ±dV/dt, or change in voltage over time, that is proportional to frequency. These ramps create current I=CdV/dt, at the design point of low voltage drop across the transistors, which causes I.sup.2R losses in the transistors' channels. As the clock period lengthens, I declines linearly but PR drops quadratically, thus causing the 2LAL power curve 405 in FIG. 4 to decline with slope —2. In other words, the quadratic decline is due to the combined effect of fewer operations and less dissipation per operation. Thus, adiabatic circuits dissipate only a portion of the signal energy in the transistor's channel with the rest going up the wire to the power supply—which is in the temperature (e.g. approximately 300 K) of the environment 365 and not subject to refrigeration overhead. This explanation shows how the transistors in the CMOS devices (CMOS HP and CMOS LP) in FIG. 1B can move along the curve of constant energy-delay product when used in an adiabatic circuit.

[0089] A critical aspect of the embodiments disclosed herein is what happens to the energy when it arrives at the power supply. As explained above, adiabatic circuitry eliminates the refrigeration overhead of 1,000× to 1,000,000× irrespective of what may or may not happen at the power supply. For operation at 4 K or lower, this is enough of an energy savings to make adiabatic circuits practical. The embodiments disclosed herein therefore make adiabatic transistor circuits practical by using cryogenic operation instead of, for example, an energy recycling power supply.

[0090] Furthermore, it is another aspect of the disclosed embodiments to extend adiabatic speed range (i.e. in the downward sloping region in FIG. 4). In certain aspects, the embodiments include a hybrid technology where speed can be accomplished using Reciprocal Quantum Logic (RQL), CMOS, or the like. The adiabatic circuits can provide a memory, state, or large amounts of logic where the value is in its complexity not its speed. For example, FIG. 4 is verification that transistorized 2LAL can be very energy efficient in applications where speed is not essential. Generally speaking, the curves in chart 400, level off on the right at the region 410, at the point where transistors have the full power supply voltage across two terminals, caused by a combination of gate or source-drain leakage.

[0091] Transistors optimized for room temperature can benefit from cooling. Total device leakage is the sum of temperature-independent gate leakage plus temperature-dependent source-drain leakage—where the two leakages can be traded off against each other by varying gate dielectric thickness. Assuming a fixed operating voltage, a gate dielectric thickness can be selected so that the gate and source-drain leakages are the same at room temperature, as shown on the left of FIG. 5.

[0092] FIG. 5 illustrates current as a function of input voltage associated with rebalancing transistors in accordance with the disclosed embodiments. Chart 505 illustrates power dissipation optimization at 300 K, which suggests balancing source-drain and gate leakage. Chart 510 illustrates that source-drain leakage drops significantly at cryogenic temperatures, but that this will not make much difference. However, Chart 515 illustrates the rebalanced result showing that the process can be optimized for cryogenic operation.

[0093] Cryogenic operation causes steepening of the subthreshold slope and a reduction in source-drain leakage, as shown in center of FIG. 5, leaving gate leakage as the dominant factor in total leakage. If the leakages were balanced to begin with, the unchanging gate leakage should limit the adiabatic energy savings to about a factor of two, which is not enough to satisfy the needs of cold electronics.

[0094] It is easy to change the supply voltage. Even, a modest reduction will reduce gate leakage while increasing source-drain leakage, tending to bring the two into balance at a lower level of total leakage. While this is desirable, the amount of reduction in supply voltage is limited by the threshold voltage, which is not temperature dependent, so reducing the supply voltage may be helpful, but may not be completely sufficient.

[0095] Accordingly, more energy efficient cryogenic memory-like circuits are possible even without changing the physical structure of transistors. Both CMOS and 2LAL logic gates can be used for data storage, as illustrated by the shift register in FIG. 4. Transistors have the same leakage characteristics irrespective of whether they have been wired into a CMOS or a 2LAL circuit, so all the curves in FIG. 4 have the same dissipation in the zero-frequency limit if they had been simulated with the same operating points.

[0096] As such, cryogenic adiabatic circuits, as disclosed herein, can be an effective memory option for some combinations of speed, power, and density. Logic is usually rated by speed and energy per operation, but memory can be useful for holding data even if it does very few operations. Memory is also rated by density, which generally means small devices are better.

[0097] CMOS SRAM can have somewhat fewer transistors than an adiabatic memory due to the simplicity of the circuits for address decoders and cells. For the same transistors, CMOS can have an advantage at the lowest speed range. However, cryogenic adiabatic transistor circuits, as disclosed herein, will have much lower energy per operation and will operate at lower power at even modest frequencies. Josephson junctions are huge compared to transistors. Therefore, both CMOS and cryogenic adiabatic transistor circuits have an advantage in density.

[0098] In certain embodiments, transistors can be optimized for lower temperature by making the gate dielectric thicker than the room-temperature optimum until the gate and source-drain leakages are the same at a lower temperature. As total leakage is reduced, the qualitative result is an extension of the region in FIG. 4 with downward slope −2, 410, before I.sub.off and static leakage cause a leveling off.

[0099] In certain embodiments, adiabatic scaling of an RQL-2LAL hybrid can be realized. Josephson junction chips are fabricated by evaporating a superconductor, such as Niobium, onto a blank silicon wafer. To manufacture a hybrid, the process starts with a completed silicon wafer instead of a blank one.

[0100] Hybrid chips 600 and 650 illustrated in FIGS. 6A and 6B. FIGS. 6A and 6B illustrate the relevant parameters of the hybrid design, which can be computed using the performance figures provided for CMOS and RQL provided in FIG. 1B.

[0101] FIG. 6A illustrates a hybrid chip 600 with CMOS, and hence no adiabatic scaling. Hybrid chip 600 includes the upper layer 605 filled with gates 610. As illustrated in FIG. 6A, the upper layer 605 can include, for example, 1 million RQL gates. It should be appreciated that the number of gates and values provided in FIG. 6A and FIG. 6B are exemplary and that other numbers of gates and values may also be used.

[0102] Hybrid chip 600 further includes a lower layer 615 connected to the upper layer 605 via connections 620. The lower layer 615 can includes CMOS gates 625. In FIG. 6A, the CMOS gates 625 represent 1,000 CMOS gates. With little or no adiabatic scaling, the semiconductor CMOS gates 625 add process complexity but the number of gates isn't enough to make a difference to the design.

[0103] FIG. 6B illustrates a hybrid chip 650 with adiabatic scaling available at cryogenic temperatures. Hybrid chip 650 includes the same upper layer 605 filled with gates 610 where the upper layer 605 can comprise a Josephson junction filled with, for example, 1 million RQL gates. However, the lower layer 615 can comprise, for example, 100 million semiconductor 2LAL gates 655 (far more than the 1 million SFQ gates of hybrid chip 600) that allows hybrid chip 650 to address more complex problems.

[0104] Thus, using adiabatic scaling, hybrid chip 600 can be filled with gates 625 comprising CMOS transistors, while the hybrid chip 650 can be filled with gates 655 comprising transistors comprising 2LAL circuits. It should be noted that the difference in the operating points for hybrid chips 600 and 650 is governed so that the power dissipation of the two layers is equal. The rest of the semiconductor layer 615 can be left empty (i.e. it is dark silicon).

[0105] Adiabatic scaling, as described herein refers to changing the clock period of an adiabatic circuit, but adjusting the number of gates on the chip so the total chip power is unchanged. For example, a chip with g adiabatic gates operating at clock rate c could have its clock rate lowered to c/10. Each gate will dissipate 1/100th the power, but in lieu of reducing power at the chip level, the gate count increases to 100 g and power at the chip level stays the same.

[0106] Table 1 illustrates an exemplary process of three adiabatic scaling steps of 10× clock period and 100× gate count for the system illustrated in FIG. 6A and FIG. 6B. However, the first step switches the circuit design from CMOS to 2LAL, the latter of which is assumed to be 10× more complex, so the first increase in gate count will be 10× instead of 100×. In table 1, superscripts (1) (2) and (3) indicate the scaling step.

TABLE-US-00001 TABLE 1 ADIABATIC SCALING Baseline N.sub.RQL f.sub.RQL P.sub.RQL P.sub.Static 1M 1.6 GHz 160 μW n/a N.sub.CMOS f.sub.CMOS P.sub.CMOS P.sub.Static 1K 4 GHz 160 μW n/a A thousand extra gates, useful for voltage-based signalling Scaling Step 1 N.sub.RQL f.sub.RQL P.sub.RQL P.sub.Static 1M 1.6 GHz 160 μW n/a N.sup.(1).sub.2LAL f.sup.(1).sub.2LAL P.sup.(1).sub.2LAL P.sup.(1).sub.Static 10K 400 MHz 160 μW 16.7 nW Ten thousand slower gates, useful for voltage-based signalling Scaling Step 2 N.sub.RQL f.sub.RQL P.sub.RQL P.sub.Static 1M 1.6 GHz 160 μW n/a N.sup.(2).sub.2LaL f.sup.(2).sub.2LaL P.sup.(2).sub.2LaL P.sup.(2).sub.Static 1M 40 MHz 160 μW 1.67 μW Doubles gate count, but the new gates are slow Scaling Step 3 N.sub.RQL f.sub.RQL P.sub.RQL P.sub.Static 1M 1.6 GHz 160 μW n/a N.sup.(3).sub.2LaL f.sup.(3).sub.2LaL P.sup.(3).sub.2LaL P.sup.(3).sub.Static 100M 4 MHz 160 μW 167 μW Similar resource mix to logic + memory, but also computes

[0107] As illustrated in Table 1 (which provides exemplary values for illustrative purposes only), the energy per operation E, propagation delay t.sub.pd, and clock rate f (assuming 500 gate delays per clock cycle) for RQL, CMOS, and 2LAL from FIG. 2 yields equations (2) and (3) as follows:

E.sub.RQL=0.1 aJ,t.sub.pd,RQL=1.25 ps,f.sub.RQL=1.6 GHz  (2)

E.sub.CMOS=40 aJ,t.sub.pd,CMOS=0.5 ps,f.sub.CMOS=4 GHz  (3)

[0108] Assuming a million-gate RQL chip, where N.sub.RQL=1 M gates, the superconductor layer can dissipate according to equation (4):

P.sub.RQL=N.sub.RQL×f.sub.RQL×E.sub.RQL=160 μW at 4 K  (4)

[0109] which corresponds to N.sub.CMOS=1 K gates.

[0110] A growing P.sub.STATIC power due to leakage can also be calculated. To calculate leakage power (assuming a 1 V supply voltage, 3 KΩ on resistance), I.sub.ON/I.sub.OFF=10.sup.8 at a 50% duty cycle.

[0111] Scaling step 3 involves making 2LAL into memory (resulting in the hybrid chip 650 illustrated in FIG. 6B). This scaling step yields N.sub.RQL=1 M fast RQL gates and N.sup.(3).sub.2LAL=100 M transistorized gates running at 4 MHz, which comprises a resource mix similar to logic and memory in standard microprocessor systems. However, 2LAL is actually a logic family, and the embodiments disclosed herein provide ways of using 2LAL gates, at scaling step 3, for important functions applicable to cold electronics applications. Furthermore, the speed of gates in scaling steps 1 and 2 fit in between the speed of scaling step 3 gates and RQL, making them suitable for speed matching.

[0112] The properties of a cryo CMOS-2LAL hybrid are also illustrated Table 1 and FIGS. 6A and 6B, by ignoring the RQL layer 610, and assuming all the transistor circuits 655 are intermixed on a chip. 2LAL's advantage in energy efficiency is so large that it should be used wherever possible. In the disclosed embodiments, this can limit cryo CMOS to functions that do not have a parallel implementation, or to activities that require generation of high-speed signals.

[0113] Control systems for spin qubits are an exemplary application for a cryo CMOS-2LAL hybrid. An alternate embodiment can comprise a cryo CMOS-2LAL hybrid on a monolithic chip all at a single temperature. The hybrid can include interface electronics to a qubit-containing payload and control electronics.

[0114] Commercial memories almost always allow random access, but the combination of fast random-access times and high density is not feasible at cryogenic temperatures. FIG. 7 illustrates a system 700 comprising a high capacity, high bandwidth memory-like structure 705 that can be used for sequential storage in accordance with the disclosed embodiments. The values provided in FIG. 7 are meant to be exemplary. In other embodiments other values can be used.

[0115] The system 700 includes a series of circular 2LAL shift registers 710, built from gates of scaling step 3, each connected to a 10:1 multiplexer 720 built from gates of scaling step 2, and yet again to a 10:1 multiplexer 730 built from gates of scaling step 1. This circuit causes data, at the highly parallel output of the storage elements 715, to become less parallel by a factor of 10 but speed up by a factor of 10 as it flows to data pathway 725. This process repeats from data pathway 725 to the final data transferred to the superconductor layer at 1 GB/s by data pathway 726.

[0116] All the components from shift registers 710 through multiplexer 730 can be configured on a semiconductor layer 735. The output from multiplexer 730 can then be sent to the superconducting layer 740 of the system 700. To meet power requirements, the semiconductors 735 must be slowed down to meet control signal requirements. However, the multiplexing scheme embodied in FIG. 7, involving both the semiconductors 735 and much faster superconductors 740, suffices to match speeds.

[0117] The system 700 in FIG. 7 stores data in a serial shift register built with gates from scaling step 3 illustrated in FIG. 6B. This allows sequential access at f.sup.(3).sub.2LAL=4 MHz, or 1 GB/sec (assuming the shift register is 2,000 bits wide, as used in the exemplary embodiment illustrated in FIG. 7). If the register loops back on itself, it can be loaded during the system boot process and the contents used many times. The shift registers may be as long as necessary to meet application storage needs, subject to chip size limitations.

[0118] It should be noted that transferring this data directly to RQL would require 2,000 receivers running at 1/1,250 of their maximum speed. To make more efficient use of resources, the structure 700 can include 10:1 multiplexers 720 using gates from scaling step 2 to create, for example, a 200-bit wide stream clocked at 40 MHz. A second level of multiplexers 745 creates a 20-bit wide stream at 400 MHz. Thus, the system 700 can comprise a circuit that has a data density similar to a memory but uses 2LAL's variable speed logic to process the data into a stream suitable for the much faster RQL logic.

[0119] In certain embodiments, energy efficient digital control signals can be employed. Specifically, in certain embodiments a circuit derived from DRAM for generating control signals in a cryogenic environment can be modified to improve energy efficiency by addressing logic based on a cryogenic adiabatic logic family, such as 2LAL.

[0120] In FIG. 8A an exemplary semiconductor-superconductor hybrid system 800 is illustrated. The semiconductor layer applies voltage-based signals to the gates of superconducting FETs, which translate the signals into a form readily used by superconducting circuits. The hybrid system 800 can be fabricated by using a CMOS wafer as a base for depositing superconductor circuits—in lieu of other methods using a blank silicon wafer as a base.

[0121] Specifically, the hybrid system 800 includes a control signal generation layer 805 with DRAM memory cells 810 that not only hold data for access from an external processor, but also “tap” each cell with a wire. The wire runs to another portion of the system 800 carrying the state of the cell as a digital control signal.

[0122] The hybrid system 800 includes a column data drive 815 that is operably connected to the control signal generation layer 805. A row decoder 820 is also operably connected to the control signal generation layer 805. Clock and data 825 can be connected to the row decoder 820 and/or the column data drive 815. An access transistor 830 can be provided on the control signal generation layer connections to the controlled layer 850.

[0123] The controlled layer 850 can include a Josephson weak link or resistor 855, associated with a Josephson junction 860 (illustrated in an exploded view). A signal generator 865 can be provided in the room temperature environment 870, and can be connected to the control signal generation layer 805 in the cryogenic environment 875

[0124] The DRAM-derived circuit 800 in FIG. 8A stores data on the capacitor plate 880 at the interface 885 between layers. The capacitor plate 880 can be the gate of a superconducting FET, and the effect of the control signal can be to control the critical current of the Josephson junction 860.

[0125] By using address, or row, decoders constructed from a cryogenic adiabatic logic, such as 2LAL, the process for updating the control signals can be fully adiabatic, meaning the energy for an update could vary with speed according to the quadratic curve illustrated in FIG. 4, including the energy to charge the capacitive loads of the DRAM cells 810 and the control signal.

[0126] The update process begins and ends in a reference state where all access transistors are in the off, or nonconducting, state and a copy of all the control signals are in the memory of an external processor.

[0127] An associated method 890 is illustrated in FIG. 8B. To update the programmable voltages on a row at step 891, the external processor transmits its copy of all the programmable voltages on that row to the column data logic, which drives the control values to the source terminal of all the access transistors. The access transistors block further current flow because they are all turned off.

[0128] Next at step 892 the adiabatic row decoder translates the binary address from the external processor to a 1-of-N signal that identifies the row, driving the signal to the gates of all the access transistors on the selected row. The natural operation of the adiabatic logic charges the transistor gates with very low dissipation, again following the quadratic curve in FIG. 4. There is very little initial current flow through the transistors that turn on because the external processor used its copy of the control signal data to drive each column with the same voltage as the control signal at the row-column intersection—i.e. each transistor's source and drain will be at the same voltage when the transistors turns on.

[0129] At step 893, the external processor then transmits new data to the column data logic block. The natural operation of the adiabatic logic will charge or discharge the programmable voltages through the access transistors with very low power dissipation.

[0130] At step 894, the external processor then instructs the row decoder to turn off all access transistors. If the external processor retains the new signal values in its memory, the system will have been restored to the expected state between invocations of the method 890.

[0131] It should be noted that the high energy efficiency of adiabatic circuitry comes with some unusual properties. For example, a four-phase clocked logic family has been developed around 2LAL, which includes a signaling specification that requires each data signal to be valid during one of the clock phases. While a string of 0s in 2LAL produces a DC value at the clock's low voltage V.sub.L, a string of 1s produces an AC signal that transitions between V.sub.L and the clock's high voltage V.sub.H. The AC signal meets the signaling specification, but is in an unexpected state at all other times. This behavior is transparent when connecting 2LAL gates together, but the DRAM access transistors are not 2LAL gates so the complete signaling behavior must be considered.

[0132] The access transistors in FIG. 8A require certain voltages to function properly. Such source-gate voltages reliably turn the transistor on or off. The row decoder and column drive circuits can be driven by two separate sets of 2LAL clocks of the general form shown in FIG. 3. However, the external clock generator determines V.sub.L and V.sub.H, which can be different for the two functions. In FIG. 8A, the row decoder's waveforms can swing from V.sub.L,row to V.sub.H,row and the column data drive waveforms can swing from V.sub.L,data to V.sub.H,data. A transistor in the on state can see a source-gate voltage of V.sub.H,row−V.sub.L,data, and similarly for the off state. In certain embodiments, these voltages lead to two sets of four combined clock and power supply signals.

[0133] It should be appreciated that the embodiments herein use 2LAL as an example, but other logic families, such as SCRL, may be used in other embodiments. Instead of following the 2LAL convention of 0s being a DC level and 1s being an AC signal between V.sub.L and V.sub.H, SCRL signals return to an intermediate value (V.sub.L+V.sub.H)/2 during certain phases of the clock. Each adiabatic logic family may have its own requirements.

[0134] Another aspect of the disclosed embodiments is the ability to create analog control signals, as illustrated on the right side of FIG. 8A. While adiabatic principles apply to analog signals, there isn't a general way of extending an adiabatic logic family like 2LAL to handle analog signals. However, the analog signals only appear on the columns, so only the column data needs to be adapted to the drive that portion of FIG. 8A.

[0135] In lieu of an adiabatic digital column driver, such an embodiment can include running wires for each column to an analog voltage generator at room temperature. If the voltage generator follows the protocol for the column data drive 815, the energy efficiency will follow the quadratic curve in FIG. 4.

[0136] However, other applications may require high-speed analog signals, such as the high-speed pulses. The high-speed pulses in such a situation will pass through resistive transistor channels and dissipate power, but the disclosed embodiments nonetheless improve the energy efficiency of the row decoding.

[0137] FIG. 9 illustrates an alternative embodiment comprising an adiabatic memory 900, similar to conventional SRAM, with taps. The main cell 905 is disposed on the control signal generation layer 930 and comprises four transistors 910 in a cross-coupled inverter configuration and two access transistors 915. Unlike conventional SRAM where cells receive DC power, the cell's power comes from row and column wires. Each cell 905 is connected to a tap 920 that interfaces between the control signal generation layer 930 and the controlled layer 925. The adiabatic SRAM circuit 900 replaces a single access transistor per bit, as shown in FIG. 9, with four transistors in a cross-coupled inverter configuration, connected between two floating power supplies.

[0138] CMOS addressing logic in a standard SRAM operates at the power levels of base level (as shown in Table 1), which is strong enough to overpower the cross-coupled inverters in the storage cell. An adiabatic SRAM uses adiabatic logic for address decoding. However, overpowering the single digital signal in the memory cell would create more heat than the entire rest of the memory, at least at the speed of scaling step 3 of table 1. Since the power in the adiabatic memory comes from the row and column drive, individual cells can be essentially powered down adiabatically, switched, and then powered up adiabatically in a new state.

[0139] FIG. 8A and FIG. 9 illustrate how a DRAM-type control signal can influence an SFQ circuit on another layer. FIGS. 10A-10C illustrate additional embodiments. Both DRAM- and SRAM-generated signals provide a voltage that can influence other parts of the system through an electric field.

[0140] Three options for using the control signals are illustrated in FIGS. 10A-10C. In FIG. 10A control voltages 1020 pass from the semiconductor layer 1005 to the superconductor layer 1010 and then influence a superconductor FET 1015. In FIG. 10B an SFQ pulse, generated in the superconductor layer 1010, passes to the semiconductor layer 1005 via an ohmic (i.e. non-superconducting) wire 1030, passes through a large, but otherwise ordinary, transistor 1035, and back to the superconductor layer. If the transistor is on, the SFQ pulse becomes somewhat attenuated, if off, the SFQ pulse is almost entirely blocked. FIG. 10C illustrates a pass gate 1050 for controlling other parts of the semiconductor layer.

[0141] FIG. 10A includes a superconducting field-effect transistor (FET) 1015. A superconducting wire can conduct current horizontally with zero resistance. However, a narrow superconducting wire only conducts with zero resistance up to a maximum current, called the critical current, above which the device becomes a resistor. A wire used in this way is called a weak link.

[0142] Superconductivity can be disrupted by an electric field, such as the field due to the programmable voltage across the capacitor (for example in FIG. 8A or FIG. 9). The superconducting FET 1015 has a weak link critical current that changes when the voltage structure 1016 applies more voltage, positive or negative. In certain embodiments the drive voltage can be as low as 2.5 V, which is a reasonable voltage swing for transistorized circuits. This supports a structure, like system 800 shown in FIG. 8A, where CMOS voltage signals are converted to SFQ current signals.

[0143] FIG. 10B illustrates a semiconductor FET that serves to interrupt an SFQ pulse. SFQ pulses propagate efficiently along transmission lines, which have a characteristic impedance (e.g. around 15Ω for Niobium superconductor chips at 4 K, leading to SFQ pulse dimensions of about 1 mV×2 ps). If such an SFQ signal is routed through a semiconductor FET, with a sufficiently low on resistance (e.g. approximately 15Ω), the pulse will pass with some attenuation. If the transistor is off, it doesn't pass at all. Thus, a control signal can influence the SFQ circuit by blocking or passing an SFQ pulse. The energy consumed is just the energy in the pulse, if the pulse is destroyed or attenuated.

[0144] FIG. 10C illustrates a control voltage influencing more semiconductor circuitry. If the control voltage is applied to the gate of a semiconductor FET, the FET can act as an SPST switch, with the control voltage shorting the source and drain or leaving an open circuit. The CMOS transmission gate previously illustrated in FIG. 3 has similar properties, but requires two transistors and complementary control signals.

[0145] In another embodiment, the systems and methods disclosed herein can be used to yield an improved cryogenic field programmable gate array (FPGA). This can be realized in at least two ways, both using 2LAL control signals to configure the FPGA's programmable logic. In one embodiment, the programmable logic is RQL on a separate layer with the principle advantage that valuable space on the Josephson junction layer is not taken up with configuration logic unnecessarily. In the second embodiment, the programmable logic is also CMOS or 2LAL on the same layer, with the advantage being in energy efficiency during reconfiguration.

[0146] An FPGA generally comprises an array of configurable logic blocks (CLBs) connected by a programmable routing network, as shown in FIG. 11. The FPGA simulates an integrated circuit by configuring each CLB to be the equivalent of a few gates. The routing network is configured to replicate an integrated circuit's wiring pattern or netlist. Just as memories are manufactured without any data, FPGAs are manufactured without a specific function. A configuration string sets the FPGA's function during the boot process.

[0147] FIG. 11 illustrates the basic structure of an FPGA 1100 comprising configurable logic blocks 1115 (CLBs) connected by a network of routers 1120 whose overall routing pattern is controlled by setting control signals arriving from the control signal generation layer. Control signals give each CLB 1115 a specific identity and set the routing pattern to duplicate a logic design. The embodiment uses two layers, a control signal generation layer 1105 and a controlled layer 1110, thus benefitting from the density (complexity) of the semiconductor control signal generation and the high-speed/low-power characteristics of the Josephson junction-based controlled logic.

[0148] For example, a CLB 1115 can support Boolean AND, OR, NOT, and a half adder, with two control signals selecting one of the four functions. Likewise, control signals for routers can specify whether data continues in the same direction, turns left, turns right, or connects to the nearest gate. In both cases, the control signals can be generated by adiabatic transistor logic such as 2LAL register stages 1130. If the programmable logic is RQL, the voltage-based signals would be transformed to SFQ via the structures shown in FIGS. 10A-10C.

[0149] CMOS FPGAs have bidirectional pass gates, yet Josephson junctions are not easily configured to pass signals in both directions. As a consequence, superconductor FPGAs can use only unidirectional connections, but require more of them, resulting in higher overhead than equivalent CMOS FPGAs. Superconductor FPGAs can also be created using a magnetic Josephson junction (MJJ) as the underlying programmable device. An MJJ has an internal magnet whose field can point in one of two directions. The MJJ's internal state causes its critical current to change, effectively disabling circuits that depend on a specific critical current. Selective disablement is the method influencing the configurable logic to create the desired function.

[0150] One embodiment of the improved FPGA, is to combine the control signal generation layer in FIG. 8A or FIG. 9 with the superconductor FPGA, replacing the MJJs with the superconductor FETs. The superconductor FETs are not essential and the transistorized SFQ interrupter in FIG. 10 could be also be used.

[0151] Quantum computer control electronics can be realized according to the embodiments disclosed herein. Distributing the control function across multiple temperatures is a requirement for continued scaling. For example, only passive analog devices and digital multiplexers can be placed at the coldest temperature stages. Digital controllers are necessary, but they are only viable at 4 K or higher. As such, in certain embodiments, the controller can be partitioned both functionally and across different temperatures to meet limitations on devices, materials, and architectures.

[0152] Quantum computers based on spin qubits can also use the architecture of system 200 in FIG. 2, in accordance with the disclosed embodiments. Spin qubits are electrons loosely bound to a location in a material, such as through a donor atom or a quantum dot. Spin qubits require low temperatures. Each qubit type requires control signals with certain properties, such as DC, AC, microwave, various noise levels, and so forth. For example, in some cases physical I/O requirements for quantum dot qubits include: 1) an independent DC voltage on every qubit (site) up to ±1 V; 2) an independent voltage pulse with sub-ns rise times on every qubit up to tens of mV; and 3) an independent microwave magnetic or electric field at every site, typically −40 to −20 dBm, 1-50 GHz bursts of 10 ns to 1 μs duration.

[0153] Superconducting qubits can be controlled with SFQ pulses directly. In accordance with the disclosed embodiments, this allows reconfigurable FPGA logic to create SFQ pulses that interact with qubits directly and with no per-qubit external wiring. FIG. 12 illustrates the preferred approach for generating these pulses according to the disclosed embodiments, which is to use slower but more complex transistor circuits to control a smaller number of high-speed analog microwave components built from Josephson junctions.

[0154] FIG. 12, thus illustrates a system 1200 for controlled microwave modulation. The values provided in FIG. 12 are exemplary and other values may be used without departing from the scope of the embodiments. Pulse envelopes can be stored in a memory-like shift register 1205 (as illustrated in FIG. 7). The pulse envelopes can be speed matched to RQL's faster clock. The gigabyte/second stream provides the control signal to a superconductor D-A converter 1210 that generates analog currents, I.sub.mod 1220. The digitally controlled current becomes the flux control for an SPST microwave switch 1215. The current couples to the Josephson junction (an x) via mutual inductance, altering the transmission/reflection properties of the SPST switch 1215.

[0155] The first step is to store digitally encoded waveforms in the memory-like structure 1205, as illustrated in FIG. 7, and transfer it to the SFQ layer. The next step is to convert the digitally encoded waveform into an analog signal amenable to these microwave components, 1210, which is a typically a current. Current sources controlled by RQL are an option, which typically produce a low-bandwidth modulation signal I.sub.mod. The next step is to use one of the microwave switches, modulators, or other such components associated with the quantum computer for controlling microwave signals with currents, 1215, which are typically generated by current sources at room temperature and transported through the temperature gradient on a microwave transmission line. However, in the preferred embodiment, the I.sub.mod generated in situ controls the modulator 1215. FIG. 7 also shows a feedback path from the high-speed electronics, allowing behavior in the payload to influence waveforms.

[0156] The embodiments herein can thus be directed to a cold, scalable controller. The suite of components disclosed herein can be used to create the preferred system-level embodiment. The controller can be described as an RQL-adiabatic transistor hybrid and/or a cryo CMOS-adiabatic transistor hybrid.

[0157] The controller can be capable of generating complex control sequences at high speed and with low power. A transmon quantum computer controller can be used as an example, where the controller needs to produce control sequences for calibration, qubit initialization, quantum computer arithmetic, and qubit readout.

[0158] While FIG. 1B shows that RQL meets the speed and power requirements, and FIGS. 10A-10C shows how to generate control signals, RQL gates are about 10,000× the size of CMOS gates, thus limiting the complexity of the controller that can fit on a chip.

[0159] The preferred embodiment raises the complexity limit by organizing the RQL logic into an FPGA as illustrated in FIG. 11, or another reconfigurable structure. The RQL logic is then reconfigured on the fly to produce the control sequences one at a time, thus increasing the apparent number of SFQ gates by a principle similar to timesharing.

[0160] However, the control sequences should follow one another without the control signals stopping during reconfiguration and stalling the quantum computer, not only wasting time but perhaps allowing the system's state to decay, such as qubits decohering. To reduce the possibility of stalls, the embodiments can include a configuration buffer, as illustrated in FIG. 13.

[0161] For example, as illustrated in FIG. 13, a system 1300 can have four modes of operation, each of which is specified by an FPGA with k configuration bits or control points. An external processor 1305 directs the source of control signals to create four sets of k control signals sequentially. With the multiplexer 1310 set to select the load input using the load/run control 1320, the four sets are loaded into the k-bit wide, four-stage shift register 1315. Switching the multiplexer 1310 to the run position, each clock of the shift register 1315 exposes the FPGA reconfigurable logic 1320 to the next mode in rotating sequence. While the 2LAL shift register 1315 must be clocked at, for example 4 MHz, for energy efficiency, this is fast enough to completely reconfigure the FPGA 1320 within the decoherence time of a qubit. As an option, the path labeled “potential branch” 1325 could convey information from the controlled payload that forces a reconfiguration, including to a configuration out of the normal rotation pattern, thus giving reconfiguration some of the capability of a standard computer's branch instruction.

[0162] The configuration buffer can comprise a k-bit wide by 4-stage cyclic 2LAL shift register 1320, where the number k corresponds to the number of FPGA configuration bits and the buffer's k-bit output is used as a form of tapped memory to configure the FPGA.

[0163] An exemplary operating sequence associated with the system 1300 illustrated in FIG. 13, using rough timing numbers, is provided below. It should be appreciated that this example is for illustrative purposes, and other operational parameters and numbers may be used in other embodiments.

[0164] After power-on, an external processor loads the four k-bit configuration sequences into the k×4-bit configuration buffer. This can be done serially and can take less than a few seconds. The configuration buffer is shifted so the FPGA configuration for calibration appears on the k outputs, leaving the RQL FPGA ready to calibrate the transmons. The RQL clock is turned on at, for example, 5 GHz, and generates the calibrating sequence until the external processor decides to turn off the RQL clock.

[0165] The external processor commands the clock generator (as shown in FIG. 3) to create four phases of the 4 MHz combined clock and power supply, rotating the contents of the configuration buffer in 250 ns so the configuration for qubit initialization appears. The RQL clock is turned on and performs qubit initialization, which takes, say 5 μs, after which the external processor turns off the RQL clock.

[0166] The external processor commands the clock generator to shift the configuration buffer again, loading the quantum computer arithmetic configuration in 250 ns. The RQL clock is turned on for, say 100 μs, or however long the qubits can operate without undue risk of decohering. The external processor shifts to the readout configuration, performs readout, and the process completes.

[0167] This controller is viable because the timings fit with each other. While the cryogenic adiabatic transistor circuits must run slowly due to the slow speed of the gates in scaling step 3 of table I, the architecture proposed in FIGS. 7 and 13 can carry out an FPGA reconfiguration in 250 ns. While 250 ns is a long time compared to the 200 μs clock period of RQL, it is much shorter than the decoherence time of current qubits. Thus, the embodiments are useful with both the technology present at the time of this writing and are expected to improve further as transmon coherence times improve through expected advances in that technology.

[0168] However, FIG. 13 also includes a feedback path (i.e. “alternative branch” 1325) for adaptive control. Each configuration can allocate a small amount of RQL logic to detect conditions that require a complex response. For example, a quantum error correction circuit will usually conclude that there has been no error. In the improbable but important circumstance that an error is detected, the error correction process may be complex enough to require reconfiguration of the FPGA to generate a completely different control sequence. So, the RQL branch signal can force a change in the shift register without direct involvement of the external processor. Other embodiments can allow a jump to a configuration outside the normal rotation pattern, giving the FPGA reconfiguration some of the capability of a standard computer's branch instruction.

[0169] There are multiple other embodiments of the configuration buffer. The configuration buffer can be a shift register of different dimensions, a structure with an access pattern different from a cycle, or multiple copies of itself running independently. The system does not have to be exclusively dedicated to controllers. For example, the system could have independent control signal generators such as in FIG. 8A or FIG. 9, or special memories as in FIG. 7.

[0170] In addition to the four exemplary quantum computer control sequences, control sequences can be created for different quantum error correction codes, such as 5-bit, 7-bit, or surface codes. This can allow a quantum computer to support any code without changing hardware. The same controller architecture can apply to a cryogenic sensor array that identifies extrasolar planets via a control sequence in the FPGA. The FPGA configuration can change as more is known about a potential planet, or as improved algorithms are discovered. This also applies to subroutines in either classical or quantum algorithms. One algorithm might use 8-bit integer data types whereas another might use 150-bit integers. In fact, a single algorithm might use integers of several word sizes. A control sequence can be developed for each different integer size and loaded into the FPGA on demand.

[0171] The embodiments herein are directed to a cold, scalable controller that not only implements the cryogenic adaptation of Rent's rule for scaling, and also uses cryogenic adiabatic transistors circuits as a highly flexible technology that can form a hybrid with multiple alternative technologies, at multiple temperatures, and in consideration of various energy-delay tradeoffs.

[0172] The embodiments illustrated herein have had three stages defined at nominally 300 K, 4 K, and 0.015 K respectively, but alternative embodiments can be created for two or more stages at any temperatures down to a temperature ratio of 10:1 between the warmest and coldest. It should be understood that the embodiments are still viable in other temperature ratios (e.g. 2:1), with the expectation that some of the benefits of the disclosed embodiments decrease as the temperature of the stages converge toward a single temperature. The term “room temperature” is used to represent the approximate temperature of earth's environment, which is the heat bath for terrestrial systems. However, embodiments can be extended to other environments where the heat bath is at a lower temperature, such as space, or higher temperature, such as under the Earth's surface.

[0173] CMOS HP and RQL have been described as technology examples for the hybrid because their parameters are readily available, as illustrated in FIG. 1B. However, other Beyond CMOS devices may also be used in the context of cryogenic operation. There are also other circuit designs that will have the same qualitative behavior as CMOS, 2LAL, and RQL such as Split-Level Charge Recovery Logic (SCRL), Efficient Charge Recovery Logic (2N2P or ECRL), 2N2N2P, Positive Feedback Adiabatic Logic (PFAL), Differential Cascode Pre-resolve Adiabatic Logic (DCPAL), Energy-efficient Rapid Single Flux Quantum (ERSFQ), Adiabatic Quantum Flux Parametron (AQFP), and purpose-built adiabatic memories, all of which can be implemented in accordance with embodiments disclosed herein.

[0174] FIGS. 14-16 are provided as exemplary diagrams of data-processing environments in which embodiments of the present invention may be implemented. It should be appreciated that FIGS. 14-16 are only exemplary and are not intended to assert or imply any limitation with regard to the environments in which aspects or embodiments of the disclosed embodiments may be implemented. Many modifications to the depicted environments may be made without departing from the spirit and scope of the disclosed embodiments.

[0175] A block diagram of a cold-capable computer system 1400 that executes programming for implementing parts of the methods and systems disclosed herein is shown in FIG. 14. A computing device in the form of a computer 1410 includes one or more processing units 1402 operating at the environmental, or room, temperature, each of which may include additional processing units 1440 and 1441 operating at lower temperatures t, designated as performing function f.sub.t and a payload 1442 operating at the lowest temperature and performing function designated q(N), where N is the computational scale. The payload may contain additional input and or output 1443 for data at the lowest temperature which may connect to the external world via a tunnel 1444 to the environmental temperature. Processor 1402 is configured to interface with sensors, peripheral devices, and other elements disclosed herein may include memory 1404, removable storage 1412, and non-removable storage 1414. Memory 1404 may include volatile memory 1406 and non-volatile memory 1408. Computer 1410 may include or have access to a computing environment that includes a variety of transitory and non-transitory computer-readable media such as volatile memory 1406 and non-volatile memory 1408, removable storage 1412 and non-removable storage 1414. Computer storage includes, for example, random access memory (RAM), read only memory (ROM), erasable programmable read-only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD ROM), Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage, or other magnetic storage devices, or any other medium capable of storing computer-readable instructions as well as data including image data.

[0176] Computer 1410 may include or have access to a computing environment through cold input or output 1443, input 1416, output 1418, and a communication connection 1420. The computer may operate in a networked environment using a communication connection 1420 or cold input or output 1443 to connect to one or more remote computers, remote sensors, detection devices, hand-held devices, multi-function devices (MFDs), mobile devices, tablet devices, mobile phones, Smartphones, or other such devices. The remote computer may also include a personal computer (PC), server, router, network PC, RFID enabled device, a peer device or other common network node, or the like. The communication connection may include a Local Area Network (LAN), a Wide Area Network (WAN), Bluetooth connection, or other networks. This functionality is described more fully in the description associated with FIG. 15 below.

[0177] Output 1418 is most commonly provided as a computer monitor, but may include any output device. Output 1418 and/or input 1416 may include a data collection apparatus associated with computer system 1400. In addition, input 1416, which commonly includes a computer keyboard and/or pointing device such as a computer mouse, computer track pad, or the like, allows a user to select and instruct computer system 1400. A user interface can be provided using output 1418 and input 1416. Output 1418 may function as a display for displaying data and information for a user, and for interactively displaying a graphical user interface (GUI) 1430.

[0178] Note that the term “GUI” generally refers to a type of environment that represents programs, files, options, and so forth by means of graphically displayed icons, menus, and dialog boxes on a computer monitor screen. A user can interact with the GUI to select and activate such options by directly touching the screen and/or pointing and clicking with a user input device 1416 such as, for example, a pointing device such as a mouse and/or with a keyboard. A particular item can function in the same manner to the user in all applications because the GUI provides standard software routines (e.g., module 1425) to handle these elements and report the user's actions. The GUI can further be used to display the electronic service image frames as discussed below.

[0179] Computer-readable instructions, for example, program module or node 1425, which can be representative of other modules or nodes described herein, are stored on a computer-readable medium and are executable by the processing unit 1402 of computer 1410. Program module or node 1425 may include a computer application. A hard drive, CD-ROM, RAM, Flash Memory, and a USB drive are just some examples of articles including a computer-readable medium.

[0180] FIG. 15 depicts a graphical representation of a quantum-enhanced network of data-processing systems 1500 in which aspects of the present invention may be implemented. Quantum-enhanced network data-processing system 1500 is a network moving either classical data or quantum, qubit-based data amongst computers or other such devices such as mobile phones, smartphones, sensors, detection devices, controllers and the like in which embodiments of the present invention may be implemented. Note that the system 1500 can be implemented in the context of a software module such as program module 1425. The system 1500 includes a network 1502 in communication with one or more clients 1510, 1512, and 1514. Quantum/classical network 1502 may also be in communication with one or more device 1504, servers 1506, and storage 1508. Quantum/classical network 1502 is a medium that can be used to provide communications links between various devices and computers connected together within a networked data processing system such as computer system 1400. Quantum/classical network 1502 may include connections such as wired communication links, wireless communication links of various types, fiber optic cables, quantum, or quantum encryption, or quantum teleportation networks, etc. Some types of quantum, qubit-based data will need to connect through special cold electronic portals such as 1444. Quantum/classical network 1502 can communicate with one or more servers 1506, one or more external devices such as the external processor 1305, a controller, actuator, sensor, or other such device 1504, and a memory storage unit such as, for example, memory or database 1508. It should be understood that device 1504 may be embodied as an external processor 1305, detector device, microcontroller, controller, receiver, transceiver, or other such device.

[0181] In the depicted example, device 1504, server 1506, and clients 1510, 1512, and 1514 connect to quantum/classical network 1502 along with storage unit 1508. Clients 1510, 1512, and 1514 may be, for example, personal computers or network computers, handheld devices, mobile devices, tablet devices, smartphones, personal digital assistants, microcontrollers, recording devices, MFDs, other cold-capable computer systems, etc. Cold-capable computer system 1400 depicted in FIG. 14 can be, for example, a client such as client 1510 and/or 1512.

[0182] Cold-capable computer system 1400 can also be implemented as a server such as server 1506, depending upon design considerations. In the depicted example, server 1506 provides data such as boot files, operating system images, applications, and application updates to clients 1510, 1512, and/or 1514. Clients 1510, 1512, and 1514 and external device 1504 are clients to server 1506 in this example. Network data-processing system 1500 may include additional servers, clients, and other devices not shown. Specifically, clients may connect to any member of a network of servers, which provide equivalent content.

[0183] In the depicted example, network data-processing system 1500 is the Internet with network 1502 representing a worldwide collection of networks and gateways that use the Transmission Control Protocol/Internet Protocol (TCP/IP) suite of protocols to communicate with one another. At the heart of the Internet is a backbone of high-speed data communication lines between major nodes or host computers consisting of thousands of commercial, government, educational, and other computer systems that route data and messages. Of course, network data-processing system 1500 may also be implemented as a number of different types of networks such as, for example, a quantum Internet, an intranet, a local area network (LAN), or a wide area network (WAN). FIGS. 14 and 15 are intended as examples and not as architectural limitations for different embodiments of the present invention.

[0184] FIG. 16 illustrates a software system 1600, which may be employed for directing the operation of the data-processing systems such as computer system 1400 depicted in FIG. 14. Software application 1605, may be stored in memory 1404, on removable storage 1412, or on non-removable storage 1414 shown in FIG. 14, and generally includes and/or is associated with a kernel or operating system 1610 and a shell or interface 1615. One or more application programs, such as module(s) or node(s) 1425, may be “loaded” (i.e., transferred from removable storage 1414 into the memory 1404) for execution by the data-processing system 1400. The data-processing system 1400 can receive user commands and data through user interface 1615, which can include input 1416 and output 1418, accessible by a user 1620. These inputs may then be acted upon by the computer system 1400 in accordance with instructions from operating system 1610 and/or software application 1605 and any software module(s) 1425 thereof.

[0185] Generally, program modules (e.g., module 1425) can include, but are not limited to, routines, subroutines, software applications, programs, objects, components, data structures, etc., that perform particular tasks or implement particular abstract data types and instructions. Moreover, those skilled in the art will appreciate that elements of the disclosed methods and systems may be practiced with other computer system configurations such as, for example, hand-held devices, mobile phones, smart phones, tablet devices, multi-processor systems, printers, copiers, fax machines, multi-function devices, data networks, microprocessor-based or programmable consumer electronics, networked personal computers, minicomputers, mainframe computers, servers, medical equipment, medical devices, and the like.

[0186] Note that the term module or node as utilized herein may refer to a collection of routines and data structures that perform a particular task or implements a particular abstract data type. Modules may be composed of two parts: an interface, which lists the constants, data types, variables, and routines that can be accessed by other modules or routines; and an implementation, which is typically private (accessible only to that module) and which includes source code that actually implements the routines in the module. The term module may also simply refer to an application such as a computer program designed to assist in the performance of a specific task such as word processing, accounting, inventory management, etc., or a hardware component designed to equivalently assist in the performance of a task.

[0187] The interface 1615 (e.g., a graphical user interface 1430) can serve to display results, whereupon a user 1620 may supply additional inputs or terminate a particular session. In some embodiments, operating system 1610 and GUI 130 can be implemented in the context of a “windows” system. It can be appreciated, of course, that other types of systems are possible. For example, rather than a traditional “windows” system, other operation systems such as, for example, a real time operating system (RTOS) more commonly employed in wireless systems may also be employed with respect to operating system 1610 and interface 1615. The software application 1605 can include, for example, module(s) 1425, which can include instructions for carrying out steps or logical operations such as those shown and described herein.

[0188] The following description is presented with respect to embodiments of the present invention, which can be embodied in the context of, or require the use of a data-processing system such as computer system 1400, in conjunction with program module 1425, and data-processing system 1500 and network 1502 depicted in FIGS. 14-3. The present invention, however, is not limited to any particular application or any particular environment. Instead, those skilled in the art will find that the systems and methods of the present invention may be advantageously applied to a variety of system and application software including database management systems, word processors, and the like. Moreover, the present invention may be embodied on a variety of different platforms including Windows, Macintosh, UNIX, LINUX, Android, Arduino and the like. Therefore, the descriptions of the exemplary embodiments, which follow, are for purposes of illustration and not considered a limitation.

[0189] Based on the foregoing, it can be appreciated that a number of embodiments, preferred and alternative, are disclosed herein. It should be appreciated that variations of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. In an embodiment, a system comprises an adiabatic circuit configured in a cryogenic environment, an external processor connected to the adiabatic circuit, the processor configured in a room temperature environment, wherein the processor can load and update control signal values stored in the adiabatic circuit, and at least one capacitive node connected to an output of the adiabatic circuit thereby producing an AC/DC cryogenic control signal.

[0190] In an embodiment, the adiabatic circuit further comprises a 1-of-N decoder driving each row of an array of access transistors through a gate of each of the access transistors. In an embodiment, the system further comprises a cryogenic column driver circuit, wherein each source on the access transistors in each column of the array of access transistors connect to the column driver circuit. In an embodiment, the column driver circuit comprises an adiabatic circuit thereby making the column driver circuit cryogenic adiabatic, allowing multiplexing of at least two digital signals. In an embodiment, the system further comprises an access transistor drain associated with each access transistor in the array of access transistors, wherein the access transistor drain is connected to the at least one capacitive node thereby creating a control signal.

[0191] In an embodiment, the system further comprises a superconductor FET wherein the control signal connects to a gate of the superconductor FET. In an embodiment, the system further comprises a semiconductor FET where the control signal connects to a gate of the semiconductor FET. In an embodiment, the system further comprises at least one of: an SFQ interrupter and a pass gate. In an embodiment, the system further comprises a Josephson junction circuit, wherein the semiconductor FET passes and blocks an SFQ pulse from the Josephson junction circuit.

[0192] In an embodiment, the adiabatic circuit comprises a tapped adiabatic SRAM. In an embodiment, the control signals are provided to at least one Josephson junction-based microwave circuit.

[0193] In an embodiment, the system further comprises a Josephson junction FPGA-like structure, wherein the control signals configure the Josephson junction-based FPGA-like structure. In an embodiment, the Josephson junction FPGA-like structure comprises at least one configurable logic element, and a programmable routing network. In an embodiment, the system further comprises a configuration buffer configured to store configurations that can be switched. In an embodiment, the system further comprises a branch signal provided from the at least one configurable logic element to the configuration buffer, wherein the branch signal causes a configuration change to a new configuration.

[0194] In an embodiment, the system further comprises at least one transistor, wherein a leakage current of the at least one transistor is rebalanced for cryogenic operation.

[0195] In an embodiment, the system further comprises a clock rate, wherein the clock rate is a monotonic function of an operating temperature.

[0196] In an embodiment, a system comprises a spin qubit quantum computer, an adiabatic circuit configured in a cryogenic environment, an external processor connected to the adiabatic circuit in an room temperature environment, wherein the processor can load and update control signal values stored in the adiabatic circuit, and at least one capacitive node connected to an output of the adiabatic circuit producing a control signal, wherein the control signal controls quantum operations of the spin qubit quantum computer.

[0197] In yet another embodiment a system comprises an adiabatic memory configured in a cryogenic environment, a digitized waveform stored in the adiabatic memory, and at least one multiplexer that creates a faster digitized waveform by reducing the width of the digitized waveform while increasing its speed. In an embodiment, the faster digitized waveform is provided to at least one Josephson junction-based microwave circuit.

[0198] It should be understood that various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.