INTEGRATED ELECTRONIC CIRCUIT WITH OFFSET COMPENSATION FOR AN IMPLANTABLE PROBE

Abstract

Integrated electronic circuit (10,12) for an implantable probe module, including a number of pixel circuits each having: an electrode for contacting a biological tissue; a biasing stage (M.sub.1,C) with a capacitor and a first transistor, which is coupled to the capacitor and injects in an input node (N.sub.IN) a biasing current (I.sub.bias) that depends upon the charge of the capacitor; a second transistor coupled to the electrode and to the input node (N.sub.IN); an amplifier coupled to a reference voltage (V.sub.ref1) and to the input node (N.sub.IN). The integrated electronic circuit (10,12) furthermore includes a feedback stage electrically controllable so as to be alternatively coupled or decoupled from each pixel circuit. The feedback stage forms, when coupled to a pixel circuit, an autozeroing loop that charges the corresponding capacitor so that the biasing current (I.sub.bias) is such that on the input node (N.sub.IN) a voltage substantially equal to the reference voltage is present.

Claims

1. An integrated electronic circuit (10,12) for an implantable probe module (11), comprising a number of pixel circuits (10) each including: an electrode (15) configured to contact a biological tissue; a biasing stage (M.sub.1,C) comprising a capacitor (C) and a first transistor (M.sub.1) having a respective control terminal and a respective first conduction terminal, which are respectively coupled to the capacitor (C) and to an input node (N.sub.IN), the first transistor (M.sub.1) being configured to inject in the input node (N.sub.IN) a biasing current (I.sub.bias) that depends upon the charge of the capacitor (C); a second transistor (M.sub.2), which has a respective control terminal and a respective first conduction terminal, which are respectively coupled to the electrode (15) and to the input node (N.sub.IN); an amplifier (20) having a first input terminal, configured to be set to a corresponding first reference voltage (V.sub.ref1), and a second input terminal, which is coupled to the input node (N.sub.IN); said integrated electronic circuit (10,12) furthermore comprising: a feedback stage (30) electrically controllable so as to be alternatively coupled or decoupled from the biasing stage (M.sub.1,C) and from the amplifier (20) of each pixel circuit (10), said feedback stage (30) being configured to form, when coupled to the biasing stage (M.sub.1,C) and to the amplifier (20) of a pixel circuit (10), an autozeroing loop that charges the corresponding capacitor (C) so that the corresponding biasing current (I.sub.bias) is such that on the corresponding input node (N.sub.IN) a voltage substantially equal to the corresponding first reference voltage (V.sub.ref1) is present.

2. The integrated electronic circuit (10,12) according to claim 1, wherein each pixel circuit (10) is configured in such a way that the respective second transistor (M.sub.2) is traversed by the same biasing current (I.sub.bias) injected by the corresponding first transistor (M.sub.1).

3. The integrated electronic circuit (10,12) according to claim 1, wherein the feedback stage (30) has a first input terminal, configured to be set to a second reference voltage (V.sub.ref2), a second input terminal and a respective output terminal, said feedback stage (30) furthermore comprising a feedback amplifier (32), the output terminal of which is coupled to the output terminal of the feedback stage (30); and wherein each pixel circuit (10) furthermore comprises a respective first switch (S.sub.1), which is controllable so as to couple/decouple the corresponding capacitor (C) to the output terminal of the feedback stage (30), and a respective second switch (S.sub.2), which is controllable so as to couple/decouple the output terminal of the corresponding amplifier (20) to the second input terminal of the feedback stage (30); and wherein the feedback stage (30) is electrically controllable so as to operate alternatively in a first configuration, in which a first and a second input terminal of the feedback amplifier (32) are respectively coupled to the first and to the second input terminals of the feedback stage (30), and in a second configuration, wherein the first and the second input terminals of the feedback amplifier (32) are respectively coupled to the output terminal of the feedback amplifier (32) and to the first input terminal of the feedback stage (30), in such a way that the feedback amplifier (32) operates as a voltage follower and transfers the second reference voltage (V.sub.ref2) to the output terminal of the feedback stage (30).

4. The integrated electronic circuit (10,12) according to claim 3, wherein the feedback amplifier (32) is a transconductance amplifier.

5. The integrated electronic circuit (10,12) according to claim 3, furthermore comprising a control circuitry (12) configured to control the first and second switches (S.sub.1,S.sub.2) of the pixel circuits (10) so as to couple the feedback stage (30) to one pixel circuit (10) at a time, said control circuitry (12) being furthermore configured to control the feedback stage (30) so that, when said feedback stage (30) is coupled to a pixel circuit (10), the feedback stage (30) operates in the first configuration; said control circuitry (12) being furthermore configured to alternate first periods of time (25), in which the pixel circuits (10) are individually coupled, in succession, to the feedback stage (30), with second periods of time (27), wherein the feedback stage (30) is decoupled from the pixel circuits (10) and operates in the second configuration.

6. The integrated electronic circuit (10,12) according to claim 1, wherein the second transistor (M.sub.2) of each pixel circuit (10) has a respective second conduction terminal, which is set to a first reference potential (GND); and wherein the first transistor (M.sub.1) of each pixel circuit (10) has a respective second conduction terminal, which is set to a second reference potential (VDD); and wherein the capacitor (C) of each pixel circuit (10) has a respective first terminal, set to the first or the second reference potential (VDD), and a respective second terminal, coupled to the control terminal of the corresponding first transistor (M.sub.1).

7. The integrated electronic circuit (10,12) according to claim 1, wherein the first and second transistors (M.sub.1,M.sub.2) of each pixel circuit (10) are P-channel enhancement MOSFET transistors.

8. The integrated electronic circuit (10,12) according to claim 1, furthermore comprising a biasing circuitry (12) coupled to the first input terminals of the amplifiers (20) of the pixel circuits (10) and configured to set, on each of said input terminals, a corresponding first reference voltage (V.sub.ref1).

9. The integrated electronic circuit (10,12) according to claim 1, wherein the amplifier (20) of each pixel circuit (10) is configured to generate an output signal (V.sub.OUT) on its own output terminal; said integrated electronic circuit (10,12) furthermore comprising a reading circuit (12) couplable in an electrically controllable manner to the pixel circuits (10), so as to read the respective output signals (V.sub.OUT).

10. The integrated electronic circuit (10,12) according to claim 1, wherein the amplifier (20) of each pixel circuit (10) is a transconductance amplifier.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0012] For a better understanding of the invention, embodiments thereof will now be disclosed, for merely illustrative and non-limiting purposes and with reference to the enclosed drawings, wherein:

[0013] FIG. 1 shows a block diagram of a multipixel probe;

[0014] FIG. 2 shows a block diagram of a probe module including the present integrated electronic circuit;

[0015] FIG. 3 shows a circuit diagram of a portion of the probe module shown in FIG. 2;

[0016] FIG. 4 schematically shows a section of a portion of a semiconductive plate;

[0017] FIG. 5 shows a block diagram of a circuitry;

[0018] FIG. 6 shows a circuit diagram of a portion of the probe module;

[0019] FIG. 7 shows examples of trends over time of signals;

[0020] FIGS. 8 and 9 show circuit diagrams of this integrated electronic circuit, under different operating conditions; and

[0021] FIG. 10 shows a further circuit diagram of the probe module.

DESCRIPTION OF EMBODIMENTS

[0022] FIG. 2 shows a multi-electrode and implantable type probe module 11, which includes a shared circuitry 12 and a plurality of pixels 10 equal to each other and electrically coupled to the shared circuitry 12. For example, the pixels 10 may be thirty-two in number. One of such pixel 10 is shown in FIG. 3 and is described below.

[0023] In detail, the pixel 10 comprises a supply terminal, which in use is set to a supply voltage VDD for example equal to 1.8V, and a ground (GND). Furthermore, the pixel 10 comprises a first and a second transistor M.sub.1, M.sub.2, which are referred to hereinbelow as the first and second biasing transistors M.sub.1, M.sub.2 respectively.

[0024] The first and second biasing transistors M.sub.1, M.sub.2 are P-channel enhancement MOSFET transistors. Furthermore, the source terminal of the first biasing transistor M.sub.1 is connected to the supply voltage VDD; the drain terminal of the first biasing transistor M.sub.1 is connected to the source terminal of the second biasing transistor M.sub.2, so as to form an input node N.sub.IN. The drain terminal of the second biasing transistor M.sub.2 is grounded; furthermore, and without any loss of generality, the source terminal of the second biasing transistor M.sub.2 is connected to the body terminal of the second biasing transistor M.sub.2.

[0025] As shown in FIG. 4, the gate terminal of the second biasing transistor M.sub.2 is electrically connected to a corresponding electrode 15, which in use is placed in contact with the biological tissue to be analysed (for example, brain tissue), so that on the electrode 15 there is an input voltage V.sub.in, which is equal to the sum of a direct voltage V.sub.DC and a so-called small signal voltage V.sub.in.

[0026] As shown in FIG. 4, the electrode 15 may be formed so that it passes through a dielectric region 16 of a plate (die) 18 in which the probe module 11 is formed, so that it contacts a metallization 19 (e.g., the upper metallization) of the plate 18, said metallization 19 being electrically connected to the gate terminal of the second biasing transistor M.sub.2.

[0027] The pixel 10 further comprises a capacitor C, which has a first and a second terminal, which are respectively connected to the gate terminal of the first biasing transistor M.sub.1 and to the supply voltage VDD.

[0028] The pixel 10 further comprises an amplifier 20 (for example, but not limited to, of the transconductance type), the positive input terminal of which is connected to the input node N.sub.IN, and the negative input terminal of which is connected to the shared circuitry 12, shown in FIG. 5, which sets the negative input terminal to a voltage V.sub.ref1 (for example equal to 600 mV).

[0029] The pixel 10 furthermore comprises three switches, which are referred to hereinbelow as the first and second calibration switches S.sub.1, S.sub.2 and as the output switch S.sub.OUT respectively. As described in greater detail below, the first and second calibration switches S.sub.1, S.sub.2 are controlled by a signal .sub.AZ[i], while the output switch S.sub.OUT is controlled by a signal read [i]. The signal .sub.AZ[i] and the signal read [i] are generated by the shared circuitry 12, as shown in FIG. 5 and as described in greater detail below. Furthermore, the output switch S.sub.OUT is interposed between the output terminal of the amplifier 20 and an output node N.sub.out, which in turn is coupled to the shared circuitry 12.

[0030] The shared circuitry 12 comprises a feedback amplifier stage 30 (shown in FIG. 3), which has a first and a second input terminal; the first input terminal is connected to the shared circuitry 12, so as to be set to a voltage V.sub.ref2 (for example, equal to 900 mV), while the second input terminal is connected to the first terminal of the second calibration switch S.sub.2, the second terminal of which is connected to the output terminal of the amplifier 20.

[0031] The feedback amplifier stage 30 has furthermore an output terminal, which is connected to a first terminal of the first calibration switch S.sub.1, the second terminal of which is connected to the first terminal of the capacitor C, and therefore also to the gate terminal of the first biasing transistor M.sub.1.

[0032] In greater detail, as shown in FIG. 6, the feedback amplifier stage 30 comprises a feedback amplifier 32, example, limited to, by a formed for but not transconductance amplifier, and a first, a second, a third and a fourth additional switch SA.sub.1, SA.sub.2, SA.sub.3, SA.sub.4.

[0033] The output terminal of the feedback amplifier 32 forms the output terminal of the feedback amplifier stage 30, therefore it is connected to the first terminal of the first calibration switch S.sub.1.

[0034] The first additional switch SA.sub.1 is interposed between the negative input terminal of the feedback amplifier 32 and the first input terminal of the feedback amplifier stage 30, which, as mentioned above, is set to the voltage V.sub.ref2.

[0035] The second additional switch SA.sub.2 is interposed between the positive input terminal of the feedback amplifier 32 and the first input terminal of the feedback amplifier stage 30.

[0036] The third additional switch SA.sub.3 is interposed between the negative input terminal of the feedback amplifier 32 and the output terminal of the feedback amplifier 32.

[0037] The fourth additional switch SA.sub.4 is interposed between the positive input terminal of the feedback amplifier 32 and the second input terminal of the feedback amplifier stage 30.

[0038] Furthermore, the first and fourth additional switches SA.sub.1, SA.sub.4 are controlled by a signal .sub.AZ generated by the shared circuitry 12. In particular, the first and fourth additional switches SA.sub.1, SA.sub.4 are closed when the signal .sub.AZ is equal to 1 and are open when the signal .sub.AZ is equal to 0.

[0039] The second and the third additional switches SA.sub.2, SA.sub.4 are controlled by a signal N.sub.AZ equal to the logical negation of the signal .sub.AZ. In this way, the second and third additional switches SA.sub.2, SA.sub.3 are open when the signal .sub.AZ is equal to 1 and are closed when the signal .sub.AZ is equal to 0.

[0040] In practice, the first and second biasing transistors M.sub.1, M.sub.2 form a so-called common drain stage, which has a unit gain and receives as input the input voltage V.sub.in. Furthermore, as explained below, the common drain stage allows to control the direct voltage present on the positive input terminal of the amplifier 20, which provides a high gain (e.g., higher than 40 dB) over a band extending, for example, up to 4 kHz. At the output from the amplifier there is an output signal V.sub.OUT, which, when read [i]=1, is provided on the output node N.sub.OUT, therefore it is provided to the shared circuitry 12, which reads it in a per se known way.

[0041] In greater detail, the shared circuitry 12 generates the signals .sub.AZ (and thus also N.sub.AZ) and .sub.AZ[i] so that the pixel 10 operates under different operating conditions.

[0042] In particular, as shown in FIG. 7, the signal .sub.AZ is a signal that provides for an alternation of bursts of pulses (denoted with 25) and of sensing periods (one shown in FIG. 7, where it is denoted with 27). Each pulse burst 25 comprises a number of pulses equal to the number of pixels 10.

[0043] As far as instead the signal .sub.AZ[i] is concerned, however, it is relative to the i-th pixel 10. Furthermore, considering the i-th pixel 10, the corresponding signal .sub.AZ [i] is generated by the shared circuitry 12 so as to be equal to 1 only when the i-th pixel 10 is selected, otherwise it is equal to 0; furthermore, the signal .sub.AZ[i] has a single pulse (denoted with 29) for each pulse burst 25 of the signal .sub.AZ, said single pulse 29 being temporally aligned with a corresponding pulse of the pulse burst 25. In addition, when .sub.AZ[i]=1, .sub.AZ[j]=0 occurs for each j between 1 and 32, but other than i.

[0044] That being said, referring again to the pixel 10 shown in FIG. 3, it can operate under a calibration condition, which is given when .sub.AZ[i]=1, which also entails .sub.AZ=1; this condition is shown in FIG. 8.

[0045] In detail, the first and second calibration switches S.sub.1, S.sub.2 are closed, therefore the feedback amplifier 32 is coupled to the amplifier 20 and forms an autozeroing loop such that a voltage approximately equal to the voltage V.sub.ref1 is set on the input node N.sub.IN. In particular, the capacitor C is subject to a voltage such that the gate terminal of the first biasing transistor M.sub.1 is in turn subject to a voltage such that the first biasing transistor M.sub.1 injects in the input node NIN a biasing current I.sub.bias. The biasing current I.sub.bias therefore depends on the charge stored in the capacitor C and is precisely such that the input node N.sub.IN is set equal to the voltage V.sub.ref1.

[0046] Furthermore, thanks to the autozeroing loop, on the output terminal of the amplifier 20 there is a voltage approximately equal to the voltage V.sub.ref2, as shown again in FIG. 7.

[0047] Subsequently, when the signal .sub.AZ[i] returns to 0, the first and second calibration switches S.sub.1, S.sub.1 open and the pixel 10 operates under sensing conditions, shown in FIG. 9. In practice, the feedback amplifier stage 30 is decoupled from the amplifier 20 and the autozeroing loop opens.

[0048] Ideally, the capacitor C maintains the previously stored charge, therefore the biasing current I.sub.bias does not vary and the input node N.sub.IN remains at the voltage V.sub.ref1; consequently, the biasing of the positive input terminal of the amplifier 20 does not vary. Furthermore, the amplifier 20 operates in open loop and amplifies the input signal V.sub.IN present on the electrode 15, allowing a correct sensing thereof. Thus, while the pixel 10 operates under sensing conditions, the shared circuitry 12 can set read [i]=1, so that the same shared circuitry 12 can read the output signal V.sub.OUT, which includes a direct voltage contribution equal to the voltage V.sub.ref2 and a small signal contribution that is a function of the aforementioned small: signal voltage V.sub.in.

[0049] In fact, due to unavoidable losses, the charge present in the capacitor C tends to reduce, causing a reduction of the biasing current I.sub.bias and therefore a variation (reduction) of the voltage present on the input node N.sub.IN, with consequent reduction of the output signal V.sub.OUT, and in particular of the direct voltage component of the latter, as shown in FIG. 7. Precisely in order to prevent this reduction from bringing the terminal at the output from the amplifier 20 so close to a limit voltage V.sub.sat such that correct amplification is no longer possible, the shared circuitry 12 controls each pixel 10 so as to alternate calibration conditions, in which the voltage V.sub.ref1 is restored on the input node N.sub.IN, at sensing conditions, in which the input signal V.sub.IN is read.

[0050] Furthermore, during each period of time in which the pixel 10 operates under calibration conditions, the autozeroing loop cancels the impact on the biasing of the amplifier 20 of the DC offset affecting the electrode 15, that is, it compensates for the DC offset. In this regard, thanks to the fact that the biasing current I.sub.bias is injected in the input node N.sub.IN by a single transistor (in particular, the first biasing transistor M.sub.1), the interval of the DC offset values that can be compensated for (with the same voltage V.sub.ref1) is maximized, since the biasing current I.sub.bias can be reduced up to a minimum value I.sub.min which depends on the sizing of the first and second biasing transistors M.sub.1, M.sub.2. In this regard, the direct voltage on the input node N.sub.IN is equal to the sum between the direct voltage V.sub.DC of the input voltage V.sub.in and a direct voltage V.sub.DCAZ set by the autozeroing loop; in the presence of high values of the direct voltage V.sub.DC, the autozeroing loop reduces the direct voltage V.sub.DCAZ (to the limit, until it cancels it, if V.sub.DC=V.sub.ref1) tending to turn off the first biasing transistor M.sub.1 so as to reduce the biasing current I.sub.bias.

[0051] Still with reference to the biasing current I.sub.bias, the current flowing in the second biasing transistor M.sub.2 is precisely equal to the biasing current I.sub.bias, since no current flows in the positive input terminal of the amplifier 20. With regard to the signal .sub.AZ, when it is equal to 0, it happens that the second and third additional switches SA.sub.2, SA.sub.3 are closed, while the first and fourth additional switches SA.sub.1, SA.sub.4 are open. Consequently, as shown in FIG. 10, the feedback amplifier 32 operates as a voltage buffer and transfer the voltage V.sub.ref2 to its own output terminal, and thus also to the first terminal of the first calibration switch S.sub.1 of each pixel 10. In this way, the charge losses suffered by the capacitors C of the pixels 10 through the respective first calibration switches S.sub.1 during the sensing periods 27 are reduced, because the voltage at the ends of the first calibration switches S.sub.1 is controlled. The small charge losses that might occur are also reduced, considering a pulse burst 25 of the signal .sub.AZ, during each time interval between two successive pulses of the burst (one shown in FIG. 7, where it is denoted with 26).

[0052] According to a variant, the voltages V.sub.ref1 generated on the negative input terminals of the amplifiers 20 of the pixels 10 may vary from pixel to pixel. In other words, the shared circuitry 12 applies, on each negative input terminal of the amplifiers 20 of the pixels 10, a corresponding voltage V.sub.ref1, with the following benefits.

[0053] In general, the autozeroing loop is capable of compensating for DC offsets in the interval V.sub.ref1V, where V is proportional to the biasing current I.sub.bias, which however is subject to an upper limit depending on the dimensions of the first and second biasing transistors M.sub.1, M.sub.2, as well as on the stability conditions of the autozeroing loop. Therefore, high values of the voltage V.sub.ref1 are better suited to compensate for high values of the DC offset; on the contrary, in case the DC offset has a reduced value, the compensation is preferably obtained by adopting a reduced voltage V.sub.ref1.

[0054] That being said, since electrodes 15 of different pixels 10 may be subject to different DC offsets, in particular in the event that the probe module 11 includes a very large array of electrodes 15, the possibility of setting, for different pixels 10, different values of the respective voltages V.sub.ref1 (which are set on the negative input terminals of the respective amplifiers 20) allows to optimize, for each pixel 10, the compensation for the DC offset it experiences.

[0055] The advantages that the present integrated electronic circuit allows obtaining emerge clearly from the previous description. In particular, during the calibration step, the autozeroing loop including the feedback amplifier 32 allows to control the biasing current I.sub.bias that flows in the common drain stage and therefore allows to adjust the direct voltage present on the positive input terminal of the amplifier 20, compensating for the DC offset present in the voltage V.sub.in. Furthermore, since the biasing current I.sub.bias comes from a single transistor (in this case, the first biasing transistor M.sub.1), it is possible to compensate for high DC offsets, with the same voltage V.sub.ref1.

[0056] Furthermore, the Applicant has observed that the autozeroing loop is stable, despite the wide interval of values that can be assumed by the biasing current I.sub.bias.

[0057] It is finally clear that modifications and variants can be made to this integrated electronic circuit, without departing from the scope of the present invention, as defined by the enclosed claims.

[0058] For example, the capacitor C may be made in MIM (metal-insulator-metal) technology or by using the parasitic capacitance present on the gate terminal of the first biasing transistor M.sub.1.

[0059] For example, the negative and positive input terminals of each amplifier 20 and/or of the feedback amplifier may be reversed with respect to what is described.

[0060] Furthermore, the probe module 11 can be used together with other probe modules similar to it, so as to implement a system for recording electrical signals of biological origin with high parallelism.

[0061] Finally, the capacitor C can be grounded (GND), instead of to the supply voltage VDD.