METHOD AND DEVICE FOR DESIGNING RIS CONTROL SIGNAL IN WIRELESS COMMUNICATION SYSTEM

Abstract

Disclosed is a network entity including a transceiver; a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions stored in the memory, wherein the at least one processor is configured to receive, from a base station (BS), a reconfigurable intelligent surface (RIS) control signal including RIS reflective pattern information and configuration information for the RIS reflective pattern information, and control a reflective pattern of an RIS based on the RIS reflective pattern information and the configuration information for the RIS reflective pattern information.

Claims

1. A network entity comprising: a transceiver; a memory storing one or more instructions; and at least one processor configured to execute the one or more instructions stored in the memory, wherein the at least one processor is configured to receive, from a base station (BS), a reconfigurable intelligent surface (RIS) control signal including RIS reflective pattern information and configuration information for the RIS reflective pattern information, and control a reflective pattern of an RIS based on the RIS reflective pattern information and the configuration information for the RIS reflective pattern information.

2. The network entity of claim 1, wherein: the configuration information for the RIS reflective pattern information comprises information related to a slot offset, and the at least one processor is configured to control the reflective pattern of the RIS for each symbol based on the RIS reflective pattern information from a slot after the slot offset elapses from a reception time of the RIS control signal.

3. The network entity of claim 2, wherein: the RIS reflective pattern information comprises information related to a reflective pattern corresponding to each symbol in the slot, and the at least one processor is configured to control the reflective pattern of the RIS for each symbol based on the reflective pattern corresponding to each symbol.

4. The network entity of claim 2, wherein: the RIS reflective pattern information comprises information related to a number of reflective patterns corresponding to the slot and information related to a set of reflective patterns sequentially corresponding to symbols in the slot, the configuration information for the RIS reflective pattern information comprises information related to a starting symbol corresponding to each reflective pattern in the reflective pattern set, the at least one processor is configured to control the reflective pattern of the RIS for each symbol based on the information related to the number of reflective patterns corresponding to the slot, the information related to the set of reflective patterns sequentially corresponding to the symbols in the slot, and the information related to a starting symbol corresponding to each reflective pattern in the reflective pattern set.

5. The network entity of claim 2, wherein: the RIS reflective pattern information comprises information related to a number of reflective patterns corresponding to the slot and information related to a set of reflective patterns sequentially corresponding to symbols in the slot, the configuration information for the RIS reflective pattern information comprises information related to symbol length corresponding to each reflective pattern in the reflective pattern set, the at least one processor is configured to control the reflective pattern of the RIS for each symbol based on the information related to the number of reflective patterns corresponding to the slot, the information related to the set of reflective patterns sequentially corresponding to the symbols in the slot, and the information related to symbol length corresponding to each reflective pattern in the reflective pattern set.

6. The network entity of claim 1, wherein: the RIS reflective pattern information comprises information related to at least one signal transmitted in each period, the configuration information for the RIS reflective pattern information comprises information related to the period, and the at least one processor is configured to control a reflective pattern of the RIS based on the information related to the at least one signal in each period.

7. The network entity of claim 6, wherein: the information related to the at least one signal comprises information related to at least one reflective pattern corresponding to each of the at least one signal, the configuration information for the RIS reflective pattern information comprises information related to a system frame number (SFN) and a subframe number and information related to a starting symbol and symbol length corresponding to each of the at least one reflective pattern, and the at least one processor is configured to control a reflective pattern of the RIS based on the information related to the at least one reflective pattern and the information related to the starting symbol and the symbol length corresponding to each of the at least one reflective pattern in each period from the subframe number of the SFN.

8. The network entity of claim 6, wherein: the information related to the at least one signal comprises information related to at least one reflective pattern corresponding to each of the at least one signal, the configuration information for the RIS reflective pattern information comprises information related to a timing offset and information related to a starting symbol and symbol length corresponding to each of the at least one reflective pattern, and the at least one processor is configured to control a reflective pattern of the RIS based on the information related to the at least one reflective pattern and the information related to the starting symbol and the symbol length corresponding to each of the at least one reflective pattern in each period from a time when the timing offset elapses from a reception time of the IRS control signal.

9. The network entity of claim 6, wherein: the at least one signal transmitted in each period comprises a sync signal, and the at least one processor is configured to receive configuration information for the sync signal from the BS, identify configuration information for a plurality of sync signals including the sync signal based on the configuration information for the sync signal, and control a reflective pattern of the RIS in each period based on information related to a reflective pattern corresponding to each of the at least one of the plurality of sync signals and configuration information for the at least one sync signal.

10. The network entity of claim 9, wherein: the at least one processor is configured to identify when each of at least one physical random access channel (PRACH) occasion corresponding to each of the at least one sync signal occurs based on the configuration information for the sync signal, and control a reflective pattern of the RIS at a time when each PRACH occasion occurs in each period based on the information related to the reflective pattern corresponding to each of the at least one sync signal.

11. A method of operating a network entity in a wireless communication system, the method comprising: receiving, from a base station, a reconfigurable intelligence surface (RIS) control signal including RIS reflective pattern information and configuration information for the RIS reflective pattern information; and controlling a reflective pattern of an RIS based on the RIS reflective pattern information and the configuration information for the RIS reflective pattern information.

12. The method of claim 11, wherein: the configuration information for the RIS reflective pattern information comprises information related to a slot offset, and the controlling of a reflective pattern of the RIS comprises controlling a reflective pattern of the RIS for each symbol based on the RIS reflective pattern information from a slot after the slot offset elapses from a reception time of the RIS control signal.

13. The method of claim 12, wherein: the RIS reflective pattern information comprises information related to a reflective pattern corresponding to each symbol in the slot, and the controlling of a reflective pattern of the RIS comprises controlling a reflective pattern of the RIS for each symbol based on a reflective pattern corresponding to each symbol.

14. The method of claim 11, wherein: the RIS reflective pattern information comprises information related to at least one signal transmitted in each period, the configuration information for the RIS reflective pattern information comprises information related to the period, and the controlling of a reflective pattern of the RIS comprises controlling a reflective pattern of the RIS based on the information related to the at least one signal.

15. The method of claim 14, wherein the at least one signal transmitted in each period comprises a sync signal, and the method further comprises: receiving configuration information for the sync signal from the BS; and identifying configuration information for a plurality of sync signals including the sync signal based on the configuration information for the sync signal, wherein the controlling of a reflective pattern of the RIS comprises controlling a reflective pattern of the RIS in each period based on information related to a reflective pattern corresponding to each of the at least one of the plurality of sync signals and configuration information for the at least one sync signal.

Description

DESCRIPTION OF DRAWINGS

[0032] FIG. 1 illustrates a reconfigurable intelligence surface (RIS) based wireless communication system environment, according to an embodiment of the disclosure.

[0033] FIG. 2A illustrates an RIS based wireless communication system environment, according to an embodiment of the disclosure.

[0034] FIG. 2B illustrates an RIS based wireless communication system environment, according to an embodiment of the disclosure.

[0035] FIG. 3A illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0036] FIG. 3B illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0037] FIG. 4 illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0038] FIG. 5A illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0039] FIG. 5B illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0040] FIG. 5C illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0041] FIG. 5D illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0042] FIG. 5E illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0043] FIG. 6A illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0044] FIG. 6B illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0045] FIG. 6C illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0046] FIG. 6D illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0047] FIG. 6E illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0048] FIG. 7A illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0049] FIG. 7B illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0050] FIG. 7C illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0051] FIG. 7D illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0052] FIG. 7E illustrates a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0053] FIG. 8A illustrates an example of an RIS control signal when a base station (BS) transmits a signal in each period, according to an embodiment of the disclosure.

[0054] FIG. 8B illustrates an example of an RIS control signal when a BS transmits a signal in each period, according to an embodiment of the disclosure.

[0055] FIG. 9A illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0056] FIG. 9B illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0057] FIG. 9C illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0058] FIG. 9D illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0059] FIG. 10A illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0060] FIG. 10B illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0061] FIG. 10C illustrates an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0062] FIG. 11A illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0063] FIG. 11B illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0064] FIG. 11C illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0065] FIG. 11D illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0066] FIG. 11E illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0067] FIG. 11F illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0068] FIG. 11G illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0069] FIG. 11H illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0070] FIG. 12A illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0071] FIG. 12B illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0072] FIG. 12C illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0073] FIG. 12D illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0074] FIG. 12E illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0075] FIG. 12F illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0076] FIG. 12G illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0077] FIG. 12H illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0078] FIG. 12I illustrates an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0079] FIG. 13 is a flowchart illustrating a procedure in which an RIS controller controls a reflective pattern of an RIS, according to an embodiment of the disclosure.

[0080] FIG. 14 is a schematic block diagram of a configuration of a network entity, according to an embodiment of the disclosure.

[0081] FIG. 15 is a schematic block diagram of a configuration of a BS, according to an embodiment of the disclosure.

MODE FOR INVENTION

[0082] Operating principles of embodiments of the disclosure will now be described with reference to accompanying drawings. In the following descriptions of the disclosure, well-known functions or configurations are not described in detail because they would obscure the disclosure with unnecessary details. Further, the terms, as will be mentioned at a later time, are defined by taking functionalities in the disclosure into account, but may vary depending on practices or intentions of users or operators. Accordingly, the terms should be defined based on descriptions throughout this specification. Herein, the terms to identify access nodes, the terms to refer to network entities, the terms to refer to messages, the terms to refer to interfaces among network entities, the terms to refer to various types of identification information, etc., are examples for convenience of explanation. Accordingly, the disclosure is not limited to the terms as herein used, and may use different terms to refer to the items having the same meaning in a technological sense.

[0083] Advantages and features of the disclosure, and methods for attaining them will be understood more clearly with reference to the following embodiments of the disclosure, which will be described in detail later along with the accompanying drawings. The embodiments of the disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments of the disclosure are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the embodiments of the disclosure to those of ordinary skill in the art. Like numbers refer to like elements throughout the specification.

[0084] It will be understood that each block and combination of the blocks of a flowchart may be performed by computer program instructions. The computer program instructions may be loaded onto a processor of a universal computer, a special-purpose computer, or other programmable data processing equipment, and thus they generate means for performing functions described in the block(s) of the flowcharts when executed by the processor of the computer or other programmable data processing equipment. The computer program instructions may also be stored in computer-executable or computer-readable memory that may direct the computers or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-executable or computer-readable memory may produce an article of manufacture including instruction means that perform the functions specified in the flowchart blocks(s). The computer program instructions may also be loaded onto the computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide operations for implementing the functions specified in the flowchart block(s).

[0085] Furthermore, each block may represent a part of a module, segment, or code including one or more executable instructions to perform particular logic function(s). It is noted that the functions described in the blocks may occur out of order in some alternative embodiments. For example, two successive blocks may be performed substantially at the same time or in reverse order depending on the corresponding functions.

[0086] The term module (or sometimes unit) as used herein refers to a software or hardware component, such as field programmable gate array (FPGA) or application specific integrated circuit (ASIC), which performs some functions. However, the module is not limited to software or hardware. The module may be configured to be stored in an addressable storage medium, or to execute one or more processors. For example, the modules may include components, such as software components, object-oriented software components, class components and task components, processes, functions, attributes, procedures, subroutines, segments of program codes, drivers, firmware, microcodes, circuits, data, databases, data structures, tables, arrays, and variables. Functions served by components and modules may be combined into a smaller number of components and modules, or further divided into a larger number of components and modules. Moreover, the components and modules may be implemented to execute one or more central processing units (CPUs) in a device or security multimedia card. In embodiments, the module may include one or more processors.

[0087] Descriptions of some well-known technologies that possibly obscure the disclosure will be omitted, if necessary. Embodiments of the disclosure will now be described with reference to accompanying drawings.

[0088] Herein, terms to identify access nodes, terms to refer to network entities, terms to refer to messages, terms to refer to interfaces among network entities, terms to refer to various types of identification information, etc., are examples for convenience of explanation. Accordingly, the disclosure is not limited to the terms as herein used, and may use different terms to refer to the items having the same meaning in a technological sense.

[0089] Some of the terms and names defined by the 3rd generation partnership project (3GPP) long term evolution (LTE) will be used hereinafter. The disclosure is not, however, limited to the terms and definitions, and may equally apply to any systems that conform to other standards. In the disclosure, for convenience of explanation, eNode B (eNB) may be interchangeably used with gNode B (gNB). For example, a BS referred to as an eNB may also indicate a gNB. Furthermore, the term terminal or user equipment (UE) may refer not only to a cell phone, an NB-IoT device, and a sensor but also to another wireless communication device.

[0090] In the following description, a base station is an entity for performing resource allocation for a terminal, and may be at least one of a gNB, an eNB, a Node B, a base station (BS), a radio access unit, a base station controller, or a network node. The terminal may include a UE, a mobile station (MS), a cellular phone, a smart phone, a computer, or a multimedia system capable of performing a communication function. It is, of course, not limited thereto.

[0091] In the disclosure, a reconfigurable intelligence surface (RIS) refers to a device that forms reflective patterns with combinations of phases and/or amplitudes of respective reflecting elements (REs) included in a reflective plane and intelligently reflects an incident beam on the RIS in a desired direction according to the reflective patterns.

[0092] In the disclosure, an RIS codebook refers to a set of reflective patterns formed with combinations of phases and/or amplitudes of the respective REs included in the reflective plane of the RIS.

[0093] FIG. 1 illustrates an RIS based wireless communication system environment, according to an embodiment of the disclosure.

[0094] Referring to FIG. 1, the RIS based wireless communication system environment may include an RIS controller (or RC) 100, an RIS 120, a BS 140 and one or more UEs 160 and 180.

[0095] In an embodiment, the RIS controller 100 may generate a plurality of reflective patterns by combining a phase and/or amplitude corresponding to each of a plurality of REs included in a reflective plane of the RIS 120. For example, when the reflective plane of the RIS 120 includes N REs, the RIS controller 100 may generate the following M specific reflective patterns of the RIS by combining a phase and/or amplitude corresponding to each of the N REs.

.sub.m={.sub.m,1e.sup.j.sup.m,1,.sub.m,2e.sup.j.sup.m,2, . . . ,.sub.m,Ne.sup.j.sup.m,N},m=1,2, . . . ,M

[0096] where denotes an amplitude corresponding to each of N REs, denotes a phase corresponding to each of the N REs, and m denotes an RIS codeword index.

[0097] In an embodiment, the RIS controller 100 may be physically attached to the RIS 120 to control the RIS 120 or physically separated from the RIS 120 to control the RIS 120 through a control signal. It is, however, merely an example and how the RIS controller 100 controls the RIS 120 is not limited thereto.

[0098] Referring to FIG. 1, the one or more UEs 160 and 180 may or may not receive a signal transmitted by the BS 140 depending on their locations. For example, when the UE 180 is located in an area other than shades, the UE 180 may receive the signal transmitted by the BS 140. On the other hand, when the UE 160 is located in a shaded area, the UE 160 may not receive the signal transmitted by the BS 140. In this case, the RIS controller 100 may properly control a reflective pattern of the RIS 120 so that the UE 160 located in the shaded area is able to receive the signal transmitted by the BS 140. In other words, even though the UE 160 located in the shaded area may not directly receive the signal transmitted by the BS 140, it may receive a signal reflecting off the RIS 120.

[0099] In an embodiment of the disclosure, in a case that the BS 140 transmits a signal to the UE 160 through the RIS 120, the BS 140 may transmit an RIS control signal 110 to the RIS controller 100. For example, the BS 140 may transmit the RIS control signal 110 to the RIS controller 100 by L1 signaling or radio resource control (RRC) signaling. In this case, the BS 140 may configure a new physical control channel or a dedicated RIS control channel to transmit the RIS control signal 110, and transmit the RIS control signal 110 to the RIS controller 100 through the configured control channel. Alternatively, the BS 140 may transmit the RIS control signal 110 to the RIS controller 100 in a control resource set (CORESET). It is, however, merely an example and how the BS 140 transmits the RIS control signal 110 to the RIS controller 100 is not limited thereto.

[0100] In an embodiment of the disclosure, the RIS controller 100 may access the BS 140 according to a common initial access procedure before receiving the RIS control signal 110 from the BS 140. For example, the RIS controller 100 may receive a synchronization signal block (SSB) transmitted by the BS 140, and complete the initial access by performing a random access procedure based on the SSB. In this case, the RIS controller 100 may be connected to the BS 140 in the same band as a band in which the BS 140 provides services for the UE 160. (I.e., the RIS controller 100 may make an in-band connection to the BS 140.)

[0101] In an embodiment, the RIS controller 100 may control a reflective pattern of the RIS 120 based on the received RIS control signal 110 so that the UE 160 located in a shaded area is able to receive the signal transmitted by the BS 140. For example, the RIS controller 100 may reflect the signal transmitted by the BS 140 toward where the UE 160 is located by controlling a phase and/or amplitude corresponding to each of the plurality of REs based on the received RIS control signal 110.

[0102] FIGS. 2A and 2B illustrate an RIS based wireless communication system environment, according to an embodiment of the disclosure.

[0103] Referring to FIG. 2A, the RIS based wireless communication system environment may include an RIS controller 200, an RIS 220, a BS 240 and a plurality of UEs 260 to 290 located in shaded areas.

[0104] In an embodiment, in a case that the BS 240 transmits signals to the plurality of UEs 260 to 290 through the RIS 220, the BS 240 may transmit an RIS control signal 210 to the RIS controller 200. In this case, the RIS control signal 210 may include RIS reflective pattern information corresponding to a location of each of the plurality of UEs 260 to 290 and configuration information for the RIS reflective pattern information.

[0105] Referring to FIG. 2B, the RIS controller 200 may control a reflective pattern of the RIS 220 for each symbol based on the received RIS control signal 210 so that each of the plurality of UEs 260 to 290 is able to receive the signal transmitted by the BS 240.

[0106] In an embodiment, in a case that the BS 240 transmits a physical downlink control channel (PDCCH) to UE 1 260 in symbols 0 to 2 of a slot n, the BS 240 may transmit, to the RIS controller 200, the RIS control signal 210 including RIS reflective pattern information corresponding to the location of UE 1 260 and configuration information (symbols 0 to 2 of the slot n) for the RIS reflective pattern information. The RIS controller 200 may control the reflective pattern of the RIS 220 based on the received RIS reflective pattern information so that UE 1 260 may receive the PDCCH transmitted by the BS in symbols 0 to 2 of the slot n.

[0107] In an embodiment, in a case that the BS 240 transmits a channel state information reference signal (CSI-RS) to UE 2 270 in symbol 3 of the slot n, the BS 240 may transmit, to the RIS controller 200, the RIS control signal 210 including RIS reflective pattern information corresponding to the location of UE 2 270 and configuration information (symbol 3 of the slot n) for the RIS reflective pattern information. The RIS controller 200 may control the reflective pattern of the RIS 220 based on the received RIS reflective pattern information so that UE 2 270 may receive the CSI-RS transmitted by the BS 240 in symbol 3 of the slot n.

[0108] In an embodiment, in a case that the BS 240 transmits a physical downlink shared channel (PDSCH) to UE 3 280 in symbols 4 to 6 of the slot n, the BS 240 may transmit, to the RIS controller 200, the RIS control signal 210 including RIS reflective pattern information corresponding to the location of UE 3 280 and configuration information (symbols 4 to 6 of the slot n) for the RIS reflective pattern information. The RIS controller 200 may control the reflective pattern of the RIS 220 based on the received RIS reflective pattern information so that UE 3 280 may receive the PDSCH transmitted by the BS 240 in symbols 4 to 6 of the slot n.

[0109] In an embodiment, in a case that the BS 240 receives a physical uplink shared channel (PUSCH) from UE 4 290 in symbols 7 to 9 of the slot n, the BS 240 may transmit, to the RIS controller 200, the RIS control signal 210 including RIS reflective pattern information corresponding to the location of UE 4 290 and configuration information (symbols 7 to 9 of the slot n) for the RIS reflective pattern information. The RIS controller 200 may control the reflective pattern of the RIS 220 based on the received RIS reflective pattern information so that the BS 240 may receive the PUSCH transmitted by UE 4 290 in symbols 7 to 9 of the slot n.

[0110] FIGS. 3A and 3B illustrate an example of an RIS control signal, according to an embodiment of the disclosure.

[0111] In an embodiment, a BS may transmit, to an RIS controller, an RIS control signal in a certain slot. For example, the BS may transmit the RIS control signal to the RIS controller by L1 signaling in the certain slot.

[0112] In an embodiment, the RIS control signal may include information about a slot offset, and the RIS controller may control a reflective pattern of the RIS for each symbol based on the received RIS control signal from a slot after the lapse of the slot offset from a reception time of the RIS control signal. For example, when the RIS control signal includes information about slot offset K, K0, the RIS controller may control a reflective pattern of the RIS for each symbol of a slot separated by K slots from a slot in which the RIS control signal is received, based on the RIS reflective pattern information.

[0113] In an embodiment, when the information about the slot offset is transmitted to the RIS controller by L1 signaling, the RIS controller may set a new slot offset value in each slot. Alternatively, when the information about the slot offset is transmitted to the RIS controller by RRC signaling, the RIS controller may set the same slot offset value until receiving information about a new slot offset It is, however, merely an example, and how the RIS controller sets the slot offset value is not limited thereto.

[0114] In an embodiment, the RIS control signal may include information about a RIS codeword index .sub.m. When there are M RIS codeword indexes, the RIS codeword index .sub.m may be represented as a bitstream in a size of log.sub.2 M bits. For example, when M is 8, the RIS codeword index may be represented as a bitstream in a size of 3 bits as follows: [0115] [.sub.0 .sub.1 .sub.2 .sub.3 .sub.4 .sub.5 .sub.6 .sub.7]=[000 001 010 011 100 101 110 111]

[0116] In this case, the RIS codeword index may include an RIS off operation (an occasion when the RIS is not operating), which may be defined by all bits being 0, .sub.0.

[0117] In an embodiment, the RIS control signal may include information about a RIS codeword index to be applied to an arbitrary symbol. For example, when symbol length of a slot is S, an RIS codeword index to be applied to symbol s+1 may be defined as a bitstream as follows:

[00001]$b_0^{\left(s\right)}{b}_1^{\left(s\right)}.Math.b_{.Math.{\log }_{2}M.Math.-1}^{\left(s\right)},s=0,1,.Math.,S-1$

[0118] Referring to FIGS. 3A and 3B, shown is an RIS codeword index corresponding to each of 14 symbols in the slot in a case that the symbol length S is 14 and there are 4 RIS codeword indexes. In an embodiment, an RIS codeword index to be applied to symbol s+1 may be represented as follows:

b.sub.0.sup.(s)b.sub.1.sup.(s),s=0,1, . . . ,13

[0119] For example, when RIS codeword index .sub.0 corresponds to first symbol s=0 to fifth symbol s=4, b.sub.0.sup.(0)b.sub.1.sup.(0), . . . , b.sub.0.sup.(4)b.sub.1.sup.(4) may all be defined as 00. When RIS codeword index .sub.1 corresponds to sixth symbol s=5 to eighth symbol s=7, b.sub.0.sup.(5)b.sub.1.sup.(5), . . . , b.sub.0.sup.(7)b.sub.1.sup.(7) may all be defined as 01. When RIS codeword index .sub.2 corresponds to ninth symbol s=8 to twelfth symbol s=4, b.sub.0.sup.(8)b.sub.1.sup.(8), . . . , b.sub.0.sup.(11)b.sub.1.sup.(11) may all be defined as 10. When RIS codeword index .sub.3 corresponds to thirteenth symbol s=12 to fourteenth symbol s=13, b.sub.0.sup.(12)b.sub.1.sup.(12), . . . , b.sub.0.sup.(13)b.sub.1.sup.(13) may all be defined as 11.

[0120] In an embodiment, the RIS control signal may include information about a transfer mode flag, and depending on the transfer mode, symbol information to which the RIS codeword index is to be applied may be represented in a different manner. For example, when the information about the transfer mode flag indicates transfer mode 0, each symbol is allocated an RIS codeword index. When the information about the transfer mode flag indicates transfer mode 1, an RIS codeword index may be allocated to be applied for a certain symbol length. It is, however, merely an example, and how to name a transfer mode and how to represent the symbol information corresponding to each transfer mode are not limited thereto.

[0121] In the meantime, the information about the transfer mode flag may be transmitted by 1-bit L1 signaling or RRC signaling.

[0122] FIG. 4 illustrates an example of an RIS control signal, according to an embodiment of the disclosure.

[0123] In an embodiment, when the information about the transfer mode flag indicates transfer mode 0, the RIS control signal may include information about reflective patterns (or RIS codeword indexes) corresponding to all the symbols in a slot. For example, in a case that symbol length of the slot is S and there are M RIS codeword indexes, the RIS control signal may include an RIS codeword index bitstream in a size of S.Math.log.sub.2 M bits.

b.sub.0.sup.(0)b.sub.1.sup.(0). . . b.sub.log.sub.2 .sub.M-1b.sub.0.sup.(1)b.sub.1.sup.(1). . . b.sub.log.sub.2 .sub.M-1. . . b.sub.0.sup.(S-1)b.sub.1.sup.(S-1). . . b.sub.log.sub.2.sub.M- 1.sup.(S-1)

[0124] Referring to FIG. 4, the RIS controller may receive an RIS control signal 400 in slot n. In an embodiment, the RIS control signal 400 may include transfer mode flag information indicating transfer mode 0 and information about slot offset K. Furthermore, when symbol length S of the slot is 14 and there are 8 RIS codeword indexes, the RIS control signal 400 may include information about a reflective pattern corresponding to each of 14 symbols in the slot as follows: [0125] [.sub.7 .sub.1 .sub.1 .sub.5 .sub.5 .sub.6 .sub.6 .sub.4 .sub.4 .sub.2 .sub.0 .sub.3 .sub.3 .sub.7]

[0126] In this case, the information about the reflective patterns may be represented as an RIS codeword index bitstream corresponding to a size of 42 (=3.Math.14) bits as follows: [0127] [001 001 101 101 110 110 100 100 010 000 011 011 111]

[0128] In an embodiment, the RIS controller may control a reflective pattern of the RIS for each symbol of slot n+k after the lapse of K slots from the slot n in which the RIS control signal 400 is received, based on the received information about the reflective patterns.

[0129] FIGS. 5A to 5E illustrate an example of an RIS control signal, according to an embodiment of the disclosure.

[0130] Referring to FIG. 5A, when the information about the transfer mode flag indicates transfer mode 1, the RIS control signal may include information about a number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about symbols to which each reflective pattern in the reflective pattern set is to be applied. In an embodiment, the information about the number P of reflective patterns may be represented as a bitstream indicating P, the information about the set of reflective patterns sequentially corresponding to symbols in the slot as a first bitmap, and the information about symbols to which each reflective pattern in the reflective pattern set is to be applied as a second bitmap.

[0131] In an embodiment, the number P of reflective patterns corresponding to the arbitrary slot has a value between 1 and the symbol length S of the slot, and the RIS controller may identify a border between the first bitmap and the second bitmap based on the information about the number P of reflective patterns. Furthermore, the information about the number P of reflective patterns may be represented as a bitstream in a size of log.sub.2 S bits as follows:

[r.sub.0r.sub.1. . . r.sub.log.sub.2.sub.S-1]

[0132] In an embodiment, the information about the set of reflective patterns sequentially corresponding to the symbols in the slot may be represented as a set of P RIS codeword indexes among M RIS codeword indexes. For example, the information about the set of reflective patterns sequentially corresponding to the symbols in the slot may be represented as a bitstram (the first bitmap) in a size of P.Math.log.sub.2 M bits as follows:

[00002]$\left[b_0^{\left(0\right)}{b}_1^{\left(0\right)}.Math.b_{.Math.{\log }_{2}M.Math.-1}^{\left(0\right)}{b}_0^{\left(1\right)}{b}_1^{\left(1\right)}.Math.b_{.Math.{\log }_{2}M.Math.-1}^{\left(1\right)}.Math.b_0^{\left(P-1\right)}{b}_1^{\left(P-1\right)}.Math.b_{.Math.{\log }_{2}M.Math.-1}^{\left(P-1\right)}\right]=\left[{}^{\left(0\right)}{}^{\left(1\right)}.Math.{}^{\left(P-1\right)}\right]$

[0133] Bitstream .sup.(p) is a bitstream in a size of log.sub.2 M bits to be applied to the (p+1)-th, and indicates a value of one of the M RIS codeword indexes. In this case, each bitstream .sup.(p) may have the same value with different streams, but neighboring bitstreams do not have the same value.

[0134] In an embodiment, the information about symbols to which each reflective pattern in the reflective pattern set is to be applied may include information about a starting symbol corresponding to each reflective pattern in the reflective pattern set or information about symbol length corresponding to each reflective pattern in the reflective pattern set. In this case, the starting symbol may indicate the foremost symbol among one or more neighboring symbols corresponding to the same reflective pattern, and the symbol length may indicate the number of the one or more neighboring symbols corresponding to the same reflective pattern.

[0135] In an embodiment, when the information about symbols to which each reflective pattern in the reflective pattern set is to be applied includes the information about the starting symbol corresponding to each reflective pattern in the reflective pattern set, the information about the starting symbol may be represented by allocating 1 to a bit corresponding to the starting symbol. For example, when the symbol length of the slot is S, the information about the starting symbol corresponding to each reflective pattern in the reflective pattern set may be represented as a bitstream (the second bitmap) in an S bit size as follows:

[00003]$a^{\left(0\right)}{a}^{\left(1\right)}.Math.a^{\left(s-1\right)}$$a^{\left(s\right)}=\{\begin{array}{cc}1,& \mathrm{if}s=\mathrm{Index}\mathrm{of}\mathrm{starting}\mathrm{symbol}\\ 0,& \mathrm{otherwise}\end{array}$

[0136] In another embodiment, when the information about symbols to which each reflective pattern in the reflective pattern set is to be applied includes the information about the starting symbol corresponding to each reflective pattern in the reflective pattern set, the information about the starting symbol may be represented by expressing the index of the starting symbol in bits. For example, when the symbol length of the slot is S and the number of reflective patterns corresponding to an arbitrary slot is P, the index of a starting symbol corresponding to the (p+1)-th reflective pattern may be represented as a bitstream in a size of log.sub.2 S bits as follows:

[00004]$a_0^{\left(p\right)}{a}_1^{\left(p\right)}.Math.a_{.Math.{\log }_{2}S.Math.-1}^{\left(p\right)}\mathrm{for}p=0,1,.Math.P-1$

[0137] Accordingly, the information about the starting symbol corresponding to each reflective pattern in the reflective pattern set may be represented as a bitstream (the second bitmap) in a size of P.Math.log.sub.2 S bits as follows:

a.sub.0.sup.(0)a.sub.1.sup.(0). . . a.sub.log.sub.2.sub.S-1.sup.(0)a.sub.1.sup.(1). . . a.sub.log.sub.2.sub.S-1.sup.(1)a.sub.0.sup.(1). . . a.sub.0.sup.(P-1)a.sub.1.sup.(P-1). . . a.sub.log.sub.2.sub.S-1.sup.(P-1)

[0138] FIG. 5D illustrates bitstreams corresponding to indexes of starting symbols in a case that the symbol length S of the slot is 14, according to an embodiment of the disclosure. For example, when an index of a starting symbol is 4, the index of the starting symbol may be represented as 0100. When an index of a starting symbol is 10, the index of the starting symbol may be represented as 1010.

[0139] In an embodiment, when the information about symbols to which each reflective patterns in the reflective pattern set is to be applied includes the information about the symbol length corresponding to each reflective pattern in the reflective pattern set, the information about the symbol length may represent a value of the symbol length in bits. For example, when the symbol length of the slot is S and the number of reflective patterns corresponding to an arbitrary slot is P, the value of the symbol length corresponding to the (p+1)-th reflective pattern may be represented as a bitstream in a size of log.sub.2 S bits as follows:

[00005]$a_0^{\left(p\right)}{a}_1^{\left(p\right)}.Math.a_{.Math.{\log }_{2}S.Math.-1}^{\left(p\right)}\mathrm{for}p=0,1,.Math.P-1$

[0140] Accordingly, the information about the symbol length corresponding to each reflective pattern in the reflective pattern set may be represented as a bitstream (the second bitmap) in a size of P.Math.log.sub.2 S bits as follows:

a.sub.0.sup.(0)a.sub.1.sup.(0). . . a.sub.log.sub.2.sub.S-1.sup.(0)a.sub.1.sup.(1). . . a.sub.log.sub.2.sub.S-1.sup.(1)a.sub.0.sup.(1). . . a.sub.0.sup.(P-1)a.sub.1.sup.(P-1). . . a.sub.log.sub.2.sub.S-1.sup.(P-1)

[0141] FIG. 5E illustrates bitstreams corresponding to indexes of starting symbols in a case that the symbol length S of the slot is 14, according to an embodiment of the disclosure. For example, when a value of a symbol length is 4, the value of the symbol length may be represented as 0011. When a value of a symbol length is 10, the value of the symbol length may be represented as 1001.

[0142] FIG. 5B illustrates a bitstream included in an RIS control signal in a case that the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and a bit corresponding to the starting symbol is allocated 1, according to an embodiment. In this case, the length of the bitstream that, indicates P may be log.sub.2 S, the length of the first bitmap may be P.Math.log.sub.2 M, and the length of the second bitmap may be S. Accordingly, total length of the bitstream included in the RIS control signal may be as follows:

[00006]$.Math.{\log }_{2}S.Math.+P.Math..Math.{\log }_{2}M.Math.+S$

[0143] FIG. 5C illustrates a bitstream included in the RIS control signal in a case that the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and an index of the starting symbol is represented in bits or in a case that the RIS control signal includes information about symbol length corresponding to each reflective pattern in the reflective pattern set and a value of the symbol length is represented in bits. In this case, the length of the bitstream that indicates P may be log.sub.2 S, the length of the first bitmap may be P.Math.log.sub.2 M, and the length of the second bitmap may be P.Math.log.sub.2 S. Accordingly, total length of the bitstream included in the RIS control signal may be as follows:

[00007]$.Math.{\log }_{2}S.Math.+P.Math..Math.{\log }_{2}M.Math.+P.Math..Math.{\log }_{2}S.Math.$

[0144] Hence, in a case of S<P.Math.log.sub.2 S, with the RIS control signal including information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and a bit corresponding to the starting symbol being allocated 1, signaling overhead may be reduced.

[0145] In an embodiment, when information about a transfer mode flag indicates transfer mode 1, the BS may transmit information about how to represent the second bitmap to the RIS controller. For example, the BS may transmit the information about how to represent the second bitmap to the RIS controller in 2-bit L1 signaling or RRC signaling. However, when the method of representing the second bitmap is selected in advance and used, the BS may not transmit the information about how to represent the second bitmap to the RIS controller.

[0146] In an embodiment, when the BS fails to transmit the RIS control signal, the RIS controller may control the reflective patterns of the RIS based on a default RIS codeword index. The default RIS codeword index may indicate .sub.0 (RIS off operation) or an RIS codeword index right before the BS fails transmission of the RIS control signal, and the RIS controller may choose it by considering various scheduling environments.

[0147] FIGS. 6A to 6E illustrate a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0148] FIG. 6A illustrates an example of a reflective pattern or an RIS codeword index corresponding to each symbol in slot n+K. In an embodiment, symbol length S of the slot may be 14, and the number M of RIS codewords indexes may be 8.

[0149] Referring to FIG. 6A, RIS codeword index .sub.1 may correspond to symbols 0 to 3, and RIS codeword index .sub.5 may correspond to symbols 4 and 5. Furthermore, the RIS may not operate in symbols 6 and 7. (I.e., RIS codewords index .sub.0 may correspond to symbols 6 and 7.) RIS codeword index .sub.2 may correspond to symbols 8 to 10, and RIS codeword index .sub.3 may correspond to symbols 11 and 13.

[0150] FIG. 6B illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 6A in a case that information about the transmission mode flag indicates transfer mode 0. In an embodiment, as the information about the transfer mode flag indicates transfer mode 0, the RIS control signal may include information about a reflective pattern (or an RIS codeword index) corresponding to each symbol in the slot. Accordingly, the RIS control signal may include a bitstream in a size of 42 (=14.Math.log.sub.2 8) bits as follows: [0151] [001001101101000000010010010011011011]

[0152] FIG. 6C illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 6A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about a number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about a starting symbol corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the starting symbol may be represented by allocating 1 to a bit corresponding to the starting symbol.

[0153] Referring to FIG. 6A, as 5 reflective patterns or RIS codeword indexes (.sub.1.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3) are applied to slot n+K, the number P of the reflective patterns is 5 and a bitstream that represents P is 0101. Furthermore, as indexes of starting symbols corresponding to the respective 5 RIS codeword indexes are {0, 4, 6, 8, 11}, the second bitmap may be represented as [10001010100100] by allocating 1s to bits (first, fifth, seventh, ninth and twelfth bits) corresponding to the starting symbols. Accordingly, the RIS control signal may include a bitstream in a size of 33(=log.sub.2 14+5.Math.log.sub.2 8+14=4+15+14) bits as follows: [0154] [0101 001101000010011 10001010100100]

[0155] FIG. 6D illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 6A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about a number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about a starting symbol corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the starting symbol may be represented by indicating the index of the starting symbol in bits.

[0156] As described above, as 5 reflective patterns or RIS codeword indexes (.sub.1.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3) are applied to slot n+K, the number P of the reflective patterns is 5 and a bitstream that represents P is 0101. Furthermore, as indexes of the starting symbols corresponding to the respective 5 RIS codeword indexes are {0, 4, 6, 8, 11}, the second bitmap may be represented as [00000100011010001011] by expressing the indexes of the starting symbols in bits. (Refer to FG. 5D) Accordingly, the RIS control signal may include a bitstream in a size of 39(=log.sub.2 14+5.Math.log.sub.2 8+5.Math.log.sub.2 14=4+15+20) bits as follows: [0157] [0101 001101000010011 00000100011010001011]

[0158] FIG. 6E illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 6A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about the number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about symbol length corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the symbol length may be represented by indicating a value of the symbol length in bits.

[0159] As described above, as 5 reflective patterns or RIS codeword indexes (.sub.1.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3) are applied to slot n+K, the number P of the reflective patterns is 5 and a bitstream that represents P may be 0101. Furthermore, as values of the symbol length corresponding to the respective 5 RIS codeword indexes are {4, 2, 2, 3, 3}, the second bitmap may be represented as [00110001000100100010] by expressing the values of the symbol length in bits. (Refer to FG. 5E) Accordingly, the RIS control signal may include a bitstream in a size of 39(=log.sub.2 14+5.Math.log.sub.2 8+5.Math.log.sub.2 14=4+15+20) bits as follows: [0160] [0101 001101000010011 00110001000100100010]

[0161] In the meantime, referring to FIGS. 6A to 6E, in a case that the bitstream corresponding to the reflective patterns of the RIS is represented based on transfer mode 1, it may be represented in a smaller number of bits than in the case of being represented based on transfer mode 0. Furthermore, when the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and 1 is allocated to a bit corresponding to a starting symbol, the bitstream corresponding to the reflective patterns of the RIS may be represented in a smaller number of bits than in a case that the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and the index of the starting symbol is represented in bits and than in a case that the RIS control signal includes information about symbol length corresponding to each reflective pattern in the reflective pattern set and a value of the symbol length is represented in bits.

[0162] FIGS. 7A to 7E illustrate a method of designing an RIS control signal, according to an embodiment of the disclosure.

[0163] FIG. 7A illustrates an example of a reflective pattern or an RIS codeword index corresponding to each symbol in slot n+K. In this case, symbol length S of the slot may be 14, and the number M of RIS codewords indexes may be 8.

[0164] Referring to FIG. 7A, the RIS may not operate in symbols 0, 3, 4, 7 and 13. (I.e., RIS codewords index .sub.0 may correspond to symbols 0, 3, 4, 7 and 13.) RIS codeword index .sub.1 may correspond to symbols 1 and 2, and RIS codeword index .sub.5 may correspond to symbols 5 and 6. Furthermore, RIS codeword index .sub.2 may correspond to symbols 8 to 10, and RIS codeword index .sub.3 may correspond to symbols 11 and 12.

[0165] FIG. 7B illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 7A in a case that information about the transmission mode flag indicates transfer mode 0. In an embodiment, as the information about the transfer mode flag indicates transfer mode 0, the RIS control signal may include information about a reflective pattern or information about an RIS codeword index corresponding to each symbol in the slot. Accordingly, the RIS control signal may include a bitstream in a size of 42(=14.Math.log.sub.2 8) bits as follows: [0166] [001001001001101101000000010010010011011011]

[0167] FIG. 7C illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 7A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about the number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about a starting symbol corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the starting symbol may be represented by allocating 1 to a bit corresponding to the starting symbol.

[0168] Referring to FIG. 7A, as 8 reflective patterns or RIS codeword indexes .sub.0.fwdarw..sub.1.fwdarw..sub.0.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3.fwdarw..sub.0 are applied to slot n+K, the number P of the reflective patterns is 8 and a bitstream that represents P may be 1000. Furthermore, as indexes of starting symbols corresponding to the respective 8 RIS codeword indexes are {0, 1, 3, 5, 7, 8, 11, 13}, the second bitmap may be represented as [11010101100101] by allocating 1s to bits (first, second, fourth, sixth, eighth, ninth, twelfth and fourteenth bits) corresponding to the starting symbols. Accordingly, the RIS control signal may include a bitstream in a size of 42(=log.sub.2 14+8.Math.log.sub.2 8+14=4+24+14) bits as follows: [0169] [1000 000001000101000010011000 11010101100101]

[0170] FIG. 7D illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 7A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about the number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about a starting symbol corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the starting symbol may be represented by indicating the index of the starting symbol in bits.

[0171] As described above, as 8 reflective patterns or RIS codeword indexes .sub.0.fwdarw..sub.1.fwdarw..sub.0.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3.fwdarw..sub.0 are applied to slot n+K, the number P of the reflective patterns is 8 and a bitstream that represents P is 1000. Furthermore, as indexes of the starting symbols corresponding to the respective 8 RIS codeword indexes are {0, 1, 3, 5, 7, 8, 11, 13}, the second bitmap may be represented as [00000001001101010111100010111101] by expressing the indexes of the starting symbols in bits. (Refer to FG. 5D) Accordingly, the RIS control signal may include a bitstream in a size of 60(=log.sub.2 14+8.Math.log.sub.2 8+8.Math.log.sub.2 14=4+24+32) bits as follows: [0172] [1000 000001000101000010011000 00000001001101010111100010111101]

[0173] FIG. 7E illustrates an example of a bitstream corresponding to the reflective patterns as shown in FIG. 7A in a case that information about the transmission mode flag indicates transfer mode 1. In an embodiment, the RIS control signal may include information about the number P of reflective patterns corresponding to an arbitrary slot, information about a set of reflective patterns sequentially corresponding to symbols in the slot, and information about symbol length corresponding to each reflective pattern in the reflective pattern set. Furthermore, the information about the symbol length may be represented by indicating a value of the symbol length in bits.

[0174] As described above, as 8 reflective patterns or RIS codeword indexes .sub.0.fwdarw..sub.1.fwdarw..sub.0.fwdarw..sub.5.fwdarw..sub.0.fwdarw..sub.2.fwdarw..sub.3.fwdarw..sub.0 are applied to slot n+K, the number P of the reflective patterns is 8 and a bitstream that represents P may be 1000. Furthermore, as values of the symbol length corresponding to the respective 8 RIS codeword indexes are {1, 2, 2, 2, 1, 3, 2, 1}, the second bitmap may be represented as [00000001000100010000001000010000] by expressing the values of the symbol length in bits. (Refer to FG. 5E) Accordingly, the RIS control signal may include a bitstream in a size of 60(=log.sub.2 14+8.Math.log.sub.2 8+8.Math.log.sub.2 14=4+24+32) bits as follows: [0175] [1000 000001000101000010011000 00000001000100010000001000010000]

[0176] In the meantime, referring to FIGS. 7A to 7E, in a case that the bitstream corresponding to the reflective patterns of the RIS is represented based on transfer mode 0, it may be represented in a smaller number of bits than in the case of being represented based on transfer mode 1. Furthermore, when the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and 1 is allocated to a bit corresponding to a starting symbol, the bitstream corresponding to the reflective patterns of the RIS may be represented in a smaller number of bits than in a case that the RIS control signal includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set and the index of the starting symbol is represented in bits and than in a case that the RIS control signal includes information about symbol length corresponding to each reflective pattern in the reflective pattern set and a value of the symbol length is represented in bits.

[0177] FIG. 8A and FIG. 8B illustrate an example of an RIS control signal when a BS transmits a signal in each period, according to an embodiment of the disclosure.

[0178] Referring to FIG. 8A, the BS may transmit the same signal to one or more UEs through the RIS at particular intervals. For example, the BS may transmit a sync signal to a UE located in a shaded area at 5 ms (half frame) intervals. In this case, the signal transmitted at particular intervals may be a semi-persistent signal.

[0179] Referring to 8B, as the BS transmits the same signal to the UE located in a shaded area through the RIS at particular intervals, the RIS controller may set a reflective pattern of the RIS corresponding to the location of the UE in each period. For example, the reflective pattern of the RIS may be repeated at 5 ms (half frame) intervals.

[0180] In an embodiment, when the BS transmits the same signal to the UE located in the shaded area at particular intervals, the BS may transmit, to the RIS controller, an RIS control signal including information about the period and information about the RIS reflective pattern corresponding to each signal repeated in each period. For example, the BS may transmit, to the RIS controller, information about the period and information about the RIS reflective pattern corresponding to each signal by RRC signaling in advance. Accordingly, compared to a case that the BS transmits the RIS control signal to the RIS controller in each slot, signaling overhead may be reduced.

[0181] In an embodiment, the RIS controller may set an RIS reflective pattern corresponding to each signal repeated in each period from a particular time for particular duration and repeat the setting in each period based on the received RIS control signal.

[0182] It is, however, merely an example, and when the BS transmits the same signal to the UE located in the shaded area through the RIS in each particular period, the BS may transmit the RIS control signal to the RIS controller in each slot by L1 signaling. For example, as described above in connection with FIGS. 4 to 7E, the BS may transmit the RIS control signal including information about RIS reflective patterns corresponding to all symbols in the slot or information about an RIS reflective pattern corresponding to a particular symbol length by L1 signaling in each slot.

[0183] FIGS. 9A to 9D illustrate an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure.

[0184] Referring to FIG. 9A, the BS 940 may transmit a signal into a shaded area through an RIS 920 at particular intervals. For example, the BS 940 may transmit SSB1 and SSB2 to the shaded area through the RIS 920 at particular intervals.

[0185] FIGS. 9B and 9C illustrate an example of an RIS control signal 910 transmitted by the BS 940 to an RIS controller 900 in a case that the BS 940 transmits signals through the RIS 920 at particular intervals. In an embodiment, the RIS control signal 910 may include information about an RIS reflective pattern corresponding to each signal transmitted in each period and information about a starting symbol and symbol length corresponding to each RIS reflective pattern. Furthermore, the RIS control signal 910 may include information about a period and information about a time to apply the RIS reflective pattern.

[0186] In an embodiment, the information about the period included in the RIS control signal may be represented as a time unit, or represented as the number of slots, the number of frames, or the like. For example, the information about the period may be represented as a time unit such as 10 ms, or represented as 10 slots, 8 frames, or the like.

[0187] In an embodiment, the information about the time to apply the RIS reflective pattern included in the RIS control signal 910 may be represented as absolute time information or relative time information. For example, the information about the time to apply the RIS reflective pattern may be represented as accurate information such as system frame number (SFN), subframe number and/or slot number. Alternatively, the information about the time to apply the RIS reflective pattern may be represented as a timing offset .sub.t, allowing the RIS controller 900 to control a reflective pattern of the RIS based on the RIS control signal 910 from after the lapse of .sub.t from when receiving the RIS control signal 910.

[0188] Referring to FIGS. 9B and 9C, the RIS control signal 910 may include information indicating that a period for transmission of SSB1 and SSB2 is 10 ms. Furthermore, the RIS control signal 910 may include information indicating that the RIS reflective pattern is to be repetitively set at 10 ms intervals from a time at which SFN=9 and subframe number=0. The RIS control signal 910 may include {.sub.1, 4, 4} and {.sub.2, 16, 4} that indicate information about {RIS codeword index, starting symbol, symbol length} corresponding to SSB1 and SSB2, respectively.

[0189] In an embodiment, the RIS control signal 910 may be transmitted in one or more RRC messages. For example, as shown in FIG. 9B, information about {RIS codeword index, starting symbol, symbol length} corresponding to the respective SSB1 and SSB2 may be transmitted in one RRC message. Alternatively, as shown in FIG. 9C, information about {RIS codeword index, starting symbol, symbol length} corresponding to the respective SSB1 and SSB2 may be transmitted in different RRC messages. It is, however, merely an example, and the RIS control signal 910 may be transmitted in a manner different from what is described above.

[0190] Referring to FIG. 9D, the RIS controller 900 may set an RIS reflective pattern corresponding to each signal repeated in each period from a particular time for particular duration and repeat this in each period based on the received RIS control signal 910. For example, the RIS controller 900 may control a reflective pattern of the RIS 920 according to RIS codeword index .sub.1 corresponding to SSB1 during symbols 4 to 7 at 10 ms intervals from when SFN=9 and subframe number=0. Furthermore, the RIS controller 900 may control a reflective pattern of the RIS 920 according to RIS codeword index (corresponding to SSB2 during symbols 16 to 19 at 10 ms intervals from when SFN=9 and subframe number=0.

[0191] FIGS. 10A to 10C illustrate an example of a BS transmitting a signal through an RIS in each period, according to an embodiment of the disclosure. Contents overlapping FIGS. 9A to 9D will be omitted or described briefly.

[0192] Referring to FIG. 10A, a BS 1040 may transmit a signal to one or more UEs 1060 through an RIS 1020 at particular intervals. For example, the BS 1040 may transmit a CSI-RS through the RIS 1020 at particular intervals.

[0193] Referring to FIG. 10B, an RIS control signal 1010 may include information indicating that a period for transmission of the CSI-RS is 5 ms. Furthermore, the RIS control signal 1010 may include information indicating that the RIS reflective pattern is to be repetitively set at 5 ms intervals from a time at which SFN=20 and subframe number=0. The RIS control signal 1010 may include {.sub.1, 8, 2} that indicates information about {RIS codeword index, starting symbol, symbol length} corresponding to the CSI-RS.

[0194] Referring to FIG. 10C, an RIS controller 1000 may set an RIS reflective pattern corresponding to each signal repeated in each period from a particular time for particular duration and repeat this in each period based on the received RIS control signal 1010. For example, the RIS controller 1000 may control a reflective pattern of the RIS 1020 according to RIS codeword index .sub.1 corresponding to the CSI-RS during symbols 8 and 9 at 5 ms intervals from when SFN=20 and subframe number=0.

[0195] In an embodiment, subcarrier spacing set by each of the RIS controller and the BS may be the same or different from the other. For example, as shown in FIG. 9D, the RIS controller 900 and the BS 940 may set the same subcarrier spacing of 30 kHz. Alternatively, as shown in FIG. 10C, the RIS controller 1000 and the BS 1040 may set different subcarrier spacing of 30 kHz and 15 kHz, respectively.

[0196] FIGS. 11A to 11H illustrate an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure.

[0197] FIGS. 11A and 11B illustrate an example of an SSB operation situation of the BS 1140 before an RIS controller 1100 accesses the BS 1140. In an embodiment, the BS 1140 may transmit SSB0 to SSB7 at 10 ms intervals before the RIS controller 1100 accesses the BS 1140.

[0198] Referring to FIG. 11C, the RIS controller 1100 may receive the SSB7 and make initial access to the BS 1140 based on the SSB7. In an embodiment, the RIS controller 1100 may identify configuration information about a physical random access channel (PRACH) and SSBs in the initial access procedure based on the SSB7. For example, referring to FIG. 11D, the RIS controller 1100 may identify transmission times of SSB0 to SSB6 and frame boundaries based on the location of the received SSB7. Furthermore, the RIS controller 1100 may identify occurrence times of PRACH occasions corresponding to the respective SSB0 to SSB7 and frame boundaries based on the location of the received SSB7.

[0199] Referring to FIG. 11E, in a case that the BS 1140 is to transmit a signal to the UE 1160 through an RIS 1120, the BS 1140 may transmit an RIS control signal 1110 to the RIS controller 1100. For example, in a case that the BS 1140 is to transmit SSB6 and SSB7 to the UE 1160 based on the RIS 1120, the BS 1140 may transmit the RIS control signal 1110 to the RIS controller 1100.

[0200] In an embodiment, the RIS control signal 1110 may include information about a signal to be transmitted by the BS 1140 to the UE 1160 and a corresponding RIS codeword index set {SSB index i, .sub.i}. For example, the RIS control signal 1110 may include {SSB index 6, .sub.6} and {SSB index 7, .sub.7}.

[0201] Referring to FIGS. 11E and 11F, the RIS controller 1100 may control a reflective pattern of the RIS at particular intervals based on information about a signal included in the RIS control signal and a corresponding RIS codeword index set {SSB index i, .sub.i}. For example, the RIS controller 1110 may control a reflective pattern of the RIS 1120 according to an RIS codeword index .sub.6 corresponding to SSB 6 at a time of transmission of SSB6 at particular intervals. Alternatively, the RIS controller 1110 may control a reflective pattern of the RIS 1120 according to an RIS codeword index .sub.7 corresponding to SSB 7 at a time of transmission of SSB7 at particular intervals. Accordingly, the UE 1160 may receive the SSB6 and SSB7 reflecting off the RIS 1120.

[0202] Referring to FIGS. 11G and 11H, the RIS controller 1100 may control a reflective pattern of the RIS at particular intervals based on configuration information about a PRACH. For example, the RIS controller 1110 may control a reflective pattern of the RIS 1120 according to an RIS codeword index .sub.6 at a time of occurrence of a PRACH occasion corresponding to SSB 6 at particular intervals. Alternatively, the RIS controller 1110 may control a reflective pattern of the RIS 1120 according to an RIS codeword index .sub.7 at a time of occurrence of a PRACH occasion corresponding to SSB 7 at particular intervals. Accordingly, the BS 1140 may receive PRACH signals reflecting off the RIS 1120. In the meantime, configuration information about a PRACH may be obtained in a procedure of initial access of the RIS controller 1100 to the BS 1140.

[0203] FIGS. 12A to 121 illustrate an example of a BS transmitting a cell-specific signal through an RIS in each period, according to an embodiment of the disclosure. Contents overlapping FIGS. 11A to 11H will be omitted or described briefly.

[0204] FIGS. 12A and 12B illustrate an example of an SSB operation situation of a BS 1240 before an RIS controller 1200 accesses the BS 1240. In an embodiment, the BS 1240 may transmit SSB0 to SSB5 at 10 ms intervals before the RIS controller 1200 accesses the BS 1240.

[0205] Referring to FIG. 12C, the RIS controller 1200 may receive SSB5 and make initial access to the BS 1240 based on the SSB5. In an embodiment, the RIS controller 1200 may identify configuration information about a PRACH and an SSB in the initial access procedure based on the SSB5. For example, referring to FIG. 12D, the RIS controller 1200 may identify transmission times of SSB0 to SSB7 and frame boundaries based on the location of the received SSB5. Furthermore, the RIS controller 1200 may identify occurrence times of PRACH occasions corresponding to the respective SSB0 to SSB5 and frame boundaries based on the location of the received SSB5.

[0206] Referring to FIG. 12E, in a case that the BS 1240 is to transmit a signal to a UE 1260 through an RIS 1220, the BS 1240 may transmit an RIS control signal 1210 to the RIS controller 1200. For example, in a case that the BS 1240 is to transmit SSB6 and SSB7 to the UE 1260 based on the RIS 1220, the BS 1240 may transmit the RIS control signal 1210 to the RIS controller 1200.

[0207] In an embodiment, the RIS control signal 1210 may include information about a signal to be transmitted by the BS 1240 to the UE 1260 and a corresponding RIS codeword index set {SSB index i, .sub.i}. For example, the RIS control signal 1210 may include {SSB index 6, .sub.6} and {SSB index 7, .sub.7}.

[0208] Referring to FIGS. 12E and 12F, the RIS controller 1200 may control a reflective pattern of the RIS at particular intervals based on information about a signal included in the RIS control signal and a corresponding RIS codeword index set {SSB index i, .sub.i}. For example, the RIS controller 1210 may control a reflective pattern of the RIS 1220 according to an RIS codeword index 06 corresponding to SSB 6 at a time of transmission of SSB6 at particular intervals. Alternatively, the RIS controller 1210 may control a reflective pattern of the RIS 1220 according to an RIS codeword index (7 corresponding to SSB 7 at a time of transmission of SSB7 at particular intervals. Accordingly, the UE 1260 may receive SSB6 and SSB7 reflecting off the RIS 1220.

[0209] Referring to FIG. 12G, as the number of SSBs transmitted by the BS 1240 varies, configuration information about a PRACH corresponding to each SSB may be changed. For example, the BS 1240 may transmit 6 SSBs (SSB0 to SSB5) before the RIS controller 1200 accesses the BS 1240 and transmit 8 SSBs (SSB0 to SSB7) after the RIS controller 1200 accesses the BS 1240. Accordingly, occurrence times of PRACH occasions corresponding to the respective SSBs may be changed. For example, an occurrence time table 1270 of PRACH occasions obtained by the RIS controller 1200 in the initial access procedure may be changed into an occurrence time table 1280 of PRACH occasions.

[0210] Referring to FIG. 12H, when PRACH configuration information is changed, the BS 1240 may transmit configuration information 1250 about a new PRACH to the RIS controller 100. For example, the BS 1240 may transmit RRC parameters such as prach-ConfigurationIndex, msg1-FDM, ssb-perRACH-OccasionAndCB-PreamblesPerSSB that reflect the new configuration information to the RIS controller 100.

[0211] Referring to FIGS. 12H and 121, the RIS controller 1200 may control a reflective pattern of the RIS at particular intervals based on the configuration information 1250 about the new PRACH. For example, the RIS controller 1210 may control a reflective pattern of the RIS 1220 according to an RIS codeword index .sub.6 at a time of occurrence of a PRACH occasion corresponding to SSB 6 at particular intervals. Alternatively, the RIS controller 1210 may control a reflective pattern of the RIS 1220 according to an RIS codeword index .sub.7 at a time of occurrence of a PRACH occasion corresponding to SSB 7 at particular intervals. Accordingly, the BS 1240 may receive PRACH signals (PRACH occasions 6 and 7) reflecting off the RIS 1220.

[0212] In an embodiment, when the SSB configuration information is changed, the BS may transmit configuration information about a new SSB to the RIS controller. For example, when the SSB configuration information is changed, the BS may transmit information about a location and repetition periodicity for each SSB index to the RIS controller. Afterward, a procedure of FIGS. 11E to 11H may be performed.

[0213] In another embodiment, when the SSB and PRACH configuration information is changed, the BS may transmit configuration information about a new SSB and PRACH to the RIS controller. For example, when the SSB and PRACH configuration information is changed, the BS may transmit information about a location and repetition periodicity for each SSB index and information about PRACH transmission time and repetition periodicity to the RIS controller. Afterward, a procedure of FIGS. 12E to 121 may be performed.

[0214] FIG. 13 is a flowchart illustrating a procedure in which an RIS controller controls a reflective pattern of an RIS, according to an embodiment of the disclosure.

[0215] In operation S1300, the RIS controller may receive an RIS control signal including RIS reflective pattern information and configuration information for the RIS reflective pattern information from the BS.

[0216] In an embodiment, the RIS reflective pattern information may include information about a reflective pattern corresponding to each symbol in a slot. Furthermore, the configuration information for the RIS reflective pattern information may include information about a slot offset.

[0217] In an embodiment, the RIS reflective pattern information may include information about the number of reflective patterns corresponding to the slot and information about a set of reflective patterns sequentially corresponding to symbols in the slot. Furthermore, the configuration information for the RIS reflective pattern information may include information about a slot offset, and information about a starting symbol corresponding to each reflective pattern in the reflective pattern set. In this case, the information about the starting symbol may be represented by allocating 1 to a bit corresponding to the starting symbol, or represented by indicating an index of the starting symbol in bits.

[0218] In an embodiment, the RIS reflective pattern information may include information about the number of reflective patterns corresponding to the slot and information about a set of reflective patterns sequentially corresponding to symbols in the slot. Furthermore, the configuration information for the RIS reflective pattern information may include information about a slot offset, and information about symbol length corresponding to each reflective pattern in the reflective pattern set. In this case, the information about the symbol length may be represented by indicating a value of the symbol length in bits.

[0219] In an embodiment, the RIS reflective pattern information may include information about at least one signal transmitted in each period, and the configuration information for the RIS reflective pattern information may include information about the period.

[0220] In an embodiment, the information about the at least one signal transmitted in each period may include information about at least one reflective pattern corresponding to each of the at least one signal. Furthermore, the configuration information for the RIS reflective pattern information may include information about an SFN and a subframe number and information about a starting symbol and symbol length corresponding to each of the at least one reflective pattern.

[0221] In an embodiment, the information about the at least one signal transmitted in each period may include information about at least one reflective pattern corresponding to each of the at least one signal. Furthermore, the configuration information for the RIS reflective pattern information may include information about a timing offset and information about a starting symbol and symbol length corresponding to each of the at least one reflective pattern.

[0222] In operation S1350, the RIS controller may control a reflective pattern of the RIS based on the RIS reflective pattern information and configuration information for the RIS reflective pattern information.

[0223] In an embodiment, when the configuration information for the RIS reflective pattern information includes information about a slot offset, the RIS controller may control a reflective pattern of the RIS for each symbol based on the RIS reflective pattern information from after the lapse of the slot offset from a reception time of the RIS control signal.

[0224] In an embodiment, when the RIS reflective pattern information includes information about a reflective pattern corresponding to each symbol in the slot, the RIS controller may control a reflective pattern of the RIS for each symbol based on the reflective pattern corresponding to each symbol.

[0225] In an embodiment, when the RIS reflective pattern information includes information about the number of reflective patterns corresponding to the slot and information about a set of reflective patterns sequentially corresponding to symbols in the slot, and the configuration information for the RIS reflective pattern information includes information about a starting symbol corresponding to each reflective pattern in the reflective pattern set, the RIS controller may control a reflective pattern of the RIS for each symbol based on the information about the number of reflective patterns corresponding to the slot, the information about the set of reflective patterns sequentially corresponding to symbols in the slot, and the information about the starting symbol corresponding to each reflective pattern in the reflective pattern set.

[0226] In an embodiment, when the RIS reflective pattern information includes information about the number of reflective patterns corresponding to the slot and information about a set of reflective patterns sequentially corresponding to symbols in the slot, and the configuration information for the RIS reflective pattern information includes information about symbol length corresponding to each reflective pattern in the reflective pattern set, the RIS controller may control a reflective pattern of the RIS for each symbol based on the information about the number of reflective patterns corresponding to the slot, the information about the set of reflective patterns sequentially corresponding to symbols in the slot, and the information about the symbol length corresponding to each reflective pattern in the reflective pattern set.

[0227] In an embodiment, when the RIS reflective pattern information includes information about at least one signal transmitted in each period, and the configuration information for the RIS reflective pattern includes information about the period, the RIS controller may control a reflective pattern of the RIS based on the information about the at least one signal in each period.

[0228] In an embodiment, when the information about the at least one signal transmitted in each period includes information about at least one reflective pattern corresponding to each of the at least one signal, and the configuration information for the RIS reflective pattern information includes information about an SFN and a subframe number and information about a starting symbol and symbol length corresponding to each of the at least one reflective pattern, the RIS controller may control a reflective pattern of the RIS based on the information about the at least one reflective pattern and the information about the starting symbol and the symbol length corresponding to each of the at least one reflective pattern in each period from the subframe number of the SFN.

[0229] In an embodiment, when the information about the at least one signal transmitted in each period includes information about at least one reflective pattern corresponding to each of the at least one signal, and the configuration information for the RIS reflective pattern information includes information about a timing offset and information about a starting symbol and symbol length corresponding to each of the at least one reflective pattern, the RIS controller may control a reflective pattern of the RIS based on the information about the at least one reflective pattern and the information about the starting symbol and the symbol length corresponding to each of the at least one reflective pattern in each period from when the timing offset elapses from a reception time of the RIS control signal.

[0230] In an embodiment, when the at least one signal transmitted in each period includes a sync signal, the RIS controller may receive configuration information for the sync signal from the BS, and based on the configuration information for the sync signal, identify configuration information for a plurality of sync signals including the sync signal. Furthermore, the RIS controller may control a reflective pattern of the RIS in each period based on information about a reflective pattern corresponding to each of the at least one of the plurality of sync signals and configuration information for the at least one sync signal.

[0231] In an embodiment, the RIS controller may identify an occurrence time of each of at least one PRACH occasion corresponding to each of the at least one sync signal based on the configuration information for the sync signal. Furthermore, the RIS controller may control a reflective pattern of the RIS at a time when each PRACH occasion occurs in each period based on the information about the reflective pattern corresponding to each of the at least one sync signal.

[0232] FIG. 14 is a schematic block diagram of a configuration of a network entity, according to an embodiment of the disclosure.

[0233] Referring to the FIG. 14, a network entity 1400 may include a processor 1410, a transceiver 1420 and a memory 1430. Components of the network entity 1400 are not, however, limited thereto. For example, the network entity 1400 may include more or fewer components than described above. In addition, the processor 1410, the transceiver 1420 and the memory 1430 may be implemented in the form of a single chip.

[0234] The processor 1410 may include one or more processors. The one or more processors may include a universal processor such as a central processing unit (CPU), an application processor (AP), a digital signal processor (DSP), etc., a graphic processing unit (GPU), a vision processing unit (VPU), etc., or a dedicated artificial intelligence (AI) processor such as a neural processing unit (NPU). When the one or more processors are the dedicated AI processors, they may be designed in a hardware structure that is specific to dealing with a particular AI model.

[0235] The processor 1410 may control a series of processes for the UE to be operated according to the embodiments of the disclosure. For example, the processor 1410 may receive control signals and data signals through the transceiver 1420 and process the received control signals and data signals. The processor 1410 may transmit the processed control signal and data signal through the transceiver 1420. Furthermore, the processor 1410 may control input data derived from the received control signal and data signal to be processed according to a predefined operation rule or AI model stored in the memory 1430.

[0236] The predefined operation rule or the AI model may be made by learning. Specifically, a predefined operation rule or an AI model being made by learning refers to the predefined operation rule or the AI model established to perform a desired feature (or an object) being made when a basic AI model is trained by a learning algorithm with a lot of training data. Such learning may be performed by the UE itself in which AI is performed according to the disclosure, or by a separate server and/or system. Examples of the learning algorithm may include supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, without being limited thereto.

[0237] The AI model may include a plurality of neural network layers. Each of the plurality of neural network layers may have a plurality of weight values, and perform neural network operation through operation between an operation result of the previous layer and the plurality of weight values. The plurality of weight values owned by the plurality of neural network layers may be optimized by learning results of the AI model. For example, the plurality of weight values may be updated to reduce or minimize a loss value or a cost value obtained by the AI model during a training procedure. An artificial neural network may include, for example, a convolutional neural network (CNN), a deep neural network (DNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), or a deep Q-network, without being limited thereto.

[0238] In an embodiment, the processor 1410 may control a reflective pattern of an RIS based on RIS reflective pattern information and configuration information for the RIS reflective pattern information.

[0239] A transmitter and a receiver may be collectively referred to as the transceiver 1420, and the transceiver of the network entity 1400 may transmit or receive signals to or from the BS, the RIS or the UE. The signals transmitted or received may include control information and data. For this, the transceiver 1420 may include an RF transmitter for up-converting the frequency of a signal to be transmitted and amplifying the signal and an RF receiver for low-noise amplifying a received signal and down-converting the frequency of the received signal. It is merely an example of the transceiver 1420, and the elements of the transceiver 1420 are not limited to the RF transmitter and RF receiver. In addition, the transceiver 1420 may receive a signal on a wireless channel and output the signal to the processor 1410, and transmit a signal output from the processor 1410 on a wireless channel.

[0240] The memory 1430 may store a program and data required for operation of the network entity 1400. Furthermore, the memory 1430 may store control information or data included in a signal obtained by the network entity 1400. Furthermore, the memory 1430 may store predefined operation rules or an AI model used by the network entity 1400. The memory 1430 may include a storage medium such as a read only memory (ROM), a random access memory (RAM), a hard disk, a compact disc ROM (CD-ROM), and a digital versatile disk (DVD), or a combination of storage mediums. Alternatively, the memory 1430 may not be separately present but integrated into the processor 1400.

[0241] FIG. 15 is a schematic block diagram of a configuration of a BS, according to an embodiment of the disclosure.

[0242] Referring to FIG. 15, the BS 1500 may include a processor 1510, a transceiver 1520 and a memory 1530. The processor 1510, the transceiver 1520 and the memory 1520 of the BS 1500 may operate according to the aforementioned communication method of the BS. Components of the BS are not, however, limited thereto. For example, the BS may include more or fewer components than described above. In addition, the processor 1510, the transceiver 1520 and the memory 1530 may be implemented in the form of a single chip. The processor 1510 may include one or more processors.

[0243] The processor 1510 may control a series of processes for the BS to be operated according to the embodiments of the disclosure. For example, the processor 1510 may receive a control signal and a data signal through the transceiver 1520, and process the received control signal and data signal. The processor 1510 may transmit the processed control signal and data signal through the transceiver 1520. Furthermore, the processor 1510 may control each component of the BS to configure an RIS control signal including the RIS reflective pattern information and the configuration for the RIS reflective pattern information and transmit the RIS control signal to a network entity.

[0244] A receiver of the BS 1500 and a transmitter of the BS are collectively referred to as the transceiver 1520, which may transmit or receive signals to or from a network entity or a UE. The signals to be transmitted to or received from the network entity or the network entity may include control information and data. For this, the transceiver 1520 may include an RF transmitter for up-converting the frequency of a signal to be transmitted and amplifying the signal and an RF receiver for low-noise amplifying a received signal and down-converting the frequency of the received signal. It is merely an example of the transceiver 1510, and the elements of the transceiver 1510 are not limited to the RF transmitter and RF receiver.

[0245] In addition, the transceiver 1520 may receive a signal on a wireless channel and output the signal to the processor 1510, and transmit a signal output from the processor 1510 on a wireless channel

[0246] The memory 1530 may store a program and data required for an operation of the BS. Furthermore, the memory 1530 may store control information or data included in a signal obtained by the BS. The memory 1530 may include a storage medium such as a ROM, a RAM, a hard disk, a CD-ROM, and a DVD, or a combination of storage mediums. Alternatively, the memory 1520 may not be separately present but integrated into the processor 1530.

[0247] The machine-readable storage medium may be provided in the form of a non-transitory storage medium. The term non-transitory storage medium may mean a tangible device without including a signal, e.g., electromagnetic waves, and may not distinguish between storing data in the storage medium semi-permanently and temporarily. For example, the non-transitory storage medium may include a buffer that temporarily stores data.

[0248] In an embodiment of the disclosure, the aforementioned method according to the various embodiments of the disclosure may be provided in a computer program product. The computer program product may be a commercial product that may be traded between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., a compact disc read only memory (CD-ROM)) or distributed directly between two user devices (e.g., smart phones) or online (e.g., downloaded or uploaded). In the case of the online distribution, at least part of the computer program product (e.g., a downloadable app) may be at least temporarily stored or arbitrarily created in a storage medium that may be readable to a device such as a server of the manufacturer, a server of the application store, or a relay server.