AUDIO AMPLIFIER CIRCUIT

Abstract

A first voltage dividing circuit receives an internal power supply voltage at an input node. A buffer has an input node connected to an output node of the first voltage dividing circuit. A second voltage dividing circuit receives a power supply voltage V.sub.CC at an input node. A voltage of the output node of the first voltage dividing circuit is a first reference voltage V.sub.FIL, and a voltage of the output node of the second voltage dividing circuit is a second reference voltage V.sub.FILP. A resistor Ro is connected between an output node of the buffer and the output node of the second voltage dividing circuit. The clamp circuit controls the voltage of the output node of the first voltage dividing circuit such that the second reference voltage does not exceed a limit voltage determined to be equal to or lower than the internal power supply voltage.

Claims

1. An audio amplifier circuit comprising: an input gain circuit structured to amplify an analog audio signal, a pulse modulator including an integrator and structured to generate a pulse signal having a pulse width corresponding to an output signal of the input gain circuit, a power supply terminal structured to receive a power supply voltage, a driver structured to receive the power supply voltage and amplify the pulse signal, a bias circuit structured to supply a first reference voltage to the input gain circuit and supply a second reference voltage to the integrator; and an internal voltage source structured to generate an internal power supply voltage, wherein the bias circuit includes: a first voltage dividing circuit structured to receive the internal power supply voltage at an input node; a buffer having an input node connected to an output node of the first voltage dividing circuit, a signal of an output node being the first reference voltage, a second voltage dividing circuit structured to receive the power supply voltage at an input node, a signal of an output node being the second reference voltage, a resistor connected between the output node of the buffer and the output node of the second voltage dividing circuit; and a clamp circuit structured to control a voltage of the output node of the first voltage dividing circuit such that the second reference voltage does not exceed a limit voltage determined to be equal to or lower than the internal power supply voltage.

2. The audio amplifier circuit according to claim 1, wherein the clamp circuit is a shunt regulator.

3. The audio amplifier circuit according to claim 1, wherein the clamp circuit includes: a shunt transistor connected between the output node of the second voltage dividing circuit and a ground; and an error amplifier structured to receive a monitoring signal corresponding to the second reference voltage and a predetermined reference voltage, and have an output connected to a control terminal of the shunt transistor.

4. An audio amplifier circuit comprising: an input gain circuit structured to amplify an analog audio signal, a pulse modulator including an integrator and structured to generate a pulse signal having a pulse width corresponding to an output signal of the input gain circuit, a power supply terminal structured to receive a power supply voltage, a driver structured to receive the power supply voltage and amplify the pulse signal, a bias circuit structured to supply a first reference voltage to the input gain circuit and supply a second reference voltage to the integrator; and an internal voltage source structured to generate an internal power supply voltage, wherein the bias circuit includes: a first node structured to receive the internal power supply voltage, a second node structured to receive the power supply voltage, a third node at which the first reference voltage is generated, a fourth node at which the second reference voltage is generated, a fifth node to which a capacitor is to be connected, a first resistor connected between the first node and the fifth node, a second resistor connected between the fifth node and a ground, a buffer having an input node connected to the fifth node, a third resistor connected between the second node and the fourth node, a fourth resistor connected between the fourth node and the ground, a fifth resistor connected between an output node of the buffer and the fourth node; and a clamp circuit structured to receive a monitoring signal corresponding to the second reference voltage and sink a current corresponding to an error between a predetermined reference voltage and the monitoring signal from the third node.

5. The audio amplifier circuit according to claim 4, wherein the clamp circuit includes: a shunt transistor connected between the third node and a ground; and an error amplifier structured to receive the monitoring signal and the predetermined reference voltage, and have an output connected to a control terminal of the shunt transistor.

6. The audio amplifier circuit according to claim 4, wherein the integrator includes: an operational amplifier structured to receive the second reference voltage at a non-inverting input terminal, a capacitor connected between an inverting input node and an output node of the operational amplifier, an input resistor connected between the inverting input node of the operational amplifier and an input node of the pulse modulator; and a feedback resistor connected between the inverting input node of the operational amplifier and an output node of the driver, wherein, when a resistance value of the input resistor is Ri and a resistance value of the feedback resistor is Rf, a resistance value of the fifth resistor is Ri, and resistance values of the third resistor and the fourth resistor are 2Rf.

7. The audio amplifier circuit according to claim 1, wherein the audio amplifier circuit is integrated on one semiconductor substrate.

8. An in-vehicle electronic apparatus comprising the audio amplifier circuit according to claim 1.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Embodiments will now be described, by way of example only, with reference to the accompanying drawings which are meant to be exemplary, not limiting, and wherein like elements are numbered alike in several Figures, in which:

[0006] FIG. 1 is a circuit diagram of an in-vehicle audio system including an audio amplifier circuit according to an embodiment,

[0007] FIG. 2 is a level diagram of the in-vehicle audio system of FIG. 1,

[0008] FIG. 3 is a circuit diagram of a bias circuit of FIG. 1,

[0009] FIG. 4 is a diagram for explaining an operation of the audio amplifier circuit of FIG. 1; and

[0010] FIG. 5 is a diagram for explaining an operation of the audio amplifier circuit of FIG. 1.

DETAILED DESCRIPTION

Outline of Embodiment

[0011] An outline of some exemplary embodiments of the present disclosure will be described. This outline describes some concepts of one or more embodiments in a simplified manner for the purpose of basic understanding of the embodiments as a preface to the detailed description to be given later and does not limit the breadth of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments and is not intended to identify key elements of all the embodiments or delineate the scope of some or all of the embodiments. For convenience, one embodiment may be used to refer to one embodiment (example or modification) or a plurality of embodiments (examples or modifications) disclosed herein.

[0012] An audio amplifier circuit according to one embodiment includes: an input gain circuit that amplifies an analog audio signal; a pulse modulator that includes an integrator and generates a pulse signal having a pulse width corresponding to an output signal of the input gain circuit; a power supply terminal that receives a power supply voltage; a driver that receives the power supply voltage and amplifies the pulse signal; a bias circuit that supplies a first reference voltage to the input gain circuit and supplies a second reference voltage to the integrator; and an internal voltage source that generates an internal power supply voltage. The bias circuit includes: a first voltage dividing circuit that receives the internal power supply voltage at an input node, a buffer having an input node connected to an output node of the first voltage dividing circuit, in which a signal of an output node is a first reference voltage; a second voltage dividing circuit that receives the power supply voltage at an input node, in which a signal of an output node is the second reference voltage; a resistor connected between the output node of the buffer and the output node of the second voltage dividing circuit; and a clamp circuit that controls the voltage of the output node of the first voltage dividing circuit such that the second reference voltage does not exceed a limit voltage determined to be equal to or less than the internal power supply voltage.

[0013] In a state where the power supply voltage is lower than a certain voltage level, the first reference voltage and the second reference voltage are proportional to the power supply voltage. When the power supply voltage exceeds the certain voltage level, the clamp circuit is activated, and the second reference voltage is clamped to a predetermined limit voltage. When the clamp circuit is active, the first reference voltage decreases as the power supply voltage increases. With this configuration, it is possible to increase the center level of the amplified audio signal in conformance with the power supply voltage while protecting the circuit from overvoltage, thus making it possible to continuously reproduce the audio signal.

[0014] In one embodiment, the clamp circuit may be a shunt regulator.

[0015] In one embodiment, the clamp circuit may include: a shunt transistor connected between the output node of the second voltage dividing circuit and a ground; and an error amplifier that receives a monitoring signal corresponding to the second reference voltage and a predetermined reference voltage, and has an output connected to a control terminal of the shunt transistor.

[0016] An audio amplifier circuit according to one embodiment includes: an input gain circuit that amplifies an analog audio signal; a pulse modulator that includes an integrator and generates a pulse signal having a pulse width corresponding to an output signal of the input gain circuit; a power supply terminal that receives a power supply voltage; a driver that receives the power supply voltage and amplifies the pulse signal; a bias circuit that supplies a first reference voltage to the input gain circuit and supplies a second reference voltage to the integrator; and an internal voltage source that generates an internal power supply voltage. The bias circuit includes: a first node that receives the internal power supply voltage; a second node that receives the power supply voltage; a third node at which the first reference voltage is generated; a fourth node at which the second reference voltage is generated; a fifth node to be connected to a capacitor; a first resistor connected between the first node and the fifth node; a second resistor connected between the fifth node and a ground; a buffer having an input node connected to the fifth node; a third resistor connected between the second node and the fourth node; a fourth resistor connected between the fourth node and a ground; a fifth resistor connected between an output node of the buffer and the fourth node; and a clamp circuit that receives a monitoring signal corresponding to the second reference voltage and sinks an electric current corresponding to an error between the second reference voltage and the monitoring signal from the third node.

[0017] In a state where the power supply voltage is lower than a certain voltage level, the first reference voltage and the second reference voltage are proportional to the power supply voltage. When the power supply voltage exceeds the certain voltage level, the clamp circuit is activated, and the first reference voltage is adjusted such that the second reference voltage maintains a predetermined target level. As a result, the audio signal can be continuously reproduced while protecting the circuit from overvoltage.

[0018] In one embodiment, the clamp circuit may include: a shunt transistor connected between the third node and a ground; and an error amplifier that receives a monitoring signal corresponding to the second reference voltage and a predetermined reference voltage, and has an output connected to a control terminal of the shunt transistor.

[0019] In one embodiment, the integrator may include: an operational amplifier that receives a second reference voltage at a non-inverting input terminal, a capacitor connected between an inverting input node and an output node of the operational amplifier, an input resistor connected between the inverting input node of the operational amplifier and an input node of the pulse modulator, and a feedback resistor connected between the inverting input node of the operational amplifier and an output node of the driver. When the resistance value of the input resistor is Ri and the resistance value of the feedback resistor is Rf, the resistance value of the fifth resistor may be Ri, and the resistance values of the third resistor and the fourth resistor may be 2Rf.

[0020] In one embodiment, the audio amplifier circuit may be integrated on one semiconductor substrate. The term integrated includes a case where all components of a circuit are formed on a semiconductor substrate and a case where main components of the circuit are integrated, and some resistors, capacitors, and the like may be provided outside the semiconductor substrate to adjust a circuit constant. By integrating circuits on one chip, the circuit area can be reduced, while the characteristics of the circuit elements can be kept uniform.

Embodiment

[0021] Hereinafter, a preferred embodiment will be described with reference to the drawings. The same or equivalent components, members, and processes illustrated in the drawings are denoted by the same reference numerals, and redundant description will be omitted as appropriate. In addition, the embodiments are not intended to limit the disclosure and the invention, but are merely examples, and all features described in the embodiments and combinations thereof are not necessarily essential to the disclosure and the invention.

[0022] A state in which the member A is connected to the member B herein includes not only a case where the member A and the member B are physically and directly connected to each other, but also a case where the member A and the member B are indirectly connected to each other via another member that does not substantially affect electrical connection between the member A and the member B or that does not impair a function or an effect produced by coupling between the member A and the member B.

[0023] Similarly, a state in which the member C is connected (provided) between the member A and the member B includes not only a case where the member A and the member C or the member B and the member C are directly connected to each other, but also a case where the member C is indirectly between the member A and the member B via another member that does not substantially affect electrical connection between the member A and the member B or that does not impair a function or an effect produced by coupling between the member A and the member B.

[0024] FIG. 1 is a circuit diagram of an in-vehicle audio system 100 including an audio amplifier circuit 200 according to an embodiment. The in-vehicle audio system 100 includes an in-vehicle battery (hereinafter, simply referred to as a battery) 102, a filter 104, a speaker 106, and an audio amplifier circuit 200.

[0025] The battery 102 generates a battery voltage V.sub.BAT with a rating of 12 V. The audio amplifier circuit 200 is a functional integrated circuit (IC) in which circuits are integrated on one semiconductor substrate, and the battery voltage V.sub.BAT is supplied to the audio amplifier circuit 200 as a power supply voltage V.sub.CC. The audio amplifier circuit 200 receives an input audio signal V.sub.IN from a sound source (not illustrated), amplifies the input audio signal V.sub.IN, and drives the speaker 106 that is a load. In the present embodiment, the in-vehicle audio system 100 is configured with a fully differential amplifier, and the input audio signal V.sub.AUD is a differential signal including V.sub.AUDN and V.sub.AUDP of opposite phases.

[0026] The audio amplifier circuit 200 receives the differential signals V.sub.AUDN and V.sub.AUDP at differential input terminals INN and INP from the sound source (not illustrated) via a coupling capacitor. In addition, the speaker 106 is connected to differential output terminals OUTP and OUTN of the audio amplifier circuit 200 via a filter 104. A suffix P attached to signals or terminals represents a positive phase, and a suffix N represents a negative phase. When both components of the positive phase and the negative phase are collectively mentioned, the suffix is omitted.

[0027] The audio amplifier circuit 200 is a class D amplifier (switching amplifier) and generates a pulse drive signal having a duty cycle corresponding to the input audio signal V.sub.IN. A high frequency component of the pulse drive signal VDRV is removed by the filter 104, and an analog audio signal V.sub.OUT in the audio band is supplied to the speaker 106.

[0028] A power supply terminal VCC of the audio amplifier circuit 200 is connected to the battery 102 and receives the power supply voltage V.sub.CC. An external capacitor C1 is connected to a capacitor connection terminal FILA. Pulse drive signals V.sub.DRVP and V.sub.DRVN have an amplitude equal to that of the power supply voltage V.sub.CC.

[0029] The audio amplifier circuit 200 includes an input gain circuit 210, a pulse width modulation (PWM) circuit 220, a driver circuit 230, an internal voltage source 240, and a bias circuit 250. Each of the input gain circuit 210, the PWM circuit 220, and the driver circuit 230 has the same configuration for both the positive-phase signal and the negative-phase signal.

[0030] The internal voltage source 240 generates an internal power supply voltage V.sub.REGD.

[0031] The input gain circuit 210 operates using the internal power supply voltage V.sub.REGD supplied from the internal voltage source 240 as a power supply voltage. In addition, the input gain circuit 210 is supplied with a first reference voltage V.sub.FIL from the bias circuit 250. The first reference voltage V.sub.FIL is equal to or larger than the maximum amplitude of V.sub.AUD. In the present embodiment, the first reference voltage V.sub.FIL is a voltage times the internal power supply voltage V.sub.REGD.

[00001]$\begin{array}{cc}{V}_{\mathrm{FIL}}=V_{\mathrm{REGD}}/2& \left(1\right)\end{array}$

[0032] The internal power supply voltage V.sub.REGD can be, for example, 5.3 V, and the first reference voltage V.sub.FIL can be 2.65 V.

[0033] The input gain circuit 210 amplifies the input audio signal V.sub.AUD. Specifically, an input gain circuit 210N amplifies the negative-phase audio signal V.sub.AUDN, and an input gain circuit 210P amplifies the positive-phase audio signal V.sub.AUDP. Gains of the input gain circuits 210N and 210P are g.sub.1.

[0034] The differential audio signal V.sub.AUDN is input to the input terminal INN via the coupling capacitor. A signal V.sub.INN of the input terminal INN is:

[00002]$\begin{array}{cc}{V}_{\mathrm{INN}}=V_{\mathrm{AUDN}}+V_{\mathrm{FIL}}& \left(2\right)\end{array}$

[0035] and An output signal of the input gain circuit 210N is:

[00003]$\begin{array}{cc}{V}_N=g_1{V}_{\mathrm{AUDN}}+V_{\mathrm{FIL}}& \left(3\right)\end{array}$

[0036] Similarly, a signal V.sub.INP of the input terminal INP is:

[00004]$\begin{array}{cc}{V}_{\mathrm{INP}}=V_{\mathrm{AUDP}}+V_{\mathrm{FIL}}& \left(4\right)\end{array}$

[0037] An output signal of the input gain circuit 210P is:

[00005]$\begin{array}{cc}{V}_P=g_1{V}_{\mathrm{AUDP}}+V_{\mathrm{FIL}}& \left(5\right)\end{array}$

[0038] The PWM circuit 220 is a feedback type pulse modulator. The PWM circuit 220 includes integrators 222P and 222N, comparators 224P and 224N, and an oscillator 226. The PWM circuit 220 is supplied with a second reference voltage V.sub.FILP from the bias circuit 250.

[0039] The integrator 222P receives the output signal V.sub.N of the input gain circuit 210N in the preceding stage and the drive pulse V.sub.DRVP generated by a driver circuit 230P in the subsequent stage. The second reference voltage V.sub.FILP is input to a non-inverting input node of the integrator 222P. The integrator 222P functions as an error amplifier and amplifies an error between an integrated value (smoothed voltage) of a voltage obtained by internally dividing the two voltages V.sub.N and V.sub.DRVP by the resistors Ri and Rf and the second reference voltage V.sub.FILP.

[0040] The comparator 224P compares an output voltage V.sub.ERRP of the integrator 222P with a periodic signal of a triangular wave generated by the oscillator 226 and generates a pulse signal S.sub.PWMP. The power supply voltage of the comparator 224P is the internal power supply voltage V.sub.REGD, the high level of the pulse signal S.sub.PWMP is V.sub.REGD, and the low level of the pulse signal S.sub.PWMP is 0 V.

[0041] The driver circuit 230 includes a driver circuit 230P and a driver circuit 230N. The driver circuit 230P is supplied with the power supply voltage V.sub.CC. The driver circuit 230P receives the pulse signal S.sub.PWMP and generates the drive pulse V.sub.DRVP whose high level is the power supply voltage V.sub.CC and low level is GND (0 V). A carrier wave component of the drive pulse V.sub.DRVP is removed by the external filter 104, and the output voltage V.sub.OUTP is generated.

[0042] The integrator 222P, the comparator 224P, and the driver circuit 230P form a feedback loop. This feedback loop causes the DC (direct current) component of the output voltage V.sub.OUTP (and V.sub.DRVP) to become V.sub.FILP, and the AC (alternating current) component (audio component) to become g.sub.1(g.sub.2)V.sub.AUDN. g.sub.2 is a gain of the PWM circuit 220 and defined as g.sub.2=Rf/Ri.

[0043] The integrator 222N and the comparator 224N also operate as described above. The DC component of the output voltage V.sub.OUTN (and V.sub.DRVN) becomes V.sub.FILP, and the AC component (audio component) becomes g.sub.1(g.sub.2)V.sub.INP.

[0044] The entire configuration of the in-vehicle audio system 100 has been described above. FIG. 2 is a level diagram of the in-vehicle audio system 100 of FIG. 1. FIG. 2 illustrates the voltage V.sub.INN of the differential input terminal INN, the output signal V.sub.N of the input gain circuit 210N, the PWM signal S.sub.PWMP, the drive signal V.sub.DRVP, and the output voltage V.sub.OUTP.

[0045] The first reference voltage V.sub.FIL is of the internal power supply voltage V.sub.REGD, and the voltage V.sub.INN is a signal obtained by superimposing the audio signal V.sub.AUDN on the bias level V.sub.FIL.

[0046] The bias level of the output signal V.sub.N of the input gain circuit 210N is V.sub.FIL, and the signal amplitude (AC component) is g.sub.1 times the input signal V.sub.AUDN.

[0047] The PWM signal S.sub.PWMP is a pulse signal whose high level is the internal power supply voltage V.sub.REGD and low level is the ground voltage GND (0 V), and whose duty cycle corresponds to the voltage V.sub.N. Specifically, when V.sub.N=V.sub.FIL, the duty cycle of the PWM signal S.sub.PWMP is 50%. Since the integrator 222P is an inverting amplifier, the duty cycle of the PWM signal S.sub.PWMP is higher than 50% when V.sub.N is lower than V.sub.FIL, and the duty cycle is lower than 50% when V.sub.N is higher than V.sub.FIL.

[0048] The drive signal V.sub.DRVP is a pulse signal whose high level is the power supply voltage V.sub.CC and low level is the ground voltage GND (0 V). The duty cycle of the drive signal V.sub.DRVP is equal to the duty cycle of the PWM signal S.sub.PWMP.

[0049] The bias level of the output signal V.sub.OUTP is V.sub.CC/2, and the signal amplitude (AC component) is g.sub.1(g.sub.2) times the input signal V.sub.AUDN.

[0050] A voltage V.sub.SPK applied across the speaker 106 is V.sub.OUTPV.sub.OUTN, and the signal amplitude is twice the output signal V.sub.OUTP.

[0051] Next, a configuration of the bias circuit 250 will be described.

[0052] FIG. 3 is a circuit diagram of the bias circuit 250 of FIG. 1. The bias circuit 250 includes a first voltage dividing circuit 252, a buffer 254, a second voltage dividing circuit 256, a clamp circuit 258, and a resistor Ro.

[0053] The first voltage dividing circuit 252 receives the internal power supply voltage V.sub.REGD at an input node. The first voltage dividing circuit 252 includes resistors R11 and R12. The resistor R11 is connected between the input node of the first voltage dividing circuit 252 and the capacitor connection terminal FILA, and the resistor R12 is connected between the capacitor connection terminal FILA and a ground.

[0054] When the resistance values of the resistors R11 and R12 of the first voltage dividing circuit 252 are determined to be equal to each other (R11=R12), a voltage V.sub.FILA of the capacitor connection terminal FILA is:

[00006]$\begin{array}{cc}{V}_{\mathrm{FILA}}=V_{\mathrm{REGD}}/2& \left(6\right)\end{array}$

[0055] The buffer 254 has an input node connected to an output node of the first voltage dividing circuit 252, that is, the capacitor connection terminal FILA. A signal of an output node of the buffer 254 is the first reference voltage V.sub.FIL, which is equal to the voltage V.sub.FILA of the capacitor connection terminal FILA. Therefore, the first reference voltage V.sub.FIL in the normal state (non-overvoltage state) is:

[00007]$\begin{array}{cc}{V}_{\mathrm{FIL}}=V_{\mathrm{FILA}}=V_{\mathrm{REGD}}/2& \left(7\right)\end{array}$

[0056] The second voltage dividing circuit 256 receives the power supply voltage V.sub.CC at an input node. A voltage generated at an output node FILP of the second voltage dividing circuit 256 is the second reference voltage V.sub.FILP. The second voltage dividing circuit 256 includes resistors R21 and R22. The resistor R21 is connected between the input node and the output node of the second voltage dividing circuit 256, and the resistor R22 is connected between the output node of the second voltage dividing circuit 256 and a ground.

[0057] The resistor Ro is connected between the output node of the buffer 254 and the output node of the second voltage dividing circuit 256. The ratio of the resistance values between the resistors Ro, R21, and R22 can be Ri:2Rf:2Rf. The resistance values may be such that Ro=Ri and R21=R22=2Rf. From g.sub.2=Rf/Ri as described above, the ratio can be:

Ro:R21:R22=1:2g.sub.2:2g.sub.2

At this time, the second reference voltage V.sub.FILP is expressed by the following Formula (8) in the normal state.

[00008]$\left[\mathrm{Formula}1\right]$$\begin{array}{cc}{V}_{\mathrm{FILP}}=\frac{V_{\mathrm{CC}}}{2}+\left(\frac{V_{\mathrm{CC}}}{2}-\frac{V_{\mathrm{FIL}}}{2}\right).Math.\frac{\mathrm{Ri}}{\mathrm{Ri}+\mathrm{Rf}}& \left(8\right)\end{array}$

[0058] The clamp circuit 258 controls the voltage of the output node of the first voltage dividing circuit 252 such that the second reference voltage V.sub.FILP does not exceed a limit voltage V.sub.LIM determined to be equal to or lower than the internal power supply voltage V.sub.REGD. For example, when V.sub.REGD=5.3 V, the limit voltage V.sub.LIM can be 5 V. That is, the clamp circuit 258 is inactive when V.sub.CC<2V.sub.LIM, and is activated when V.sub.CC>2V.sub.LIM.

[0059] The resistor R22 includes resistors R22a and R22b connected in series. A voltage V.sub.MON obtained by dividing the second reference voltage V.sub.FILP is generated at a connection node between the resistors R22a and R22b. The clamp circuit 258 monitors the divided voltage (referred to as a monitoring voltage) V.sub.MON and sinks a sink current I.sub.ADJ from the capacitor connection terminal FILA such that the monitoring voltage V.sub.MON does not exceed a reference voltage V.sub.BGR.

[0060] The clamp circuit 258 is a shunt regulator, and includes a bandgap reference circuit 260, an operational amplifier OA31, resistors R31 and R32, and a shunt transistor Q31.

[0061] The bandgap reference circuit 260 generates the reference voltage V.sub.BGR of 1.2 V. The shunt transistor Q31 is connected to the output node of the second voltage dividing circuit 256, that is, between the capacitor connection terminal FILA and a ground. The operational amplifier OA31 is an error amplifier and receives the monitoring signal V.sub.MON corresponding to the second reference voltage V.sub.FILP and the reference voltage V.sub.BGR. An output of the operational amplifier OA31 is divided by the resistors R31 and R32 and supplied to a control terminal (base) of the shunt transistor Q31.

[0062] In the state of V.sub.CC>2V.sub.LIM, that is, in the state of V.sub.MON>V.sub.BGR, the current amount of the sink current I.sub.ADJ is adjusted by the clamp circuit 258 through a feedback, the voltage of the capacitor connection terminal FILA drops, and as a result, the monitoring voltage V.sub.MON becomes equal to the reference voltage V.sub.BGR.

[0063] In the state of V.sub.CC<2V.sub.LIM, that is, in the state of V.sub.MON<V.sub.BGR, the shunt transistor Q31 is turned off and the sink current I.sub.ADJ is 0, and as a result, the voltage of the capacitor connection terminal FILA is not affected. At this time, the second reference voltage V.sub.FILP is expressed by the following Formula (8).

[0064] The configuration of the bias circuit 250 has been described above. Next, an operation of the in-vehicle audio system 100 of FIG. 1 will be described.

[0065] FIG. 4 is a diagram for explaining an operation of the audio amplifier circuit 200 of FIG. 1. The horizontal axis represents the power supply voltage V.sub.CC, and the vertical axis represents various voltages. The gain g.sub.2 of the PWM circuit 220 is 9 dB.

[0066] Specifically, the voltage V.sub.FILA (first reference voltage V.sub.FIL) of the capacitor connection terminal FILA, the second reference voltage V.sub.FILP, and the monitoring voltage V.sub.MON are illustrated. For comparison, various voltages when the clamp circuit 258 is operated (w/clamp) are indicated by solid lines, and various voltages when the clamp circuit 258 is not operated (w/o clamp) are indicated by broken lines.

[0067] The battery voltage V.sub.BAT may be approximately 9 to 14.4 V for a 12 V battery and 18 to 30 V for a 24 V battery. The audio amplifier circuit 200 is designed assuming the 12 V battery 102, and is designed with a maximum operating voltage of 18 V considering a margin from 14.4 V. In addition, even in a case where the 24 V battery is mistakenly connected, the audio amplifier circuit 200 is required to maintain audio reproduction of 1 W, and therefore, the audio amplifier circuit 200 is designed to have an overvoltage protection voltage of V.sub.CC=30 V.

[0068] In a case where the clamp circuit 258 is not operated, when the power supply voltage V.sub.CC becomes an overvoltage, the voltage V.sub.FILP increases linearly with respect to the power supply voltage V.sub.CC. On the other hand, the clamp circuit 258 can be operated to, even if the power supply voltage V.sub.CC becomes an overvoltage, maintain the voltage V.sub.FILP at a voltage level allowing the audio signal to be amplified without being clipped.

[0069] FIG. 5 is a diagram for explaining an operation of the audio amplifier circuit 200 of FIG. 1. In FIG. 5, the gain g.sub.2 of the PWM circuit 220 is 14 dB.

[0070] The operation of the audio amplifier circuit 200 has been described above.

[0071] The audio amplifier circuit 200 operates such that the second reference voltage V.sub.FILP does not exceed a limit voltage V.sub.LIM determined to be equal to or lower than the internal power supply voltage V.sub.REGD. This makes it possible to enhance resistance to an overvoltage while suppressing an increase in the circuit area due to the adoption of a high withstand voltage element such as a double-diffused MOS (DMOS).

[0072] The advantage of the audio amplifier circuit 200 is made clear by a comparison with the comparative technique. In the comparative technique, when the power supply voltage V.sub.CC becomes an overvoltage, only the second reference voltage V.sub.FILP is clamped without reducing the first reference voltage V.sub.FIL (V.sub.FILA). In this case, the bias voltage (midpoint voltage) of the drive voltage V.sub.DRVP (V.sub.DRVN) deviates from V.sub.CC/2.

[0073] On the other hand, in the audio amplifier circuit 200 according to the embodiment, when the power supply voltage V.sub.CC becomes an overvoltage, the first reference voltage V.sub.FIL (V.sub.FILA) drops as the power supply voltage V.sub.CC increases. As a result, the bias voltage (midpoint voltage) of the drive voltage V.sub.DRVP (V.sub.DRVN) can be maintained at V.sub.CC/2.

[0074] According to the present embodiment, even in a case where the optimum gain is set in the operation guarantee power supply voltage range, an output equivalent to 1 W is possible when the 24 V battery is mistakenly connected. Conversely, since it is not necessary to set the gain g.sub.2 of the PWM circuit 220 high on the assumption of overvoltage operation, it is possible to realize operation in an overvoltage state without deteriorating characteristics of noise and offset voltage.

Supplement

[0075] The techniques disclosed herein are as follows:

Item 1

[0076] An audio amplifier circuit [0077] including: [0078] an input gain circuit that amplifies an analog audio signal, [0079] a pulse modulator that includes an integrator and generates a pulse signal having a pulse width corresponding to an output signal of the input gain circuit, [0080] a power supply terminal that receives a power supply voltage, [0081] a driver that receives the power supply voltage and amplifies the pulse signal, [0082] a bias circuit that supplies a first reference voltage to the input gain circuit and supplies a second reference voltage to the integrator; and [0083] an internal voltage source that generates an internal power supply voltage, [0084] wherein [0085] the bias circuit includes: [0086] a first voltage dividing circuit that receives the internal power supply voltage at an input node; [0087] a buffer having an input node connected to an output node of the first voltage dividing circuit, a signal of an output node being the first reference voltage, [0088] a second voltage dividing circuit that receives the power supply voltage at an input node, a signal of an output node being the second reference voltage, [0089] a resistor connected between the output node of the buffer and the output node of the second voltage dividing circuit; and [0090] a clamp circuit that controls a voltage of the output node of the first voltage dividing circuit such that the second reference voltage does not exceed a limit voltage determined to be equal to or lower than the internal power supply voltage.

Item 2

[0091] The audio amplifier circuit according to item 1, wherein the clamp circuit is a shunt regulator.

Item 3

[0092] The audio amplifier circuit according to item 1 or 2, wherein [0093] the clamp circuit may include: [0094] a shunt transistor connected between the output node of the second voltage dividing circuit and a ground; and [0095] an error amplifier that receives a monitoring signal corresponding to the second reference voltage and a predetermined reference voltage, and has an output connected to a control terminal of the shunt transistor.

Item 4

[0096] An audio amplifier circuit [0097] including: [0098] an input gain circuit that amplifies an analog audio signal, [0099] a pulse modulator that includes an integrator and generates a pulse signal having a pulse width corresponding to an output signal of the input gain circuit, [0100] a power supply terminal that receives a power supply voltage, [0101] a driver that receives the power supply voltage and amplifies the pulse signal, [0102] a bias circuit that supplies a first reference voltage to the input gain circuit and supplies a second reference voltage to the integrator; and [0103] an internal voltage source that generates an internal power supply voltage, [0104] wherein [0105] the bias circuit includes: [0106] a first node that receives the internal power supply voltage, [0107] a second node that receives the power supply voltage, [0108] a third node at which the first reference voltage is generated, [0109] a fourth node at which the second reference voltage is generated, [0110] a fifth node to which a capacitor is to be connected, [0111] a first resistor connected between the first node and the fifth node, [0112] a second resistor connected between the fifth node and a ground, [0113] a buffer having an input node connected to the fifth node, [0114] a third resistor connected between the second node and the fourth node, [0115] a fourth resistor connected between the fourth node and the ground, [0116] a fifth resistor connected between an output node of the buffer and the fourth node, and [0117] a clamp circuit that receives a monitoring signal corresponding to the second reference voltage and sinks a current corresponding to an error between a predetermined reference voltage and the monitoring signal from the third node.

Item 5

[0118] The audio amplifier circuit according to item 4, wherein [0119] the clamp circuit includes: [0120] a shunt transistor connected between the third node and a ground; and [0121] an error amplifier that receives the monitoring signal and the predetermined reference voltage, and has an output connected to a control terminal of the shunt transistor.

Item 6

[0122] The audio amplifier circuit according to item 4 or 5, wherein [0123] the integrator includes: [0124] an operational amplifier that receives the second reference voltage at a non-inverting input terminal; [0125] a capacitor connected between an inverting input node and an output node of the operational amplifier; [0126] an input resistor connected between the inverting input node of the operational amplifier and an input node of the pulse modulator; and [0127] a feedback resistor connected between the inverting input node of the operational amplifier and an output node of the driver, [0128] wherein, when a resistance value of the input resistor is Ri and a resistance value of the feedback resistor is Rf, a resistance value of the fifth resistor is Ri, and resistance values of the third resistor and the fourth resistor are 2Rf.

Item 7

[0129] The audio amplifier circuit according to any one of items 1 to 6, wherein the audio amplifier circuit is integrated on one semiconductor substrate.

Item 8

[0130] An in-vehicle electronic apparatus including the audio amplifier circuit according to any one of items 1 to 7.