DATA PROCESSING NETWORK FOR DATA PROCESSING

Abstract

A data processing network for performing successive data processing steps in a redundant and validated manner. Each step is used to generate output data from input data. Output data from a first data processing step are at least partially simultaneously input data of a further data processing step. At least one first data processing module is provided for performing each data processing step. The data processing network also includes a comparator module. The first data processing modules transmit control parameters of the individual data processing steps to the comparator module. The comparator module is provides a synchronized control parameter which contains control information relating to at least one performed data processing step. The data processing network includes a recording module in which a debug mode can be activated with which debug data containing information on each execution of a data processing step with the data processing network are recorded.

Claims

1-16. (canceled)

17. A data processing network configured to perform a multiplicity of successive data processing steps in a redundant and validated manner, each of the steps being used to generate output data from input data, wherein output data from a first data processing step are at least partially simultaneously input data of a further data processing step, the data processing network comprising: at least one first data processing module provided for performing each data processing step; a comparator module, wherein the first data processing modules are configured to transmit control parameters of individual data processing steps to the comparator module, and the comparator module is configured to provide a synchronized control parameter which contains control information relating to at least one performed data processing step; and a recording module in which a debug mode can be activated with which debug data containing information on each execution of a data processing step with the data processing network are recorded.

18. The data processing network according to claim 17, wherein, at least for one of the first data processing modules, a second data processing module exists which is configured to execute the same data processing step as the first data processing module and to transmit a control parameter to the comparator module, wherein the synchronized control parameter is generated by at least one comparison of corresponding control parameters transmitted by the first data processing modules and the second data processing modules.

19. The data processing network according to claim 18, wherein the recording module is connected to the comparator module and is configured to record control parameters that occur in the comparator module.

20. The data processing network according to claim 18, wherein the recording module is configured to record a state of the at least one first data processing module and/or the at least one second data processing module when the debug mode is activated.

21. The data processing network according to claim 17, wherein the recording module is configured to record initial input data of each data processing step of the data processing network when the debug mode is activated.

22. The data processing network according to claim 17, wherein the recording module is configured such that input data of each data processing step are permanently recorded while the debug mode is activated.

23. The data processing network according to claim 17, wherein priority parameters are assigned to the data processing steps and information on each execution of a data processing step is recorded according to the priority parameters.

24. The data processing network according to claim 17, wherein a slowdown mode can be activated in debug mode, which can be used to ensure that information on each execution of a data processing step is recorded completely.

25. The data processing network according to claim 18, wherein first data processing modules are realized with first hardware components and the second data processing modules are realized with second hardware components, wherein the first hardware components and the second hardware components are physically separated from one another.

26. The data processing network according to claim 25, wherein at least one of the first data processing modules includes a hardware component that is not ASIL-D-compliant.

27. The data processing network according to claim 25, wherein the comparator module is realized with third hardware components which are physically separated from the first hardware components and the second hardware components.

28. The data processing network according to claim 27, wherein the third hardware component is ASIL-D-compliant.

29. The data processing network according to claim 18, wherein the comparator module has a data memory in which ascertained control parameters are stored with time information so that a logical timeline is created which represents an order of the processing of the data processing steps with the first and second data processing modules of the data processing network, wherein the recording module is configured in debug mode to record the logical timeline with a flowchart of the data processing steps performed.

30. A debugging system for checking data processing with a data processing network configured to perform a multiplicity of successive data processing steps in a redundant and validated manner, each of the steps being used to generate output data from input data, wherein output data from a first data processing step are at least partially simultaneously input data of a further data processing step, the data processing network including: at least one first data processing module provided for performing each data processing step; a comparator module, wherein the first data processing modules are configured to transmit control parameters of individual data processing steps to the comparator module, and the comparator module is configured to provide a synchronized control parameter which contains control information relating to at least one performed data processing step; and a recording module in which a debug mode can be activated with which debug data containing information on each execution of a data processing step with the data processing network are recorded; wherein the debussing system comprises: debugging data processing modules for performing the data processing steps which are also executed correspondingly in the data processing network; an import module configured to import debug data recorded with the recording module of the data processing network; and an arrangement for starting the data processing with the debugging system.

31. The debugging system according to claim 30, wherein, at least for one of the first data processing modules, a second data processing module exists which is configured to execute the same data processing step as the first data processing module and to transmit a control parameter to the comparator module, wherein the synchronized control parameter is generated by at least one comparison of corresponding control parameters transmitted by the first data processing modules and the second data processing modules, and wherein initial input data and a state of the at least one first data processing module and/or the at least one second data processing module are imported into the debugging data processing modules when the data processing with the debugging system is started.

32. The debugging system according to claim 30, wherein, during the data processing with the debugging system, a debug comparison takes place between synthetic input data generated by the data processing with the debugging system and input data permanently recorded by the recording module in debug mode.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0095] FIG. 1 shows a described data processing network, according to an example embodiment of the present invention.

[0096] FIG. 2 shows processing of the individual data processing steps on a logical timeline, according to an example embodiment of the present invention.

[0097] FIG. 3 shows the processing of a single data processing step with the various data processing modules, according to an example embodiment of the present invention.

[0098] FIG. 4 is a flowchart of the described method performed with the data processing network, according to an example embodiment of the present invention.

[0099] FIG. 5 shows a described debugging system, according to an example embodiment of the present invention.

DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS

[0100] FIG. 1 shows a described data processing network 1 in a motor vehicle 23. By way of example, it is shown here that the data processing network 1 is used to process data from sensors 19 and an output data receiver 20 is supplied with data by the system. Such an output data receiver 20 can, for example, be a system for an autonomous driving operation or a similar system. The data processing network 1 is used, for example, to reduce the sensor data to decision-relevant parameters, which can be output data 4 of the data processing network 1.

[0101] The data processing network 1 here also includes hardware components on which the data processing network 1, or its components and modules, can be operated.

[0102] The data processing network 1 performs individual data processing steps 2 that build on one another. Output data 4 of one data processing step 2 can be input data 3 of a further data processing step 2. Each data processing step 2 is realized here with a plurality of data processing modules 5, 6 that are executed as independently as possible of one another. A first data processing module 5 and a second data processing module 6 are shown here in each case. More than two data processing modules can also be provided, which perform a data processing step 2 (in parallel).

[0103] The data processing network 1 comprises further components, which are explained in detail below with reference to the other figures. In particular, this includes the comparator module 7 and possibly also a synchronizer 27, which are only indicated schematically here.

[0104] FIG. 1 also shows a recording module 29 which is connected to each of the data processing modules 5, 6 and receives and records debug data 30 of each of the individual data processing steps. The recording module 29 in particular receives, as debug data 30, state data of the data processing module 30 and input data 3, and in particular also control parameters relating to the execution of the individual data processing steps 2.

[0105] FIG. 2 shows a different representation of the described data processing network 1. FIG. 2 shows three arrows one below the other, which define the individual hardware components and at the same time also depict the individual method steps a), b) and c) of the described method. The arrows also provide a representation of the processes on the respective hardware components on a logical timeline 17. The upper arrow is a first hardware component 12 on which first data processing modules 5 are implemented. The lower arrow is a second hardware component 13 on which second data processing modules 6 are implemented. The middle arrow is a third hardware component 14 on which the comparator module 7 is realized. Data processing steps 2 of the data processing network 1 are executed in first data processing modules 5 and second data processing modules 6 in each case. Whenever a data processing step 2 is completed, a control parameter 8 is transmitted to the comparator module 7, which then recognizes, by comparing the control parameters 8, whether the data processing step 2 has been executed correctly (i.e., without errors). The comparator module 7 then generates synchronized control parameters 9 which are used to trigger further data processing steps 2, which then further process output data (not shown here) from previous data processing steps 2. The comparator module 8 and the associated components can also be understood as a central unit 24 of the described data processing network 1. The synchronized control parameters 9 can be understood as stimuli 25 for triggering further data processing steps 2.

[0106] Also shown schematically in FIG. 2 is the recording module 29, which records debug data 30 that it receives from the first data processing module 5, the second data processing module 6, and the comparator module 7.

[0107] FIG. 3 shows the parallel processing of a data processing step 2 by a first data processing module 5 and by a second data processing module 6 in even greater detail. It can be seen that the first data processing module 5 is realized on a first hardware component 12, while the second data processing module 6 is realized on a second hardware component 13. The first data processing module 5 and the second data processing module 6 each process the same input data 3 and should also each generate the same output data 4.

[0108] A data processing step 2 or a data processing module 5, 6 can be further subdivided into a multiplicity of individual data processing components 18, each of which relates to substeps of the data processing. The data processing step 2, or the data processing module 5, 6 as defined here, therefore already relates to pre-groupings, which are sensibly selected or defined depending on the application, of substeps which are executed with the data processing components 18. The pre-grouping of substeps is preferably selected such that no data storage is required within a data processing step 2 or a data processing module 5, 6 and that, in particular, no data other than the input data are accessed for the execution.

[0109] The first data processing module 5 and the second data processing module 6 respectively generate control parameters 8 which are evaluated by the comparator module 7. The comparator module 7 is realized on a third hardware component 14, which is independent of the first hardware component 12 and the second hardware component 13, forms a central unit 24 and preferably offers the above-described higher safety (higher ASIL level) of the execution. In preferred design variants, a sequentialization module 11 for obtaining the control parameters 8 from the data processing is in each case upstream of each data processing module 5, 6 and a synchronizer 27 is upstream of the comparator module 7. Additionally, a task distribution module 22, which outputs synchronized control parameters 9 or stimuli 25 for triggering further data processing steps 2, can be downstream of the comparator module 7. The synchronizer 27, comparator module 7, and task distribution module 22 can be realized together as the described central unit 24 on the third hardware component 14. Preferably, the described data processing network 1 is operated such that data processing steps 2 are executed on the available and not fully utilized hardware. The task distribution module 22 can initiate this distribution of the data processing steps 2 to the available hardware. In addition, the execution of the data processing steps 2 performed takes a different amount of time on each hardware. The synchronizer 27 sorts the incoming control parameters 8 so that, even if the hardware is under high load, the comparator module 7 compares the correct control parameters 8 with one another in order to generate correct synchronized control parameters 9. For this purpose, the control parameters 8 are transferred as control parameter tuples 28 from the synchronizer 27 to the comparator module 7. It is not necessary for input data 3 and output data 4 respectively to be transferred via the central unit 24 or the comparator module 7 from one data processing step 2 to the next data processing step 2. For this purpose, additional data transmission interfaces 26 may also exist between the data processing modules 5, 6 or the respective hardware components 12, 13, which interfaces exist independently of the comparator module 7. Data provided via these data transmission interfaces 26 are preferably accessed if it is determined with the comparator module 7 that the particular data processing step 2, generating the output data 4, has been processed without errors in both data processing modules 5, 6.

[0110] FIG. 4 shows yet another representation of the described method, in which method steps a), b) and c) are respectively performed for each data processing step 2. The actual data processing steps 2 are always executed redundantly with the first data processing module 5 and with the second data processing module 6. In each case, the comparator module 7 subsequently checks whether the data processing step 2 has been executed correctly before the next data processing step 2 is started.

[0111] FIG. 5 shows the debugging system 33. The recording module 29 is also shown here (although it does not belong to the debugging system 33 but to the data processing network 1). Debug data 30 are imported into the debugging system 33 via the import module 35. Debugging data processing modules 34 are provided in the debugging system. The debugging data processing modules 34 are configured to execute the same data processing steps 2 that have also been executed in the data processing network. For this purpose, the import module 35 feeds the states 31 and the input data 3 into each debugging data processing module 34 for the data processing steps 2. Performing the data processing steps 2 with the debugging system produces synthetic input data 36 of further data processing steps 2, which can then also be supplied for evaluation with the debug comparison 37.