Optoelectronic synaptic memristor

Abstract

An optoelectronic synaptic memristor includes: a bottom electrode layer, a porous structure layer modified with quantum dots, a two-dimensional material layer, a transparent top electrode layer, and a waveguide layer, which are arranged in sequence from top to bottom, wherein the waveguide is ridge shaped for light conduction, comprising a wedge-shaped output terminal, wherein: through the wedge-shaped output terminal of the waveguide, light is vertically injected into the two-dimensional material layer and the porous structure layer modified with the quantum dots. By integrating the waveguide and the optoelectronic memristor, the present invention obtains the highly controlled characteristics with high alignment and confinement for light effect on the device and has advantages in realizing optoelectronic synergy in the optoelectronic synaptic memristors. The present invention has strong controllability and excellent performance and can be widely used in high-density integration of storage and computing, artificial synapses, artificial intelligence, etc.

Claims

1. An optoelectronic synaptic memristor, comprising: a bottom electrode layer, a porous structure layer modified with quantum dots, a two-dimensional material layer, a transparent top electrode layer, and a waveguide layer, which are arranged in sequence from top to bottom, wherein: a bottom of the two-dimensional material layer is attached on the porous structure layer modified with the quantum dots; and a top of the two-dimensional material layer is connected to the transparent top electrode layer; the waveguide layer is a ridge waveguide for light conduction, comprising a wedge-shaped output terminal, wherein: through the wedge-shaped output end of the waveguide layer, light is vertically injected into the two-dimensional material layer and the porous structure layer modified with the quantum dots; wherein the wedge-shaped output terminal has four inclined walls, wherein an inclination angle of each wall is 30-60.

2. The optoelectronic synaptic memristor, as recited in claim 1, further comprising: an oxide isolation layer which is arranged between the two-dimensional material layer and the waveguide layer, wherein: a refractive index of the oxide isolation layer is less than a refractive index of the waveguide layer; a hole, whose shape is consistent with the transparent top electrode layer, is provided on the oxide isolation layer, for placing the transparent top electrode layer.

3. The optoelectronic synaptic memristor, as recited in claim 1, wherein the porous structure layer modified with the quantum dots serves as an up-conversion light emitter and a light channel, wherein: the quantum dots serve as an up-conversion center and are attached in the porous structure layer; the porous structure layer is a vertical porous array for remitting incident light of the transparent top electrode layer into the two-dimensional material layer after up-conversion.

4. The optoelectronic synaptic memristor, as recited in claim 3, wherein the quantum dots are made of a material having an up-conversion function, wherein the material is one of cadmium telluride (CdTe), cadmium selenide (CdSe), indium phosphide (InP), zine sulfide (ZnS), cadmium sulfide (CdS), graphene, graphene oxide, reduced graphene oxide, and NaYF.sup.4.

5. The optoelectronic synaptic memristor, as recited in claim 3, wherein the porous structure layer is a porous array that is vertically arranged and made of silicon oxide (SiO.sub.2), silicon (Si), aluminum oxide (Al.sub.2O.sub.3), copper oxide (CuO), nickel oxide (NiO), titanium dioxide (TiO.sub.2), or tungsten trioxide (WO.sub.3).

6. A method for realizing an optoelectronic memristive effect with an optoelectronic synaptic memristor, comprising steps of: a writing process: grounding a bottom electrode layer; injecting a weak infrared light which is sensitive to quantum dots but insensitive to a two-dimensional material through a ridge waveguide; converting the weak infrared light by the quantum dots to obtain a short-wavelength light to the two-dimensional material; applying a continuous forward voltage to a top electrode layer; wherein due to vacancy defect migration in the two-dimensional material, a conductive filament is formed; meanwhile, due to an optoelectronic effect of the short-wavelength light, a device resistance state is set to a low resistance state through optoelectronic synergy; an erasing process: injecting a strong infrared light which is sensitive to the quantum dots but insensitive to the two-dimensional material through the ridge waveguide, and applying a continuous reverse voltage to the top electrode layer; wherein under an electric field, the conductive filament is broken due to the vacancy defects migrate inversely in the two-dimensional material; meanwhile, a strong photothermal effect of the strong infrared light exceeds an up-conversion optoelectronic effect, which inhibits a photocurrent and sets the device resistance state to a high resistance state; and controlling quantities, pulse widths, periods, and amplitudes of electrical pulses to regulate multi-values among the low resistance state and the high resistance state, thereby obtaining multiple storage states and simulating corresponding synaptic functions.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a structural sketch view of an optoelectronic synaptic memristor array according to a preferred embodiment of the present invention;

(2) FIG. 2 is a structural sketch view of an optoelectronic synaptic memristor according to the preferred embodiment of the present invention;

(3) FIG. 3 is a scanning electron microscope (SEM) image of a porous silicon oxide structure according to the preferred embodiment of the present invention;

(4) FIG. 4 is an SEM image of a two-dimensional MoS.sub.2/Mo.sub.2-xO.sub.x material on a Si substrate according to the preferred embodiment of the present invention;

(5) FIG. 5 is a simulated diagram of light field propagation in a waveguide with COMSOL software package according to the preferred embodiment of the present invention; and

(6) FIG. 6 is a mechanical diagram of the optoelectronic synaptic memristor according to the preferred embodiment of the present invention.

(7) Element references: 101: ridge waveguide layer; 102: oxide isolation layer; 103: wedge-shaped output terminal; 104: grating coupler; 201: transparent top electrode layer; 202: top electrode input end; 301: two-dimensional material layer; 401: porous structure layer modified with quantum dots; and 501: bottom electrode layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(8) The present invention is further illustrated in detail with the accompanying drawings and the preferred embodiments. The preferred embodiments help to understand the present invention, and the specific structural details and functional details are only for describing the preferred embodiments, not for limiting. Therefore, the present invention can be implemented in various ways, and the present invention is not limited to the preferred embodiments, but encompassing all of the modifications, equivalents, and replacements within the scope of the present invention.

Preferred Embodiment 1

(9) According to the preferred embodiment 1 of the present invention, as shown in FIG. 2, an optoelectronic synaptic memristor is provided, comprising a silicon nitride waveguide layer (Si.sub.3N.sub.4) 101 with a wedge-shaped output terminal 103, an oxide isolation layer (SiO.sub.2) 102, a transparent top electrode layer (ITO) 201, a two-dimensional material layer made of molybdenum disulfide and molybdenum oxide (MoS.sub.2/Mo.sub.2-xO.sub.x) 301, a porous silicon oxide structure layer modified with graphene quantum dots (GQDs@PSiO.sub.x) 401, and a bottom electrode layer (Si) 501, which are arranged in sequence from top to bottom.

(10) The waveguide layer (without the wedge-shaped output terminal) has a width of 5 m and a height of 10 m; an inclination angle of each side of the wedge-shaped output end is 45, and a contact surface of the wedge-shaped output end with the transparent top electrode layer is 10*10 m.sup.2; the transparent top electrode layer has a thickness of 200 nm; the two-dimensional MoS.sub.2/Mo.sub.2-xO.sub.x layer, has a thickness of 10 nm; the porous structure layer has a thickness of 100 nm; and the bottom electrode layer has a thickness of 300 m.

(11) The optoelectronic synaptic memristor is prepared on a substrate layer by layer from bottom to top through electrochemical corrosion, ultrasonic dispersion, chemical vapor deposition, transferring, magnetron sputtering, lithography, and plasma vapor deposition. The specific preparation process comprises steps of: (1) selecting highly-doped n-type (100) Si as the bottom electrode layer 501, and obtaining a porous silicon oxide structure layer through electrochemical corrosion, as shown in FIG. 3; (2) placing the as-prepared porous silicon oxide structure layer into a graphene quantum dot dispersion solution, and obtaining the porous silicon oxide structure layer modified with the graphene quantum dots, namely a GQDs@PSiO.sub.x structure, through ultrasonic dispersion for 30 min; (3) growing multi-layers nanosheet on a Si (100) substrate through chemical vapor deposition, and obtaining the two-dimensional MoS.sub.2/Mo.sub.2-xO.sub.x layer through oxidizing under an oxygen atmosphere with a vacuum tube furnace, as shown in FIG. 4; (4) transferring the two-dimensional MoS.sub.2/Mo.sub.2-xO.sub.x layer onto the GQDs@PSiO.sub.x structure; (5) obtaining the transparent ITO top electrode layer through lithography and magnetron sputtering; (6) simulating and optimizing the performance of the waveguide structure with COMSOL software package, as shown in FIG. 5, and obtaining a suitable waveguide size, so that an infrared light of 980 nm can be vertically injected into an optoelectronic memristor structure; and (7) integrating the waveguide structure, namely the waveguide layer Si.sub.3N.sub.4/SiO.sub.2, with the optoelectronic memristor structure through lithography and plasma vapor deposition, and obtaining the optoelectronic synaptic memristor.

(12) According to the preferred embodiment 1 of the present invention, through integrating the optical waveguide structure and the optoelectronic memristor structure, the optoelectronic synaptic memristor is obtained. As shown in FIG. 6, a writing process comprises steps of: injecting a 980 nm light by the device through the waveguide 101; then inwardly transmitting the light, in a direction perpendicular to the device, through the wedge-shaped output terminal 103, wherein the light passes through the transparent top electrode and the two-dimensional material layer to reach the up-conversion graphene quantum dots, and is converted into a blue-violet light about 400 nm before being transmitted to the MoS.sub.2/Mo.sub.2-xO.sub.x structure layer through the porous structure; at this time, an optoelectronic effect is far greater than a photothermal effect; and under stimulation of electric pulses, the device obtains a relatively fast and stable opening speed and current, and is set to a low resistance state.

(13) An erasing process comprises steps of: injecting a strong 980 nm infrared light by the device through a waveguide, namely the waveguide layer 101; then inwardly transmitting the light, in the direction perpendicular to the device, through the wedge-shaped output terminal 103, wherein the light passes through the transparent top electrode and the two-dimensional material layer to reach the up-conversion graphene quantum dots; at this time, the photothermal effect is enhanced, and the optoelectronic effect induced by the blue-violet light of about 400 nm is weakened, so photocurrent generation of the MoS.sub.2/Mo.sub.2-xO.sub.x structure layer is inhibited; under stimulation of the electric pulses, the device obtains a relatively fast and stable closing speed and current, and is set to a high resistance state.

(14) The device can control quantities, pulse widths, periods, and amplitudes of the electrical pulses to regulate values of the low resistance state and the high resistance state respectively, and simulating corresponding synaptic functions, such as Spike-Timing Dependent Plasticity.

(15) The device has high alignment and confinement in light control, providing obvious advantages in device energy consumption and neural function simulation.

Preferred Embodiment 2

(16) According to the preferred embodiment 2 of the present invention, as shown in FIG. 2, an optoelectronic synaptic memristor is provided, comprising a silicon waveguide layer (Si) 101 with a wedge-shaped output terminal 103, an oxide isolation layer (SiO.sub.2) 102, a transparent top electrode layer (FTO) 201, a two-dimensional material layer made of black phosphorus (BP) 301, a silicon porous structure layer modified with -NaYF.sup.4:Yb.sup.3+, Tm.sup.3+/NaYF.sup.4 quantum dots (-NaYF.sup.4:Yb.sup.3+, Tm.sup.3+/NaYF.sup.4@PSi) 401, and a bottom electrode layer (Si) 501, which are arranged in sequence from top to bottom.

(17) The waveguide has a width of 2.5 m and a height of 5 m; an inclination angle of each side of the wedge-shaped output end is 45, and a contact surface of the wedge-shaped output terminal with the transparent top electrode layer is 5*5 m.sup.2; the transparent top electrode layer has a thickness of 100 nm; the two-dimensional material layer, namely a BP layer, has a thickness of 3 nm; the porous structure layer has a thickness of 150 nm; and the bottom electrode layer has a thickness of 500 m.

(18) The optoelectronic synaptic memristor is prepared on a substrate layer by layer from bottom to top through electrochemical corrosion, ultrasonic dispersion, chemical vapor deposition, transferring, magnetron sputtering, photoetching, and plasma vapor deposition. The specific preparation process is similar to that in the preferred embodiment 1.

(19) According to the preferred embodiment 2 of the present invention, through integrating the waveguide and the optoelectronic memristor structure, the optoelectronic synaptic memristor is obtained. A writing process comprises steps of: injecting a low-power density 975 nm light by the device through the optical waveguide layer 101; then inwardly transmitting the light, in a direction perpendicular to the device, through the wedge-shaped output end 103, wherein the light passes through the transparent top electrode and the two-dimensional material to reach the up-conversion NaYF.sup.4:Yb.sup.3+, Tm.sup.3+/NaYF.sup.4 quantum dots, and is converted into an ultraviolet light around 280 nm and 365 nm before being transmitted to the BP structure layer through the porous structure; at this time, an optoelectronic effect (280 nm) is greater than a photothermal effect (365 nm); and under stimulation of electric pulses, the device obtains a relatively fast and stable opening speed and current, and is set to a low resistance state.

(20) An erasing process comprises steps of: injecting a high-power density 975 nm light by the device through an optical waveguide, in such a manner that the photothermal effect (365 nm) is enhanced; at this time, photocurrent generation is inhibited; under stimulation of the electric pulses, the device obtains a relatively fast and stable closing speed and current, and is set to a high resistance state.

(21) The device can control quantities, pulse widths, periods, and amplitudes of the electrical pulses to regulate values of the low resistance state and the high resistance state respectively, thereby obtaining multiple storage states and simulating corresponding synaptic functions, such as Spike-Timing Dependent Plasticity.

(22) The device has high alignment and confinement in light control, providing obvious advantages in device energy consumption and neural function simulation.

Preferred Embodiment 3

(23) Referring to FIG. 1, the preferred embodiment 3 provides an optoelectronic synaptic device array, comprising: N*M optoelectronic synaptic memristors (N1 and M1). Each of the optoelectronic synaptic memristors comprises: a silicon nitride waveguide layer (Si.sub.3N.sub.4) 101 with a wedge-shaped output terminal (Si.sub.3N.sub.4) 103, an oxide isolation layer (SiO.sub.2) 102, a grating coupler (Si.sub.3N.sub.4) 104, a transparent top electrode layer (ITO) 201, an external electrode (Au) 202 connected to the top electrode, a two-dimensional material layer (MoS.sub.2/Mo.sub.2-xO.sub.x) 301 located below an oxide isolation layer, which is made of molybdenum disulfide and molybdenum oxide, a porous silicon oxide structure layer modified with graphene quantum dots (GQDs@PSiO.sub.x) 401, and a bottom electrode layer (Si) 501.

(24) According to the preferred embodiment 3, the optoelectronic synaptic device array is obtained by integrating the waveguides and the optoelectronic memristors structure. All the optoelectronic synaptic memristors share one bottom electrode, but electrical signals of the optoelectronic synaptic memristors are individually controlled through independent top electrodes; each of the optoelectronic synaptic memristors has an independent waveguide system, and light of different intensities and wavelengths are input through different grating couplers; through each waveguide, the light is accurately injected into each of the optoelectronic synaptic memristors. Therefore, the functions of the optoelectronic synaptic memristors are separately regulated.

(25) Specific operation processes and mechanisms of the optoelectronic synaptic memristor array are as follows. In a writing process, the writing and erasing of a single device in the array are similar to those of an independent device.

(26) By combining the functions of multiple memristors, the array can simulate the corresponding synaptic functions to realize applications such as logic operations, matrix operations, image recognition, and neuromorphic calculations.

(27) It should be noted that, in each embodiment of the present invention, to enable readers to better understand the present invention and to make it understandable by those of ordinary skill in the art, many technical details are proposed. However, the technical solution of the present invention can be realized without these technical details, or with various changes and modifications based on the preferred embodiments.