HARMONIC CONTROL-BASED CLASS-J DISTRIBUTED POWER AMPLIFIER AND OPTIMIZATION METHOD THEREOF

Abstract

Provided are a harmonic control-based class-J distributed power amplifier and an optimization method thereof. The object of the present disclosure aims to solve the problems of low output power, low efficiency and low gain of distributed amplifiers resulting from non-uniform drive states of transistors at different positions and the like in the distributed amplifiers. The harmonic control-based distributed power amplifier includes an input artificial uniform transmission line, an output artificial non-uniform transmission line, and plural gain units. Two ports of the output artificial non-uniform transmission line are respectively connected with reactive terminals, and in each gain unit, a gate electrode of a transistor is connected with an RC parallel resonant circuit. In the present disclosure, based on load pull method and harmonic control technology, a purely reactive terminal network is added in the NDA terminal open-circuit structure.

Claims

1. An optimization method of a harmonic control-based distributed power amplifier, wherein the harmonic control-based distributed power amplifier, comprises: an input artificial uniform transmission line (1), an output artificial non-uniform transmission line (2), and plural gain units (3), wherein two ports of the output artificial non-uniform transmission line (2) are respectively connected with reactive terminals (4), and in each gain unit (3), a gate electrode of a transistor is connected with an RC parallel resonant circuit, wherein the optimization method is carried out in the following steps: at step 1, dividing a working frequency band into f.sub.1, f.sub.2 and f.sub.3, setting a fundamental frequency to f.sub.1, and obtaining an optimal fundamental wave load impedance Z.sub.10 by load pull, using Z.sub.10 as a second or third-order fixed harmonic load impedance of a frequency point within the f.sub.2 frequency band, wherein a class-J mode second-order harmonic load impedance of f.sub.1 is calculated in the following formula (1.1): $\begin{array}{cc}{Z}_{12}=\frac{0.5\left(V_{DD}-V_K\right)j}{\frac{2I_{\max }}{3}}=0-j\frac{3}{8}{R}_{{\mathrm{opt}}_B}& \left(0.1\right)\end{array}$ wherein V.sub.DD is a voltage of a power supply, V.sub.K is a knee voltage of a transistor, I.sub.max is a maximal drain current of a transistor 11 is a constant parameter, R.sub.opt.sub.B=2 (V.sub.DDV.sub.K)/I.sub.max is an optimal fundamental wave load impedance of a class-B power amplifier (PA); at step 2, setting the fundamental wave to f.sub.2, and fixing Z.sub.10 as a second-order harmonic load impedance, namely, Z.sub.22=Z.sub.10, and obtaining an optimal fundamental wave load impedance Z.sub.20 by load pull, wherein Z.sub.20 is affected by the second-order harmonic load impedance Z.sub.22: at step 3, setting the fundamental frequency to f.sub.3, fixing Z.sub.10 as a third-order harmonic load impedance, namely, Z.sub.33=Z.sub.10, fixing Z.sub.20 as a second-order harmonic load impedance, namely, Z.sub.32=Z.sub.20, and obtaining an optimal fundamental wave load impedance Z.sub.30 by load pull, wherein Z.sub.30 is affected by the second-order harmonic load impedance Z.sub.32 and the third-order harmonic load impedance Z.sub.33; at step 4, by substituting the optimal fundamental wave impedance into the following formula, calculating an initial value of a drain line impedance: $\begin{array}{cc}{G}_{CD\left(1\right)}=G_{OPT\left(1\right)}& \left(0.2\right)\end{array}$ $\begin{array}{cc}{G}_{CD\left(i2\right)}=\left(\frac{G_{\mathrm{OPT}\left(1\right)}^2}{G_{\mathrm{DL}}+G_{\mathrm{OPT}\left(1\right)}}+\underset{k=2}{\overset{i}{.Math.}}{G}_{\mathrm{OPT}\left(k\right)}\right)& \left(0.3\right)\end{array}$ wherein G.sub.CD(1) is an optimal characteristic conductance of a first-segment drain line, G.sub.OPT(1) is an optimal fundamental wave conductance of a first-level transistor, G.sub.CD(n) is an optimal characteristic conductance of an n-th-segment drain line, G.sub.DL is a drain terminating resistance, G.sub.OPT(n)=1/R.sub.OPT(n)=re(Z.sub.opt(n)) is an optimal fundamental wave conductance of an n-th-level transistor, and G.sub.OPT(k) is an optimal fundamental wave conductance of a k-th-level transistor; determining an initial value of a gate line impedance in the following formula: $\begin{array}{cc}{G}_{\mathrm{CG}\left(i\right)}=\underset{k=i}{\overset{n}{.Math.}}{G}_{\mathrm{IN}\left(k\right)}& \left(0.4\right)\end{array}$ wherein G.sub.CG(i) is an optimal characteristic conductance of an i-th-segment gate line, and G.sub.IN(k) is an input conductance of the k-th-level transistor; further, an electrical length of the gate line and an electrical length of the drain line satisfy the following relationship, wherein .sub.CG(i) is an electrical length of an i-th-segment gate line and .sub.CD(i) is an electrical length of an i-th-segment drain line: $\begin{array}{cc}{}_{\mathrm{CG}\left(i\right)}={}_{\mathrm{CD}\left(i\right)}& \left(0.5\right)\end{array}$ at step 5, terminating the second-order harmonic impedance of the f.sub.1 frequency band to a pure reactance part to realize a class-J working mode, and adjusting the electrical lengths of the gate line and the drain line, and when the condition of .sub.CG(i)=.sub.CD(i) is satisfied, introducing reactance to offset an imaginary component of the optimal fundamental wave impedance so as to complete optimization on the harmonic control-based distributed power amplifier.

2. The optimization method of claim 1, wherein in the step 4, G.sub.DL=0.

3. The optimization method of claim 1, wherein in the step 5, the gate line and the drain line are respectively terminated with inductors L.sub.1 and L.sub.2.

Description

BRIEF DESCRIPTIONS OF THE DRAWINGS

[0026] FIG. 1 is a topological schematic diagram illustrating a circuit structure of a conventional NDA.

[0027] FIG. 2 shows a circuit architecture diagram of a harmonic control-based distributed power amplifier according to a specific implementation 1 of the present disclosure.

[0028] FIG. 3 shows a circuit architecture diagram of a class-J distributed ultra-wideband power amplifier of power combination according to a specific implementation 2 of the present disclosure.

[0029] FIG. 4 shows a circuit architecture diagram of a hybrid cascaded multi-octave class-J distributed power amplifier according to a specific implementation 3 of the present disclosure.

[0030] FIG. 5 shows a small signal test diagram of a harmonic control-based distributed power amplifier according to an embodiment of the present disclosure, where a represents return loss and b represents gain.

[0031] FIG. 6 shows a large signal test diagram of a harmonic control-based distributed power amplifier according to an embodiment of the present disclosure, where .square-solid. represents output power, .box-tangle-solidup. represents gain, and represents efficiency.

DETAILED DESCRIPTIONS OF EMBODIMENTS

[0032] Specific implementation 1: in this implementation, the harmonic control-based distributed power amplifier includes an input artificial uniform transmission line 1, an output artificial non-uniform transmission line 2 and plural gain units 3; two ports of the output artificial non-uniform transmission line 2 are connected respectively with reactive terminals 4 (L.sub.1 and L.sub.2), and in each gain unit 3, a gate electrode of a transistor is connected with an RC parallel resonant circuit.

[0033] Specific implementation 2: this implementation differs from the specific implementation 1 in that an output end of the output artificial non-uniform transmission line 2 is connected with a class-J (amplifier output) matching network.

[0034] Specific implementation 3: in this implementation, the class-J distributed ultra-wideband power amplifier of power combination includes two harmonic control-based distributed power amplifiers, a power distribution network 5, a power combination network 6 and a class-J amplifier output matching network 11; two ports of the power distribution network 5 are respectively coupled to the input artificial uniform transmission lines 1 of the two harmonic control-based distributed power amplifiers, the output artificial non-uniform transmission lines 2 of the two harmonic control-based distributed power amplifiers are coupled via the power combination network 6, and the power combination network 6 is cascaded with the class-J amplifier output matching network 11.

[0035] In this implementation, wide band power combination is performed on two improved NDAs at the output port. In the present disclosure, lumped power divider and power combiner based on tap coupling inductance solve the problems of large area and narrow bandwidth of the conventional power combination, and by using planar thin-film inductive coupling technology, a desired inductance amount is reduced and a miniature passive device is obtained.

[0036] Specific implementation 4: in this implementation, the hybrid cascaded multi-octave class-J distributed power amplifier includes a drive stage power amplification unit, a (lumped) wideband matching network 7, and the class-J distributed ultra-wideband power amplifier of power combination; the drive stage power amplification unit, the wideband matching network 7 and the class-J distributed ultra-wideband power amplifier of power combination are sequentially cascaded along a signal transmission direction, and the drive stage power amplification unit is formed by parallel-connecting a negative feedback network 8 and a common source-common gate-common gate three-level stacking structure 9.

[0037] In this implementation, the class-J distributed ultra-wideband power amplifier of power combination is used as output stage and a miniature negative feedback reactive drive wideband power amplifier is designed and integrated and the hybrid cascading method is used to realize high-power and high-gain output of the MMIC power amplifier. In the drive stage power amplifier, the transistor uses the common source-common gate-common gate three-level stacking structure to obtain higher and flatter gain and bandwidth, so as to obtain a higher gain bandwidth product. With the parallel negative feedback network structure, the series resistor and the series reactor in the network improve the gain flatness of the gain and the stability of the transistor under large bandwidth. At the input port, the first-order equalizer is series-connected as gain compensation network to obtain excellent wideband matching and gain consistency. Further, the lumped wideband matching network is used to implement hybrid cascading of the reactive and distributed power amplifiers so as to realize a high-gain MMIC power amplifier under ultra-wideband.

[0038] Specific implementation 5: this implementation differs from the specific implementation 4 in that a gain compensation network 10 is coupled between a signal input end and the drive stage power amplification unit.

[0039] Specific implementation 6: this implementation differs from the specific implementation 5 in that the gain compensation network 10 is a first-order equalizer.

[0040] Specific implementation 7: in this implementation, an optimization method of the harmonic control-based distributed power amplifier, wherein the optimization method is carried out in the following steps: [0041] at step 1, dividing a working frequency band into f.sub.1, f.sub.2 and f.sub.3, setting a fundamental frequency to f.sub.1(f.sub.1f.sub.1), and obtaining an optimal fundamental wave load impedance Z.sub.10 by load pull, using Z.sub.10 as a second or third-order fixed harmonic load impedance of a frequency point within the f.sub.2 frequency band, wherein a class-J mode second-order harmonic load impedance of f.sub.1 is calculated in the following formula (1.1):

[00005]$\begin{array}{cc}{Z}_{12}=\frac{0.5\left(V_{DD}-V_K\right)j}{\frac{2I_{\max }}{3}}=0-j\frac{3}{8}{R}_{{\mathrm{opt}}_B}& \left(\mathrm{imaginary}\mathrm{part}\right)\left(1.1\right)\end{array}$ [0042] wherein V.sub.DD is a voltage of a power supply, V.sub.K is a knee voltage of a transistor, I.sub.max is a maximal drain current of a transistor 11 is a constant parameter, R.sub.opt.sub.B=2 (V.sub.DDV.sub.K)/I.sub.max is an optimal fundamental wave load impedance of a class-B power amplifier (PA); [0043] at step 2, setting the fundamental wave to f.sub.2(f.sub.2f.sub.2, f.sub.1=2f.sub.2), and fixing Z.sub.10 as a second-order harmonic load impedance, namely, Z.sub.22=Z.sub.10, and obtaining an optimal fundamental wave load impedance Z.sub.20 by load pull, wherein Z.sub.20 is affected by the second-order harmonic load impedance Z.sub.22; [0044] at step 3, setting the fundamental frequency to f.sub.3(f.sub.3f.sub.3, f.sub.1=3f.sub.3), fixing Z.sub.10 as a third-order harmonic load impedance, namely, Z.sub.33=Z.sub.10, fixing Z.sub.20 as a second-order harmonic load impedance, namely, Z.sub.32=Z.sub.20, and obtaining an optimal fundamental wave load impedance Z.sub.23 by load pull, wherein Z.sub.30 is affected by the second-order harmonic load impedance Z.sub.32 and the third-order harmonic load impedance Z.sub.33; [0045] at step 4, by substituting the optimal fundamental wave impedance into the following formula, calculating an initial value of a drain line impedance:

[00006]$\begin{array}{cc}{G}_{CD\left(1\right)}=G_{OPT\left(1\right)}& \left(1.2\right)\end{array}$$\begin{array}{cc}{G}_{\mathrm{CD}\left(i2\right)}=\left(\frac{G_{\mathrm{OPT}\left(1\right)}^2}{G_{DL}+G_{OPT\left(1\right)}}+\underset{k=2}{\overset{i}{.Math.}}{G}_{\mathrm{OPT}\left(k\right)}\right)& \left(1.3\right)\end{array}$ [0046] wherein G.sub.CD(1) is an optimal characteristic conductance of a first-segment drain line, G.sub.OPT(1) is an optimal fundamental wave conductance of a first-level transistor, G.sub.CD(n) is an optimal characteristic conductance of an n-th-segment drain line, G.sub.DL is a drain terminating resistance, G.sub.OPT(n)=1/R.sub.OPT(n)=re(Z.sub.opt(n)) is an optimal fundamental wave conductance of an n-th-level transistor, and G.sub.OPT(k) is an optimal fundamental wave conductance of a k-th-level transistor; [0047] determining an initial value of a gate line impedance in the following formula:

[00007]$\begin{array}{cc}{G}_{CG\left(i\right)}=\underset{k=i}{\overset{n}{.Math.}}{G}_{\mathrm{IN}\left(k\right)}& \left(1.4\right)\end{array}$

[0048] wherein G.sub.CG(i) is an optimal characteristic conductance of an i-th-segment gate line, and G.sub.IN(k) is an input conductance of the k-th-level transistor; [0049] further, an electrical length of the gate line and an electrical length of the drain line satisfy the following relationship, wherein .sub.CG(i) is an electrical length of an i-th-segment gate line and .sub.CD(i) is an electrical length of an i-th-segment drain line:

[00008]$\begin{array}{cc}{}_{\mathrm{CG}\left(i\right)}={}_{\mathrm{CD}\left(i\right)}& \left(1.5\right)\end{array}$ [0050] at step 5, terminating the second-order harmonic impedance of the f.sub.1 frequency band to a pure reactance part to realize a class-J working mode, and adjusting the electrical lengths of the gate line and the drain line, and when the condition of .sub.CG(i)=.sub.CD(i) is satisfied, introducing reactance to offset an imaginary component of the optimal fundamental wave impedance so as to complete optimization on the harmonic control-based distributed power amplifier.

[0051] In this implementation, the non-negligible imaginary component of the artificial transmission line at high frequency end is absorbed into the class-J amplifier output matching network so as to obtain a low-loss, large-bandwidth and high-efficiency harmonic-control-based class-J distributed amplifier.

[0052] In this implementation, by using load pull technology, optimization is performed on high-order harmonic to know the influence of the high-order harmonic on the output power and efficiency; secondly, the influence of the high-frequency fundamental wave and low-frequency harmonic impedances of the improved NDA on the output power and efficiency is analyzed; thirdly, based on the harmonic-fundamental wave impedance allocation model, the influence of each harmonic impedance and each fundamental wave impedance of the class-J ultra-wideband power amplifier on the output power and efficiency is analyzed, and based on an analysis result, key parameters affecting an efficiency and power mathematic model of the class-J ultra-wideband power amplifier are obtained, where the key parameters include the fundamental wave impedance, the harmonic impedance, the terminating load and the working mode and the like of each level of transistor; fourthly, based on the above key parameters, the circuit architecture of the class-J distributed power amplifier is designed and the non-negligible imaginary component of the artificial transmission line at high frequency end is absorbed into the class-J amplifier output matching network so as to obtain a low-loss, large-bandwidth and high-efficiency harmonic-control-based class-J distributed amplifier.

[0053] Specific implementation 8: this implementation differs from the specific implementation 7 in that G.sub.DL=0 in the step 4.

[0054] Specific implementation 9: this implementation differs from the specific implementation 7 or 8 in that in the step 5, the gate line and the drain line are respectively terminated with inductors L.sub.1 and L.sub.2.

[0055] Embodiment 1: in this embodiment, the harmonic control-based distributed power amplifier includes an input artificial uniform transmission line, an output artificial non-uniform transmission line, and plural gain units, wherein two ports of the output artificial non-uniform transmission line are respectively connected with reactive terminals, and in each gain unit, a gate electrode of a transistor is connected with an RC parallel resonant circuit.

[0056] Embodiment 2: in this embodiment, the optimization method of the harmonic control-based distributed power amplifier is carried out in the following steps: [0057] at step 1, dividing an intra-band working frequency band into three parts: f.sub.1=918 GHz, f.sub.2=69 GHz and f.sub.3=26 GHz, wherein all high-order harmonics of f.sub.1 are all outside the working frequency band; the second-order harmonic of f.sub.2 is within the working frequency band, and the third-order or higher harmonic is outside the working frequency band; the third-order or higher harmonic of f.sub.2 is within the working frequency band; setting a fundamental frequency to f.sub.1(f.sub.1f.sub.1) and obtaining an optimal fundamental wave load impedance Z.sub.10 by load pull, using Z.sub.10 as a second or third-order fixed harmonic load impedance of a frequency point within the f.sub.2 frequency band, wherein a class-J mode second-order harmonic load impedance of f.sub.1 is calculated in the following formula (1.1):

[00009]$\begin{array}{cc}{Z}_{12}=\frac{0.5\left(V_{DD}-V_K\right)j}{\frac{2I_{\max }}{3}}=0-j\frac{3}{8}{R}_{{\mathrm{opt}}_B}& \left(1.1\right)\end{array}$ [0058] wherein V.sub.DD is a voltage of a power supply, V.sub.K is a knee voltage of a transistor, I.sub.max is a maximal drain current of a transistor 11 is a constant parameter, R.sub.opt.sub.B=2(V.sub.DDV.sub.K)/I.sub.max is an optimal fundamental wave load impedance of a class-B power amplifier (PA); [0059] at step 2, setting the fundamental wave to f.sub.2(f.sub.2 f.sub.2, f=2f.sub.2), and fixing Z.sub.10 as a second-order harmonic load impedance, namely, Z.sub.22=Z.sub.10, and obtaining an optimal fundamental wave load impedance Z.sub.20 by load pull, wherein Z.sub.20 is affected by the second-order harmonic load impedance Z.sub.22; [0060] at step 3, setting the fundamental frequency to f.sub.3(f.sub.3f.sub.3, f.sub.1=3f.sub.3), fixing Z.sub.10 as a third-order harmonic load impedance, namely, Z.sub.33=Z.sub.10, fixing Z.sub.20 as a second-order harmonic load impedance, namely, Z.sub.32=Z.sub.20, and obtaining an optimal fundamental wave load impedance Z.sub.30 by load pull, wherein Z.sub.30 is affected by the second-order harmonic load impedance Z.sub.22 and the third-order harmonic load impedance Z.sub.33; [0061] at step 4, by substituting the optimal fundamental wave impedance into the following formula, calculating an initial value of a drain line impedance:

[00010]$\begin{array}{cc}{G}_{CD\left(1\right)}=G_{OPT\left(1\right)}& \left(1.2\right)\end{array}$$\begin{array}{cc}{G}_{\mathrm{CD}\left(i>2\right)}=\left(\frac{G_{\mathrm{OPT}\left(1\right)}^2}{G_{DL}+G_{OPT\left(1\right)}}+\underset{k=2}{\overset{i}{.Math.}}{G}_{\mathrm{OPT}\left(k\right)}\right)& \left(1.3\right)\end{array}$ [0062] wherein G.sub.CD(1) is an optimal characteristic conductance of a first-segment drain line, G.sub.OPT(1) is an optimal fundamental wave conductance of a first-level transistor, G.sub.CD(n) is an optimal characteristic conductance of an n-th-segment drain line, G.sub.DL is a drain terminating resistance, G.sub.DL=0, G.sub.OPT(n)=1/R.sub.OPT(n)=re (Z.sub.opt(n)) is an optimal fundamental wave conductance of an n-th-level transistor, and G.sub.OPT(k) is an optimal fundamental wave conductance of a k-th-level transistor; [0063] determining an initial value of a gate line impedance in the following formula:

[00011]$\begin{array}{cc}{G}_{CG\left(i\right)}=\underset{k=i}{\overset{n}{.Math.}}{G}_{\mathrm{IN}\left(k\right)}& \left(1.4\right)\end{array}$

[0064] wherein G.sub.CG(i) is an optimal characteristic conductance of an i-th-segment gate line, and G.sub.IN(k) is an input conductance of the k-th-level transistor; [0065] further, an electrical length of the gate line and an electrical length of the drain line satisfy the following relationship:

[00012]$\begin{array}{cc}{}_{CG\left(i\right)}={}_{CD\left(i\right)}& \left(1.5\right)\end{array}$ [0066] at step 5, terminating the gate line and the drain line respectively with inductors L.sub.1 and L.sub.2 to avoid power consumption of backward echo, terminating the second-order harmonic impedance of the f.sub.1 frequency band to a pure reactance part to realize a class-J working mode, and adjusting the electrical lengths of the gate line and the drain line, and when the condition of .sub.CG(i)=.sub.CD(i) is satisfied, introducing reactance to offset an imaginary component of the optimal fundamental wave impedance so as to complete optimization on the harmonic control-based distributed power amplifier.

[0067] The small signal result of FIG. 5 shows the power amplifier within 2-18 GHz has a flat gain of more than 18 dB and a return loss of more than-10 dB. The large signal result of FIG. 6 shows a maximal saturated output power of more than 43 dBm (20 W) and a power-added efficiency of greater than 30% within 2-18 GHz, and the result is far greater than that of the conventional distributed amplifier. It is proved that the class-J distributed amplifier in the present disclosure has the characteristics of ultra-wideband, high efficiency and high gain.