OVER CURRENT PROTECTION CIRCUIT ARRANGED FOR PROVIDING AN OVER CURRENT SIGNAL, AS WELL AS A CORRESPONDING METHOD AND COMPUTER PROGRAM PRODUCT

Abstract

An over current protection circuit arranged for providing an over current signal, the over current protection circuit includes a compare stage arranged for determining that a blanking time value is higher than a predefined reference value, an output stage arranged for outputting the over current signal based on the determination, a blanking time stage arranged for generating the blanking time value, and the blanking time stage is arranged to start generating the blanking time value upon a load current exceeding a predefined set current, the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.

Claims

1. An over current protection circuit arranged for providing an over current signal, the over current protection circuit comprising: a compare stage arranged for determining that a blanking time value is higher than a predefined reference value; an output stage arranged for outputting the over current signal based on the determination; and a blanking time stage arranged for generating the blanking time value, wherein the blanking time stage is arranged to start generating the blanking time value upon a load current exceeding a predefined set current, wherein the blanking time stage is further arranged to modulate the blanking time value based on a magnitude in which the load current exceeds the predefined set current.

2. The over current protection circuit in accordance with claim 1, wherein the blanking time stage is arranged to modulate the blanking time value so that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current.

3. The over current protection circuit in accordance with claim 1, wherein the blanking time stage is arranged to module the blanking time value so that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current.

4. The over current protection circuit in accordance with claim 1, wherein the blanking time stage comprises: a timer capacitor arranged for storing energy; a first current source arranged for charging the timer capacitor; a current provided by the first current source that is proportional to the predefined set current; a second current source arranged for discharging the timer capacitor; a current provided by the second current source is proportional to the load current; and an output of the timer capacitor is connected to the compare stage.

5. The over current protection circuit in accordance with claim 4, wherein the blanking time stage further comprises: a third current source for discharging the timer capacitor, wherein the third current source has a current provided that is constant.

6. The over current protection circuit in accordance with claim 4, wherein the compare stage comprises: a first comparator having an inverting input and a non-inverting input, wherein the inverting input of the first comparator is connected to the output of the timer capacitor, and the non-inverting output of the first comparator is connected to the predefined reference value.

7. The over current protection circuit in accordance with claim 5, wherein the compare stage further comprises: a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current, wherein the output stage comprises: an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.

8. The over current protection circuit in accordance with claim 7, wherein the blanking time stage further comprises: a switch connected in series with the third current source for activating, and deactivating, the third current source, and wherein the switch is controlled by the output of the second comparator.

9. A method for providing an over current signal using an over current protection circuit in accordance with claim 1, wherein the method comprises the steps of: determining, by the compare stage, that a blanking time value is higher than a predefined reference value; outputting, by the output stage, the over current signal based on the determination; and generating, by the blanking time stage, the blanking time value, wherein the blanking time value is started to be generated upon a load current exceeding a predefined set current, wherein the step of generating comprises modulating the blanking time value based on a magnitude in which the load current exceeds the predefined set current.

10. The method in accordance with claim 9, wherein the step of modulating further comprises: modulating the blanking time value so that the blanking time value is inversely proportional to the magnitude in which the load current exceeds the predefined set current.

11. The method in accordance with claim 9, wherein the step of modulating further comprises: modulating the blanking time value so that the blanking time value is proportional to the square of the magnitude in which the load current exceeds the predefined set current.

12. The method in accordance with claim 9, wherein the blanking time stage comprises: a timer capacitor arranged for storing energy; a first current source arranged for charging the timer capacitor; a current provided by the first current source is proportional to the predefined set current; a second current source arranged for discharging the timer capacitor; a current provided by the second current source is proportional to the load current; and an output of the timer capacitor is connected to the compare stage.

13. The method in accordance with claim 10, wherein the blanking time stage comprises: a timer capacitor arranged for storing energy; a first current source arranged for charging the timer capacitor; a current provided by the first current source is proportional to the predefined set current; a second current source arranged for discharging the timer capacitor; a current provided by the second current source is proportional to the load current; and an output of the timer capacitor is connected to the compare stage.

14. The method in accordance with claim 12, wherein the blanking time stage further comprises: a third current source for discharging the timer capacitor, wherein the third current source provides a current that is constant.

15. The method in accordance with claim 12, wherein the compare stage comprises: a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value; a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current; a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator; wherein the output stage comprises: an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.

16. The method in accordance with claim 14, wherein the compare stage comprises: a first comparator having an inverting input that is connected to the output of the timer capacitor and a non-inverting output that is connected to the predefined reference value; a second comparator having an inverting output that is arranged to receive the predefined set current and a non-inverting input that is connected to the load current; a switch connected in series with the third current source for activating, and deactivating, the third current source, wherein the switch is controlled by the output of the second comparator; wherein the output stage comprises: an AND port arranged for receiving an output of the first comparator and an output of the second comparator, wherein the AND port has an output that is the over current signal.

17. A computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with claim 9.

18. A computer program product comprising a non-transitory computer readable medium having instructions stored thereon which, when executed by a controller, cause the controller to implement a method in accordance with claim 10.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0075] FIG. 1 discloses an example of an over current protection circuit in accordance with the present disclosure.

[0076] FIG. 2 discloses a typical waveform associated with the over current protection circuit in accordance with the present disclosure.

[0077] FIG. 3 discloses the blanking time value versus the over current percentage.

DETAILED DESCRIPTION

[0078] It is noted that in the description of the figures, same reference numerals refer to the same or similar components performing a same or essentially similar function.

[0079] A more detailed description is made with reference to particular examples, some of which are illustrated in the appended drawings, such that the manner in which the features of the present disclosure may be understood in more detail. It is noted that the drawings only illustrate typical examples and are therefore not to be considered to limit the scope of the subject matter of the claims. The drawings are incorporated for facilitating an understanding of the disclosure and are thus not necessarily drawn to scale. Advantages of the subject matter as claimed will become apparent to those skilled in the art upon reading the description in conjunction with the accompanying drawings.

[0080] The ensuing description above provides preferred exemplary embodiment(s) only, and is not intended to limit the scope, applicability or configuration of the disclosure. Rather, the ensuing description of the preferred exemplary embodiment(s) will provide those skilled in the art with an enabling description for implementing a preferred exemplary embodiment of the disclosure, it being understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the disclosure.

[0081] Unless the context clearly requires otherwise, throughout the description and the claims, the words comprise, comprising, and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of including, but not limited to. As used herein, the terms connected, coupled, or any variant thereof means any connection or coupling, either direct or indirect, between two or more elements; the coupling or connection between the elements can be physical, logical, electromagnetic, or a combination thereof. Additionally, the words herein, above, below, and words of similar import, when used in this application, refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word or in reference to a list of two or more items, covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0082] These and other changes can be made to the technology in light of the following detailed description. While the description describes certain examples of the technology, and describes the best mode contemplated, no matter how detailed the description appears, the technology can be practiced in many ways. Details of the system may vary considerably in its specific implementation, while still being encompassed by the technology disclosed herein. As noted above, particular terminology used when describing certain features or aspects of the technology should not be taken to imply that the terminology is being redefined herein to be restricted to any specific characteristics, features, or aspects of the technology with which that terminology is associated. In general, the terms used in the following claims should not be construed to limit the technology to the specific examples disclosed in the specification, unless the Detailed Description section explicitly defines such terms. Accordingly, the actual scope of the technology encompasses not only the disclosed examples, but also all equivalent ways of practicing or implementing the technology under the claims.

[0083] FIG. 1 discloses an example of an over current protection circuit in accordance with the present disclosure.

[0084] As mentioned above, in one of the implementations of the present disclosure, a timer capacitor 4 is used. The timer capacitor 4 is being charged, and discharged, using a first current source 1 and a second current source 2, respectively.

[0085] It is noted that the current sources 1, 2 may, alternatively, also be swapped. In this case, the inputs of the compare stage may need to be swapped as well. In the remainder it is assumed that the first current source 1 is proportional to the predefined set current and the second current source 2 is proportional to the load current.

[0086] It may be clear that the timer capacitor 4 is being charged whenever the load current is lower compared to the predefined set current. The timer capacitor 4 is discharged whenever the load current is higher compared to the predefined set current.

[0087] A first comparator 5 is provided. The first comparator 5 compares two inputs with one another. If the input provided at the non-inverting input of the first comparator 5 is higher compared to the input provided at the inverting input of the first comparator 5, then the comparator will output a logical high level.

[0088] The inverting input of the first comparator 5 is connected to the timer capacitor 4. This means that the voltage over the timer capacitor 4 is provided as an input to the inverting input of the first comparator 5.

[0089] The predefined reference value is connected to the non-inverting input of the first comparator 5. The predefined reference value is directly related to the value at which the over current protection circuit should act, i.e. it is related to the trip current.

[0090] As is clear from this particular implementation, there is a delay before the first comparator 5 will issue a logical high signal. The first comparator 5 will not immediately issue a logical high signal when the load current is higher that the predefined set current. First, the timer capacitor 4 needs to discharge to below the predefined reference value before the first comparator 5 issues the logical high level. This is one of the concepts of the present disclosure.

[0091] This particular implementation may further comprise an AND gate as indicated with reference numeral 7, a second comparator as indicated with reference numeral 6, a switch as indicated with reference numeral 8 and a third current source as indicated with reference numeral 3. These are explained here below.

[0092] The third current source 3 is used to expedite the discharging process. It is a predefined constant current that may be initially set to calibrate the over current protection circuit.

[0093] The third current source 3 may only be triggered, i.e. activated, whenever the load current is actually higher than the predefined set current. This is accomplished by using the switch 8 in combination with the second comparator 6. The second comparator 6 compared the load current with the predefined set current and output a logical high signal whenever the load current is higher compared to the predefined set current.

[0094] This logical high signal is used for controlling the switch 8. If the signal is high, then the switch 8 is activated, such that the third current source 3 is activated. If the signal is low, then the switch 8 is deactivated, such that the third current source is deactivated.

[0095] The over current protection circuit may thus comprise a second comparator 6, wherein an inverting output of said second comparator is arranged to receive said predefined set current, and wherein a non-inverting input of said second comparator is connected to said load current.

[0096] The output stage may comprise an AND port 7 for receiving an output of said first comparator and an output of said second comparator, wherein an output of said AND port 7 is said over current signal.

[0097] FIG. 2 discloses a typical waveform associated with the over current protection circuit in accordance with the present disclosure;

[0098] The first stage is related to the working operating in which the load current is lower compared to the predefined set current, i.e. the trip current. In this stage, the timer capacitor will be charged to its maximum value. This is indicated with the wording TMR pulled HI (Normal Operation).

[0099] In a second stage, the load current will exceed the predefined set current. This would lead to the situation wherein the timer capacitor starts to discharge. This second phase is indicated with the wording IOUT exceeds ILIM and TMR starts discharging.

[0100] In the third stage, the timer capacitor has charged to just below the predefined reference value, such that over current protection circuit will activate and issue a over current signal. This third stage is indicated with TMR reaches lower threshold and IOUT Limited to ILIM.

[0101] It is noted that the over current signal may be used, by further circuitry, to limit the load current to the trip current. This is denoted in the third stage as well. Finally, a shutdown may be initiated if the load current does not further reduce to well below the trip current as indicated with the wording Shutdown due to OTP.

[0102] FIG. 3 discloses the blanking time value versus the over current percentage.

[0103] This particular graph related to the time that has passed until the over current protection activates. The first line, 1, is related to the prior art, wherein this particular time is constant, i.e. not related to the percentage of the over current condition. Whether the load current is way above the trip current, or close to the trip current, is not relevant for the prior art. The delay is always the same, for example about 100 ms.

[0104] Lines having reference numerals 2 and 3 are related to the present disclosure. Line 2 is related to the situation in which no third current source (see FIG. 1) is present. Line 3 is related to the situation in which a third current source (see FIG. 2) is present. As shown, the delay time, i.e. the time required before the over current protection circuit issues an over current signal, depends on the percentage of the over current condition. If hardly any over current situation occurs, then the so-called blanking time may be relatively large, for example 500 ms. However, for a very high over-current situation, the over current protection circuit may quickly issue the over current signal, i.e. well before the prior art solution.

[0105] To reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but the applicant contemplates the various aspects of the technology in any number of claim forms. For example, while some aspect of the technology may be recited as a computer-readable medium claim, other aspects may likewise be embodied as a computer-readable medium claim, or in other forms, such as being embodied in a means-plus-function claim.

[0106] In the description above, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of implementations of the disclosed technology. It will be apparent, however, to one skilled in the art that embodiments of the disclosed technology may be practiced without some of these specific details.

[0107] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed disclosure, from a study of the drawings, the disclosure and the appended claims. In the claims, the word comprising does not exclude other elements or steps, and the indefinite article a or an does not exclude a plurality. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.