CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Abstract

A circuit board structure includes a core layer, at least one electroplating metal layer, at least one dielectric layer and at least one conductive metal layer. The core layer includes at least one dielectric portion and at least one metal portion. The electroplating metal layer is disposed on at least one of a first surface and a second surface of the core layer, exposing a portion of at least one of the first surface and the second surface and at least connecting the at least one metal part. The dielectric layer is disposed on at least one of the first surface and the second surface and on the electroplating metal layer. The dielectric layer has at least one opening exposing a portion of the electroplating metal layer. The conductive metal layer is disposed in the opening of the dielectric layer and is correspondingly connected to the electroplating metal layer.

Claims

1. A circuit board structure, comprising: a core layer, having a first surface and a second surface opposite to each other, and comprising at least one dielectric portion and at least one metal portion; at least one electroplating metal layer, disposed on at least one of the first surface and the second surface of the core layer, exposing a portion of at least one of the first surface and the second surface and at least connected to the at least one metal portion; at least one dielectric layer, disposed on at least one of the first surface and the second surface of the core layer and on the at least one electroplating metal layer, the at least one dielectric layer has at least one opening, and the at least one opening exposes a portion of the at least one electroplating metal layer; and at least one conductive metal layer, disposed in the at least one opening of the at least one dielectric layer and correspondingly connected to the at least one electroplating metal layer.

2. The circuit board structure according to claim 1, wherein a material of the at least one metal portion, a material of the at least one electroplating metal layer, and a material of the at least one conductive metal layer comprise copper.

3. The circuit board structure according to claim 1, wherein a thickness of the core layer is greater than or equal to 200 m and less than or equal to 500 m.

4. The circuit board structure according to claim 1, wherein a thickness of the at least one dielectric layer is greater than or equal to 50 m and less than 300 m.

5. The circuit board structure according to claim 1, further comprising: at least one build-up metal layer, disposed on the at least one conductive metal layer; and at least one solder mask layer, disposed on the at least one dielectric layer, the at least one solder mask layer has at least one solder mask opening, and the at least one solder mask opening exposes a portion of the at least one build-up metal layer to define at least one pad area, wherein each of the at least one conductive metal layer and the at least one build-up metal layer is an electroplating layer.

6. The circuit board structure according to claim 1, wherein the at least one dielectric portion is a plurality of dielectric portions, and a number of the at least one metal portion is one; the at least one electroplating metal layer comprises two electroplating metal layers, which are respectively disposed on the first surface and the second surface of the core layer, respectively expose a portion of the first surface and a portion of the second surface, and are connected to the metal portion and at least one of the dielectric portions; the at least one dielectric layer comprises two dielectric layers, which are respectively disposed on the first surface and the second surface of the core layer and on the two electroplating metal layers, each of the two dielectric layers has the at least one opening, the at least one opening comprises a first opening and a second opening, the first opening exposes the two electroplating metal layers connected to at least one of the dielectric portions, and the second opening exposes the two electroplating metal layers connected to the metal portion; the at least one conductive metal layer comprises two conductive metal layers, one of the two conductive metal layers is disposed in the first opening and the second opening of one of the two dielectric layers and is connected to a corresponding one of the two electroplating metal layers, and another one of the two conductive metal layers is disposed in the first opening of another one of the two dielectric layers and connected to another corresponding one of the two electroplating metal layers, wherein each of the two conductive metal layers is a conductive paste layer.

7. The circuit board structure according to claim 6, further comprising: an electrically insulating and thermally conductive paste layer, disposed in the second opening of the another one of the two dielectric layers and connected to the another corresponding one of the two electroplating metal layers.

8. The circuit board structure according to claim 1, a number of the at least one dielectric portion is one, the at least one metal portion comprises a first metal portion and a second metal portion, the at least one opening comprises a first opening and a second opening, the at least one electroplating metal layer is connected to the first metal portion, the first opening exposes a portion of the at least one electroplating metal layer, the second opening exposes a portion of the second metal portion, and the at least one conductive metal layer is disposed in the first opening and the second opening, is correspondingly connected to the at least one electroplating metal layer and the second metal portion and extends to the at least one dielectric layer.

9. The circuit board structure according to claim 8, further comprising: at least one build-up dielectric layer, disposed on the at least one dielectric layer, the at least one build-up dielectric layer has at least one third opening, and the at least one third opening exposes a portion of the at least one conductive metal layer; and at least one build-up metal layer, disposed in the at least one third opening, connected to the at least one conductive metal layer and extending to the at least one build-up dielectric layer, wherein each of the at least one conductive metal layer and the at least one build-up dielectric layer is at least one electroplating layer.

10. The circuit board structure according to claim 9, further comprising: at least one solder mask layer, disposed on the at least one build-up dielectric layer, the at least one solder mask layer has at least one solder mask opening, and the at least one solder mask opening exposes a portion of the at least one build-up metal layer to define at least one pad area.

11. A manufacturing method of a circuit board structure, comprising: providing a core layer, the core layer has a first surface and a second surface opposite to each other and comprises at least one dielectric portion and at least one metal portion; electroplating at least one electroplating metal layer on at least one of the first surface and the second surface of the core layer, the at least one electroplating metal layer exposes a portion of at least one of the first surface and the second surface and is at least connected to the at least one metal portion; laminating at least one dielectric layer on at least one of the first surface and the second surface of the core layer and on the at least one electroplating metal layer; performing a drilling process on the at least one dielectric layer to form at least one opening that exposes a portion of the at least one electroplating metal layer; and forming at least one conductive metal layer in the at least one opening of the at least one dielectric layer, and the at least one conductive metal layer is correspondingly connected to the at least one electroplating metal layer.

12. The manufacturing method of the circuit board structure according to claim 11, wherein the at least one dielectric portion is a plurality of dielectric portions, and the at least one metal portion comprises a metal portion, and the step of providing the core layer comprises: providing a copper plate having the first surface and the second surface, wherein a thickness of the copper plate is greater than or equal to 200 m and less than or equal to 500 m; performing a first half etching process on the first surface of the copper plate to form a plurality of first cavities on the first surface; filling a first dielectric paste in the first cavities; performing a second half-etching process on the second surface of the copper plate to form a plurality of second cavities on the second surface and in communication with the first cavities to define the metal portion, wherein the second cavities expose the first dielectric paste; and filling a second dielectric paste in the second cavities, and the second dielectric paste is connected to the first dielectric paste to define the dielectric portions.

13. The manufacturing method of the circuit board structure according to claim 12, wherein the step of forming the at least one conductive metal layer in the at least one opening of the at least one dielectric layer comprises: forming at least one electroplating seed layer on the at least one dielectric layer and in the at least one opening; forming at least one first patterned photoresist layer on the at least one electroplating seed layer, the at least one first patterned photoresist layer exposes a portion of the at least one electroplating seed layer located in the at least one opening; with the at least one first patterned photoresist layer as an electroplating mask, electroplating a first metal material on the at least one electroplating seed layer exposed by the at least one first patterned photoresist layer; removing the at least one first patterned photoresist layer to expose the at least one electroplating seed layer and the first metal material; forming at least one second patterned photoresist layer on the at least one electroplating seed layer, the at least one second patterned photoresist layer exposes the first metal material and a portion of the at least one electroplating seed layer; with the at least one second patterned photoresist layer as an electroplating mask, electroplating a second metal material on the first metal material and the at least one electroplating seed layer exposed by the at least one second patterned photoresist layer; and removing the at least one second patterned photoresist layer and the at least one electroplating seed layer thereunder to expose the at least one dielectric layer and form at least one build-up metal layer and the at least one conductive metal layer that is in the at least one opening of the at least one dielectric layer and connected to the at least one build-up metal layer.

14. The manufacturing method of the circuit board structure according to claim 13, wherein a thickness of the at least one dielectric layer is greater than or equal to 50 m and less than 300 m.

15. The manufacturing method for the circuit board structure according to claim 13, further comprising: forming at least one solder mask layer on the at least one dielectric layer, the at least one solder mask layer has at least one solder mask opening, and the at least one solder mask opening exposes a portion of the at least one build-up metal layer to define at least one pad area.

16. The manufacturing method of the circuit board structure according to claim 12, wherein the step of forming the at least one conductive metal layer in the at least one opening of the at least one dielectric layer comprises: the at least one electroplating metal layer is two electroplating metal layers, and the at least one dielectric layer is two dielectric layers, each of the two dielectric layers has at least one opening, the at least one opening comprises a first opening and a second opening, the first opening exposes the two electroplating metal layers connected to at least one of the dielectric portions, and the second opening exposes the two electroplating metal layers connected to the metal portion; forming two release films on the two dielectric layers, respectively, and the two release films expose portions of the two dielectric layers, respectively, and the first opening and the second opening; filling a conductive paste layer on one of the two dielectric layers exposed by one of the two release films and in the corresponding first opening and the second opening, and on another one of the two dielectric layers exposed by another one of the two release films and in the corresponding first opening, so as to form two conductive metal layers, wherein one of the two conductive metal layers is disposed in the first opening and the second opening of one of the two dielectric layers and is connected to a corresponding one of the two electroplating metal layers, and another one of the two conductive metal layers is disposed in the first opening of another one of the two dielectric layers and connected to another corresponding one of the two electroplating metal layers; and removing the two release films to expose the two dielectric layers.

17. The manufacturing method of the circuit board structure according to claim 16, further comprising: before removing the two release films, filling an electrically insulating and thermally conductive paste layer in the second opening of the another one of the two dielectric layers and connected to the another corresponding one of the two electroplating metal layers.

18. The manufacturing method of the circuit board structure according to claim 11, further comprising: the at least one dielectric portion is a dielectric portion, the at least one metal portion comprises a first metal portion and a second metal portion, and the at least one electroplating metal layer is connected to the first metal portion; laminating the at least one dielectric layer and at least one first copper foil layer thereon on at least one of the first surface and the second surface of the core layer and on the at least one electroplating metal layer; performing a drilling process on the at least one dielectric layer and the at least one first copper foil layer thereon to form the at least one opening, the at least one opening comprises a first opening and a second opening, the first opening exposes a portion of the at least one electroplating metal layer, the second opening exposes a portion of the second metal portion; forming at least one first electroplating seed layer on the at least one first copper foil layer and in the first opening and the second opening; forming at least one first patterned photoresist layer on the at least one first electroplating seed layer, the at least one first patterned photoresist layer exposes a portion of the at least one electroplating seed layer located on the at least one first copper foil layer and the at least one first electroplating seed layer located in the first opening and the second opening; with the at least one first patterned photoresist layer as an electroplating mask, electroplating a first metal material on the at least one first electroplating seed layer exposed by the at least one first patterned photoresist layer; and removing the at least one first patterned photoresist layer to form the at least one conductive metal layer in the first opening and the second opening correspondingly connected to the at least one electroplating metal layer and the second metal portion, and extending to the at least one dielectric layer.

19. The manufacturing method of the circuit board structure according to claim 18, further comprising: laminating at least one build-up dielectric layer and at least one second copper foil layer thereon on the at least one dielectric layer and the at least one conductive metal layer; performing another drilling process on the at least one build-up dielectric layer and the at least one second copper foil layer thereon to form at least one third opening, and the at least one third opening exposes a portion of the at least one conductive metal layer; forming at least one second electroplating seed layer on the at least one second copper foil layer and in the at least one third opening; forming at least one second patterned photoresist layer on the at least one second electroplating seed layer, the at least one second patterned photoresist layer exposes a portion of the at least one second electroplating seed layer located on the at least one second copper foil layer and a portion of the at least one second electroplating seed layer located in the at least one third opening; with the at least one second patterned photoresist layer as an electroplating mask, electroplating a second metal material on the at least one second electroplating seed layer exposed by the at least one second patterned photoresist layer; and removing the at least one second patterned photoresist layer to form at least one build-up metal layer in the at least one third opening, wherein the at least one build-up metal layer is connected to the at least one conductive metal layer and extends to the at least one build-up dielectric layer.

20. The manufacturing method of the circuit board structure according to claim 19, further comprising: forming at least one solder mask layer on the at least one build-up dielectric layer, the at least one solder mask layer has at least one solder mask opening, and the at least one solder mask opening exposes a portion of the at least one build-up metal layer to define at least one pad area.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

[0028] FIG. 1A to FIG. 1O are schematic drawings of a manufacturing method for a circuit board structure according to an embodiment of the disclosure.

[0029] FIG. 2 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the disclosure.

[0030] FIG. 3A to FIG. 3E are schematic cross-sectional views of a manufacturing method for a circuit board structure according to another embodiment of the disclosure.

[0031] FIG. 4A to FIG. 4J are schematic cross-sectional views of a manufacturing method for a circuit board structure according to another embodiment of the disclosure.

DESCRIPTION OF THE EMBODIMENTS

[0032] The embodiments of the disclosure may be understood together with the drawings, and the drawings of the disclosure are also regarded as a part of the disclosure description. It is to be understood that the drawings of the disclosure are not drawn in full scale and, in fact, the dimensions of elements may be arbitrarily increased or reduced in order to clearly illustrate the features of the disclosure.

[0033] FIG. 1A to FIG. 1O are schematic drawings of a manufacturing method for a circuit board structure according to an embodiment of the disclosure. It should be noted that FIG. 1A to FIG. 1D and FIG. 1F to FIG. 1O are schematic cross-sectional views, and FIG. 1E is a schematic top view of FIG. 1D, wherein FIG. 1D is a schematic cross-sectional view along line I-I of FIG. 1E.

[0034] Regarding the manufacturing method of the circuit board shown in the present embodiment, first, referring to FIG. 1A, a copper plate 110a is provided. The copper plate 110a has a first surface S1 and a second surface S2 opposite to each other, wherein the thickness T1 of the copper plate 110a is, for example, greater than or equal to 200 m and less than or equal to 500 m. In one embodiment, the thickness T1 of the copper plate 110a is, for example, 200 m. In another embodiment, the thickness T1 of the copper plate 110a is, for example, 300 m. Here, the copper plate 110a is, for example, rolled copper, and its thickness is significantly smaller than the thick copper plate in the prior art.

[0035] Next, referring to FIG. 1B, a first half etching process is performed on the first surface S1 of the copper plate 110a, and a plurality of first cavities C1 are formed on the first surface S1. The first cavities C1 are separated from each other and do not penetrate the copper plate 110a.

[0036] Next, referring to FIG. 1C, a first dielectric paste G1 is filled in the first cavities C1, wherein the first dielectric paste G1 completely fills the first cavities C1. In one embodiment, the surface of the first dielectric paste G1 may be flush with the first surface S1 of the copper plate 110a. Here, the first dielectric paste G1 is, for example, epoxy resin, but is not limited thereto.

[0037] Next, referring to FIG. 1D, a second half-etching process is performed on the second surface S2 of the copper plate 110a, and a plurality of second cavities C2 in communication with the first cavities C1 is formed on the second surface S2 and defines a metal portion 112, wherein the second cavities C2 exposes the first dielectric paste G1. That is to say, the metal portion 112 is the remaining area of the copper plate 110a on the copper plate 110a after deducting the positions of the first cavities C1 and the second cavities C2. Therefore, the metal portion 112 is a portion of the copper plate 110a.

[0038] Next, referring to FIG. 1D and FIG. 1E, a second dielectric paste G2 is filled in the second cavities C2, wherein the second dielectric paste G2 completely fills the second cavities C2. The second dielectric paste G2 is connected to the first dielectric paste G1 to define a plurality of dielectric portions 114. In one embodiment, the surface of the second dielectric paste G2 may be flush with the second surface S2 of the copper plate 110a. Here, the material of the second dielectric paste G2 may be the same as the material of the first dielectric paste G1. That is, the second dielectric paste G2 is, for example, epoxy resin, but is not limited thereto. So far, the core layer 110a has been provided with the first surface S1 and the second surface S2 opposite to each other, and the plurality of dielectric portions 114, 114a and 114b and a metal portion 112 are included. In one embodiment, the dielectric portion 114a may be, for example, a dielectric hole, and the dielectric portion 114b can be, for example, a dielectric trench, but is not limited thereto.

[0039] Next, referring to FIG. 1F, two electroplating seed layers E1 are respectively formed on the first surface S1 and the second surface S2 of the core layer 110a, which are opposite to each other, wherein the electroplating seed layers E1 covers the first surface S1 and the second surface S2 of the core layer 110a, respectively. Here, the material of the electroplating seed layer E1 may be, for example, titanium/copper or electro-less copper, but is not limited thereto.

[0040] Next, referring to FIG. 1G, two patterned photoresist layers P1 are respectively formed on the two electroplating seed layers E1, wherein the two patterned photoresist layers P1 respectively expose portions of the two electroplating seed layers E1.

[0041] Next, referring to FIG. 1G and FIG. 1H, with two patterned photoresist layers P1 as an electroplating mask, a metal material M1 is electroplated on the electroplating seed layers E1 exposed by the two patterned photoresist layers P1. Here, the metal material M1 may be copper, for example.

[0042] Next, referring to FIG. 1H. The two patterned photoresist layers P1 are removed to expose the first surface S1 and the second surface S2 of the core layer 110a, thereby forming electroplating metal layers 120a disposed on the first surface S1 and the second surface S2 of the core layer 110a and at least connected to the metal portion 112. At this point, electroplating of at least one electroplating metal layer 120a on at least one of the first surface S1 and the second surface S2 of the core layer 110a has been completed.

[0043] Next, referring to FIG. 1I, two dielectric layers 130a and copper foil layers 135a respectively located thereon are laminated together on the first surface S1, the second surface S2, and the two electroplating metal layers 120a of the core layer 110a. In one embodiment, the thickness T2 of each of the dielectric layers 130a is, for example, greater than or equal to 50 m and less than 300 m. Here, the thickness T2 of the dielectric layer 130a is, for example, 150 m.

[0044] Next, referring to FIG. 1J, a drilling process is performed on the two dielectric layers 130a and the copper foil layers 135a respectively located thereon to form at least one opening on each of the two dielectric layers 130a (a plurality of openings 132a is schematically shown in the drawing). The openings 132a expose corresponding portions of the electroplating metal layers 120a. In one embodiment, the openings 132a may be, for example, a cavity, a blind hole, or a combination thereof. In one embodiment, the drilling process is, for example, laser drilling or mechanical drilling, but is not limited thereto.

[0045] Next, referring to FIG. 1J again, two electroplating seed layers E2 are formed on the copper foil layers 135a on the two dielectric layers 130a, respectively, and in the openings 132a. Here, the material of the electroplating seed layers E2 may be, for example, titanium/copper or electro-less copper, but is not limited thereto.

[0046] Next, referring to FIG. 1K again, two patterned photoresist layers P2 (i.e., the first patterned photoresist layers) are respectively formed on the two electroplating seed layers E2. The two patterned photoresist layers P2 expose portions of the electroplating layers 120a in the openings 132a.

[0047] Next, referring to FIG. 1K and FIG. 1L, with the two patterned photoresist layers P2 as the electroplating mask, a metal material M2 (i.e., the first metal material) is electroplated on the electroplating seed layer E2 exposed by the two patterned photoresist layers P2. Here, the metal material M2 may be copper, for example.

[0048] Next, referring to FIG. 1K and FIG. 1L, the two patterned photoresist layers P2 are removed to expose the two electroplating seed layers E2, wherein the surface of the metal material M2 is flush with the surfaces of the two electroplating seed layers E2.

[0049] Next, referring to FIG. 1M, two patterned photoresist layers P3 (i.e., the second patterned photoresist layers) are respectively formed on the two electroplating seed layers E2. The two patterned photoresist layers P3 expose the metal material M2 and portions of the two electroplating seed layer E2.

[0050] Next, referring to FIG. 1M and FIG. 1N, with the two patterned photoresist layers P3 as an electroplating mask, a metal material M3 (i.e., the second metal material) is electroplated on the metal material M2 and two electroplating seed layers E2 exposed by the two patterned photoresist layers P3. Here, the metal material M3 may be copper, for example.

[0051] After that, referring to FIG. 1M and FIG. 1N, the two patterned photoresist layers P3, the two electroplating seed layers E2 and the copper foil layers 135a thereunder are removed, and the two dielectric layers 130a are exposed to form two build-up metal layers 150a and the two conductive metal layers 140a located in the openings 132a of the two dielectric layers 130a and connected to the build-up metal layers 150a. That is, the two conductive metal layers 140a and the two build-up metal layers 150a are electroplating layers. So far, two conductive metal layers 140a have been formed in the openings 132a of the two dielectric layers 130a, respectively, and the two conductive metal layers 140a are respectively connected to the two electroplating metal layers 120a.

[0052] Finally, referring to FIG. 1O, two solder mask layers 160a are formed on the two dielectric layers 130a, respectively. Each of the solder mask layers 160a has at least one solder mask opening (a plurality of solder mask openings 162a is schematically showing in the drawing), and the solder mask openings 162a expose portions of the build-up metal layers 150a to define at least one pad area (a plurality of pad areas A11, A12, and A13 are schematically shown in the drawing). The pad areas A11 and A12, for example, are areas that may carry larger currents, and the pad area A13 is an area that may carry smaller currents, such as a signal pad. At this point, the process of manufacturing the circuit board structure 100a has been completed.

[0053] With regard to its structure, referring to FIG. 1O again, the circuit board structure 100a shown in the present embodiment includes the core layer 110a, the two electroplating metal layers 120a, the two dielectric layers 130a and the two conductive metal layers 140a. The core layer 110a has the first surface S1 and the second surface S2 opposite to each other, and includes the metal portion 112 and the plurality of dielectric portions 114. The two electroplating metal layers 120a are respectively disposed on the first surface S1 and the second surface S2 of the core layer 110, exposes a portion of the first surface S1 and a portion of the second surface S1, and is at least connected with the metal portion 112. The two dielectric layers 130a are respectively disposed on the first surface S1, the second surface S2 and the two electroplating metal layers 120a of the core layer 110a. Each of the dielectric layers 130a has the at least one opening (the plurality of openings 132a is schematically shown in the drawing), and the openings 132a expose corresponding portions of the electroplating metal layers 120a. The two conductive metal layers 140a are respectively disposed in the openings 132a of the two dielectric layers 130a, and are correspondingly connected to the two electroplating metal layers 120a.

[0054] In addition, the circuit board structure 100a shown in the present embodiment also includes the two build-up metal layers 150a and the two solder mask layers 160a. The two build-up metal layers 150a are respectively disposed on the two conductive metal layers 140a. The two solder mask layers 160a are respectively disposed on the two dielectric layers 130a. Each of the solder mask layers 160a has at least one solder mask opening (the plurality of solder mask openings 162a are schematically showed in the drawing), and the solder mask openings 162a expose portions of the build-up metal layer 150a to define the pad areas A11, A12, and A13. In the present embodiment, the material of the metal portion 112, the material of the electroplating metal layers 120a, and the material of the conductive metal layers 140a are, for example, copper. Through rapid electroplating, the electroplating metal layers 120a are connected to the metal portion 112 of the core layer 110a, and the conductive metal layers 140a are connected to the electroplating metal layers 120a, thereby forming a metal region with a certain thickness, in other words, forming a thick copper circuit board structure that may carry large currents, and having better process efficiency.

[0055] Furthermore, in the present embodiment, the core layer 110a is formed by half-etching the copper plate 110a. The thickness T1 of the core layer 110a is greater than or equal to 200 m and less than or equal to 500 m, thereby avoiding too much copper material used. The thickness T2 of the dielectric layer 130a is, for example, 50 m or more and less than 300 m. In addition, since the circuit board structure 100a of this embodiment forms the electroplating metal layers 120a, the conductive metal layers 140a and build-up metal layers 150a on the core layer 110a by rapid electroplating, time-consuming mechanical processing can be eliminated.

[0056] Other embodiments will be described below for further illustration. The following embodiments adopt the reference numerals and part of the content of the previous embodiment, wherein the same reference numerals are used to represent the same or similar elements and descriptions of the same technical content are omitted. The omitted portions are as described in the embodiment above and are not repeated in the embodiments below.

[0057] FIG. 2 is a schematic cross-sectional view of a circuit board structure according to an embodiment of the disclosure. Referring to FIG. 1O and FIG. 2, the circuit board structure 100b shown in the present embodiment is similar to the circuit board structure 100a in FIG. 1O, and a main difference between the two embodiments is that in the present embodiment, the electroplating metal layer 120a, the conductive metal layer 140a and the build-up metal layer 150a of the circuit board structure 100b are disposed only on the first surface S1 of the core layer 110a. That is, the numbers of the electroplating metal layer 120a, the conductive metal layer 140a and the build-up metal layer 150a are one, which means that the circuit board structure 100b is a single-sided circuit board. The dielectric layer 130b directly covers the second surface S2 of the core layer 110a, and the solder mask layer 160b covers the dielectric layer 130b to avoid warping caused by unbalanced structures on opposite sides of the core layer 110a.

[0058] FIG. 3A to FIG. 3E are schematic cross-sectional views of a manufacturing method for a circuit board structure according to another embodiment of the disclosure. The manufacturing method of the circuit board structure in the present embodiment is similar to the manufacturing method of the circuit board structure mentioned above, and a main difference between the two embodiments is that after the step shown in FIG. 1H, that is, after the electroplating metal layers 120a are electroplated on the first surface S1 and the second surface S2 of the core layer 110a, referring to FIG. 3A, two dielectric layers 130c are laminated on the first surface S1, the second surface S2 and the two electroplating metal layers 120a of the core layer 110a. The thickness T3 of each of the dielectric layers 130c is, for example, greater than or equal to 50 m and less than 300 m. Here, the thickness T3 of the dielectric layer 130c is, for example, 150 m.

[0059] Next, referring to FIG. 3B, a drilling process is performed on the two dielectric layers 130c to form at least one opening on the two dielectric layers 130c, respectively. The at least one opening includes first openings 132c and second openings 134c. The first openings 132c expose two electroplating metal layers 120a connected to the at least one dielectric portion 114 and/or the metal portion 112, and the second openings 134c exposes two electroplating metal layers 120a connected to the metal portion 112. In one embodiment, the drilling process is, for example, laser drilling or mechanical drilling, but is not limited thereto. In one embodiment, the first openings 132c may be, for example, a blind hole, and the second openings 134c may be, for example, a cavity.

[0060] Next, referring to FIG. 3C, two release films R are formed on the two dielectric layers 130c, respectively. The two release films R expose portions of the two dielectric layers 130c, respectively, and the first openings 132c and the second openings 134c.

[0061] Next, referring to FIG. 3C and FIG. 3D, a conductive paste layer B is filled on one of the two dielectric layers 130c exposed by one of the two release films R and the corresponding first openings 132c and the second opening 134c, and on the other of the two dielectric layers 130c exposed by the other of the two release films R and in the corresponding first opening 132c, to form two conductive metal layers 140c. Further, one of the two conductive metal layers 140c (such as the conductive metal layer 140c located above the core layer 110a) is disposed in the first openings 132c of one of the two dielectric layers 130c (such as the dielectric layer 130c located above the core layer 110a) and in the second opening 134c, and is connected to the corresponding one of the two electroplating metal layers 120a (such as the electroplating metal layer 120a located above the core layer 110a). The other of the two conductive metal layers 140c (such as the conductive metal layer 140c located below the core layer 110a) is disposed in the first opening 132c of the other of the two dielectric layers 130c (such as the dielectric layer 130c located below the core layer 110a) and is connected to the other corresponding one of the two electroplating metal layers 120a (such as the electroplating metal layer 120a located below the core layer 110a). Here, the material of the conductive paste layer B is, for example, copper paste, silver paste, solder paste or composite metal paste, wherein the thermal conductivity of the conductive paste layer B may be greater than or higher than the thermal conductivity of copper or aluminum.

[0062] Next, referring to FIG. 3D, an electrically insulating and thermally conductive paste H is filled into the second opening 134c of the other of the two dielectric layers 130c (such as the dielectric layer 130c located below the core layer 110a) and is connected with the other corresponding one of the two electroplating metal layers 120a (such as the electroplating metal layer 120a located below the core layer 110a) to form an electrically insulating and thermally conductive paste layer 150c. Here, the material of the electrically insulating and thermally conductive paste H is, for example, a composite of diamond powder, ceramic powder (Al.sub.2O.sub.3, AlN, etc.) and epoxy resin.

[0063] After that, referring to FIG. 3C and FIG. 3D, the two release films R are removed to expose the two dielectric layers 130c, respectively.

[0064] Finally, referring to FIG. 3E, two solder mask layers 160c are formed on the two dielectric layers 130c, respectively. Each of the solder mask layers 160c has at least one solder mask opening (a plurality of solder mask openings 162c is schematically showed in the drawing), and the solder mask openings 162c expose portions of the conductive metal layers 140c and a portion of the electrically insulating and thermally conductive paste layer H to define at least one pad area (a plurality of pad areas A31, A32, and A33 is schematically showed in the drawing). The pad area A31 is, for example, an area that may carry larger currents, the pad area A32 is, for example, a heat dissipation pad, and the pad area A33 is, for example, an area that may carry smaller currents, such as a signal pad. At this point, the process of manufacturing the circuit board structure 100c has been completed.

[0065] With regard to its structure, referring to FIG. 1O and FIG. 3E, the circuit board structure 100c in the present embodiment is similar to the circuit board structure 100a in FIG. 1O, and a main difference between the two embodiments is that the conductive metal layer 140c in the present embodiment is specifically a conductive paste layer, and that is, the conductive metal layer 140c is formed by filling with conductive paste. In addition, the circuit board structure 100c in the present embodiment also includes the electrically insulating and thermally conductive paste layer 150c, which is disposed in the second opening 134c of the other of the two dielectric layers 130c (such as the dielectric layer 130c located below the core layer 110a) and connected with the other corresponding one of the two electroplating metal layers 120a (such as the electroplating metal layer 120a located below the core layer 110a). In short, the circuit board structure 100c in the present embodiment not only serves as a thick copper circuit board that may carry large currents but also has an effect of heat dissipation.

[0066] FIG. 4A to FIG. 4J are schematic cross-sectional views of a manufacturing method for a circuit board structure according to another embodiment of the disclosure. First, referring to FIG. 4A, a core layer 110d is provided. The core layer 110d has a first surface S1 and a second surface S2 opposite to each other, and includes a dielectric portion 115, a first metal portion 117 and at least one second metal portion 119 (two second metal portions 119 are schematically shown in the drawings).

[0067] In one embodiment, the core layer 110d may be made of a copper foil substrate, wherein the dielectric portion 115 is, for example, a portion of the core dielectric layer of the copper foil substrate, the thickness of the core dielectric layer is, for example, 200 m or 300 m, but is not limited thereto. Then, a drilling process may be performed on the copper foil substrate, and holes may penetrate the upper copper foil and the core dielectric layer to expose the lower copper foil layer. Next, an electroplating seed layer is formed, a patterned photoresist layer is formed, and an electroplating process is performed, so that the first metal portion 117 and the second metal portions 119 are electroplated in the holes.

[0068] Next, referring to FIG. 4A again, two electroplating metal layers 120d are formed on the first surface S1 and the second surface S2 of the core layer 110d, wherein two of the electroplating metal layers 120d may be connected to opposite sides of the same first metal portion 117, respectively.

[0069] Next, referring to FIG. 4B, two dielectric layers 130d and two first copper foil layers 135d respectively located thereon are laminated on the first surface S1 and the second surface S2 of the core layer 110d and on the two electroplating metal layers 120d. The thickness T4 of the dielectric layers 130d is, for example, 50 m or more and less than 300 m. Here, the thickness T4 of the dielectric layers 130d is, for example, 100 m.

[0070] Next, referring to FIG. 4C, a drilling process is performed on the two dielectric layers 130d and the two copper foil layers 135d (i.e., the first copper foil layers) thereon to form at least one opening. The at least one opening includes first openings 132d and second openings 134d. The first openings 132d expose portions of at least one electroplating metal layer 120d. The second openings 134d expose portions of the second metal portions 119.

[0071] Next, referring to FIG. 4C again, two electroplating seed layers E3 (i.e., the first electroplating seed layers) are formed on the two copper foil layers 135d, respectively, and in the first openings 132d and in the second openings 134d.

[0072] Next, referring to FIG. 4D again, two patterned photoresist layers P4 (i.e., the first patterned photoresist layers) are formed on the two electroplating seed layers E3, respectively. The two patterned photoresist layers P4 expose portions of the two electroplating seed layers E3 located on the two copper foil layers 135d and portions of the two electroplating seed layers E3 located in the first openings 132d and the second openings 134d.

[0073] Next, referring to FIG. 4D and FIG. 4E, with the two patterned photoresist layers P4 as an electroplating mask, a metal material M4 (i.e., the first metal material) is electroplated on the two electroplating seed layers E3 exposed by the two patterned photoresist layers P4.

[0074] Next, referring to FIG. 4D and FIG. 4E, the two patterned photoresist layers P4 are removed to form two conductive metal layers 140d in the first openings 132d and the second openings 134d, correspondingly connected with the two electroplating metal layers 120d and the second metal portions 119, and extending to the two dielectric layers 130d.

[0075] Next, referring to FIG. 4F, two build-up dielectric layers 170d and two copper foil layers 175d (i.e., the second copper foil layers) respectively located thereon are laminated on the two dielectric layers 130d and the two conductive metal layers 140d. The two build-up dielectric layers 170d cover the two dielectric layers 130d and the two conductive metal layers 140d. The thickness T5 of the build-up dielectric layers 170d is, for example, 50 m or more and less than 300 m. Here, the thickness T5 of the build-up dielectric layers 170d is, for example, 150 m.

[0076] Next, referring to FIG. 4G, another drilling process is performed on the two build-up dielectric layers 170d and the two copper foil layers 175d respectively located thereon to form at least one third opening (a plurality of third openings 172d are schematically shown in the drawing). The third openings 172d expose portions of the two conductive metal layers 140d.

[0077] Next, referring to FIG. 4G again, two electroplating seed layers E4 (i.e., the second electroplating seed layers) are formed on the two copper foil layers 175d and in the third openings 172d.

[0078] Next, referring to FIG. 4H, two patterned photoresist layers P5 (i.e., the second patterned photoresist layers) are formed on the two electroplating seed layers E4. The two patterned photoresist layers P5 expose portions of the two electroplating seed layers E4 located on the two copper foil layers 175d and portions of the two electroplating seed layers E4 located in the third openings 172d.

[0079] Next, referring to FIG. 4H and FIG. 4I, with the two patterned photoresist layers P5 as the electroplating mask, a metal material M5 (i.e., the second metal material) is electroplated on the two electroplating seed layers E4 exposed by the two patterned photoresist layers P5.

[0080] After that, referring to FIG. 4H and FIG. 4I, the two patterned photoresist layers P5 are removed to form two build-up metal layers 150d in the third openings 172d. The two build-up metal layers 150d are connected to the two conductive metal layers 140d and extend to the two build-up dielectric layers 170d.

[0081] Finally, referring to FIG. 4J, two solder mask layers 160d are formed on the two build-up dielectric layers 170d. Each of the solder mask layers 160d has at least one solder mask opening (a plurality of solder mask openings 162d is schematically shown in the drawing), and the solder mask openings 162d expose portions of the build-up metal layers 150d to define at least one pad area (a plurality of pad areas A41, A42, and A43 are schematically shown in the drawing). At this point, the process of manufacturing the circuit board structure 100d has been completed. With regard to its structure, referring to FIG. 1O and FIG. 4J, the circuit board structure 100d in the present embodiment is similar to the circuit board structure 100a in FIG. 1O, and a main difference between the two embodiments is that the core layer 110d in the present embodiment is made of a copper foil substrate, and the metal portion is formed by electroplating. Therefore, the core layer 110d includes one dielectric portion 115 and a plurality of metal portions (i.e., the first metal portion 117 and the second metal portions 119).

[0082] In the present embodiment, the material of the first metal portion 117 and the second metal portions 119, the material of the electroplating metal layers 120d, the material of the conductive metal layers 140d, and the material of the build-up metal layers 150d may be, for example, copper. Through rapid electroplating, the electroplating metal layers 120d are connected to the first metal portion 117 of the core layer 110d (referring to FIG. 4E), and the conductive metal layers 140d are connected to the electroplating metal layers 120d and the second metal portions 119 (referring to FIG. 4E)), and the build-up metal layers 150d are connected to the conductive metal layers 140d (referring to FIG. 4J), thereby forming a metal area with a certain thickness, that is, forming a thick copper circuit board structure that may carry large currents, and having better process efficiency.

[0083] In summary, in the design of the circuit board structure of the disclosure, the electroplating metal layers are connected to the metal portion of the core layer, and the conductive metal layers are connected to the electroplating metal layers through the openings of the dielectric layers, thereby forming a metal area with a certain thickness that may carry large currents. In addition, since the circuit board structure of the disclosure forms the electroplating metal layers on the core layer through electroplating, time-consuming mechanical processing may be eliminated, and it is also feasible to manufacture only a single-sided circuit.

[0084] Although the disclosure has been described with reference to the above embodiments, the embodiments are not intended to limit the disclosure. A person of ordinary skill in the art may make variations and modifications without departing from the spirit and scope of the disclosure. Therefore, the protection scope of the disclosure should be subject to the appended claims.