Electrostatic Discharge protection semiconductor structure and a method of manufacture

Abstract

A discharge protection semiconductor structure is provided that includes a substrate, a well positioned on the substrate, a first contact diffusion and a second contact diffusion, the first contact diffusion and the second contact diffusion positioned on the top side of the well, and a resistor positioned between the first contact diffusion and a second contact diffusion.

Claims

1. A discharge protection semiconductor structure comprising: a substrate; a well of a first polarity positioned on the substrate; a resistor of a second polarity embedded in the well, the second polarity being inversed in respect to the first polarity, the resistor having a top surface and a bottom surface; and a first contact diffusion of the second polarity and a second contact diffusion of the second polarity, the resistor being positioned between the first contact diffusion and the second contact diffusion, a top surface of the first contact diffusion and a top surface of the second contact diffusion being coplanar with the top surface of the resistor, and a bottom surface of the first contact diffusion and a bottom surface of the second contact diffusion being below the bottom surface of the resistor; wherein doping of the well, doping of the resistor, and doping of the first contact diffusion and second contact diffusion are of a similar level.

2. The discharge protection semiconductor structure as claimed in claim 1, further comprising: the first contact diffusion and the second contact diffusion is positioned on a top side of the well.

3. The discharge protection semiconductor structure as claimed in claim 2, wherein the first contact diffusion and the second contact diffusion protrude into the well.

4. The discharge protection semiconductor structure as claimed in claim 2, wherein the first contact diffusion and the second contact diffusion protrude into the substrate below the well.

5. The discharge protection semiconductor structure as claimed in claim 1, wherein the well is p-doped, and wherein the resistor is n-doped.

6. The discharge protection semiconductor structure as claimed in claim 1, wherein the well is n-doped, and wherein the resistor is p-doped.

7. The discharge protection semiconductor structure as claimed in claim 1, wherein the resistor has a length that is in a range between 0.2 m and 2 m.

8. The discharge protection semiconductor structure as claimed in claim 1, wherein the resistor has a width that is in a range between 0.05 mm and 20 mm.

9. The discharge protection semiconductor structure as claimed in claim 1, wherein the resistor is doped in a range of 10e17 to 10e19, and wherein the resistor is of a thickness in a range of 0.01 m to 0.5 m.

10. The discharge protection structure as claimed in claim 1, wherein the resistor has a resistance between 0.2 and 10 Ohm for a mA current level.

11. The discharge protection semiconductor structure as claimed in claim 2, wherein the first contact diffusion and the second contact diffusion together with the well form a bipolar transistor with a floating base.

12. The discharge protection semiconductor structure as claimed in claim 11, wherein the bipolar transistor has a breakdown voltage comparable to a breakdown voltage of the resistor.

13. The discharge protection structure as claimed in claim 1, wherein the resistor is formed as a multi-finger arrangement.

14. The discharge protection structure as claimed in claim 2, wherein the resistor is formed as a multi-finger arrangement.

15. An integrated circuit comprising the discharge protection semiconductor structure as claimed in claim 1.

16. An integrated circuit comprising the discharge protection semiconductor structure as claimed in claim 2.

17. A method of creating a discharge protection semiconductor structure semiconductor as claimed in claim 1.

18. A method of creating a discharge protection semiconductor structure semiconductor as claimed in claim 2.

19. A two-stage protection system comprising: a first protection stage; a second protection stage connected between a signal line and a supply line; and a resistor positioned in the signal line between the first protection stage and the second protection stage, the resistor being positioned between a first contact diffusion and a second contact diffusion, the resistor being embedded in a well positioned on a substrate, the resistor having a top surface and a bottom surface, a top surface of the first contact diffusion and a top surface of the second contact diffusion being coplanar with the top surface of the resistor, and a bottom surface of the first contact diffusion and a bottom surface of the second contact diffusion being below the bottom surface of the resistor, wherein the well is of a first polarity, the resistor is of a second polarity, the second polarity being inversed in respect to the first polarity, and wherein doping of the well, doping of the first contact diffusion and the second contact diffusion, and doping of the resistor are of a similar level.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) So that the manner in which the features of the present disclosure can be understood in detail, a more particular description is made with reference to embodiments, some of which are illustrated in the appended figures. It is to be noted, however, that the appended figures illustrate only typical embodiments and are therefore not to be considered limiting of its scope. The figures are for facilitating an understanding of the disclosure and thus are not necessarily drawn to scale. Advantages of the subject matter claimed will become apparent to those skilled in the art upon reading this description in conjunction with the accompanying figures, in which like reference numerals have been used to designate like elements, and in which:

(2) FIGS. 1a, 1b and 1c show I/V diagrams for the known diffusion resistors shown presented on ESD Symposium 2019, by Worley.

(3) FIG. 2 illustrates a diagram related to an embodiment of the disclosure.

(4) FIG. 3A illustrates an embodiment of the disclosure.

(5) FIG. 3B illustrates and embodiment of the disclosure.

(6) FIG. 4 illustrates an embodiment of the disclosure.

(7) FIG. 5 illustrates an embodiment of the disclosure.

(8) FIG. 6 illustrates an embodiment of the disclosure with a two-stage protection system.

DETAILED DESCRIPTION

(9) An embodiment of this disclosure relates to a nonlinear resistor based on velocity saturation, having a low resistance value for signal transmission current levels and a high resistance for ESD current levels. The nonlinear resistor is realised with a thin and highly doped diffusion embedded in a thicker and similarly highly doped well with different doping.

(10) A diffusion resistor according to the disclosure has no snap-back. The resistor will be robust for high current densities because the filamentation will not occur. This is achieved with a resistor formed by a short, thin and highly doped layer embedded in a well of comparable doping level but with different polarity.

(11) According to an embodiment of the disclosure, suitable implants are used to form a very thin diffusion layer, in a range of 0.1 m, with a relatively high doping level, in a range of 10e18. A corresponding resistive layer is sandwiched between the surface of the silicon, which is covered with oxide, and a similarly highly doped well with different polarity.

(12) FIG. 2 shows the doping level when a boron is used 20, when a phosphorous doping is used 22 and absolute doping is used 24 showing junction at 0.1 m.

(13) An embodiment of the disclosure is shown in FIGS. 3A-3B. In this embodiment a resistor 34 is contacted by two contact diffusions, a first contact diffusion 30 and a second contact diffusion 32. The length of the resistor 38, i.e. the distance between said contact diffusions is in a range of 1 to 2 m. The total width of the resistor 40 is the parameter that defines the final resistance value. The total width of the resistor is in a range of 0.5 mm to 3 mm.

(14) The resistor is best formed in a multi-finger arrangement. This is illustrated in FIG. 4. In such an arrangement current can flow from both sides of the contacts, effectively doubling the width of the resistor. The first contact diffusion 30 and the second contact diffusion 32 are positioned on the well 36. The well is positioned on a substrate 60.

(15) In an embodiment of this disclosure, the first contact diffusion 30 and the second contact diffusion 32 are p-doped, the resistor 34 is p-doped, the well 36 is n doped and the substrate 60 is p-doped. The scope of the disclosure includes also an opposite doping arrangement, i.e. the first contact diffusion 30 and the second contact diffusion 32 are n-doped, the resistor 34 is n-doped, the well 36 is p doped and the substrate 60 is n-doped.

(16) The contact diffusions 30 and 32 together with a well 36 form a bipolar transistor with floating base 52.

(17) This transistor 52 is in parallel to the resistor 50. A breakdown voltage of the transistor is comparable to, or it is slightly smaller than a breakdown voltage of the resistor. This is shown in FIG. 5.

(18) In another embodiment of the disclosure contacts are embedded within the resistive layer. The contacts can be made so that the contact diffusions are shallower than the resistive diffusion or the contacts can be made with salicidation.

(19) Such a combination of a very thin two contact diffusion layers 30 and 32 and an underlying well 36 of a similar high doping level provides very good ESD protection.

(20) Another advantageous feature of this embodiment of the disclosure is that the contact diffusion of the resistor forms a bipolar transistor with the underlying well whose breakdown voltage is similar to the breakdown voltage of the resistive layer. Contact diffusions 30 and 32 can be confined within the well 36.

(21) When avalanche within the resistive layer starts at high enough voltages, minority carriers are injected into the resistive layer. These minority carriers cause snap back. This embodiment of the disclosure secures that most of the minority carriers do not stay within the resistive layer but get caught by the well below because the resistive layer is so thin. The lower well has a low resistance due to its high doping. Therefore, the trapped minorities can efficiently be drained away to one of the contacts.

(22) Due to the effective trapping of minorities the snap back is smaller, which causes that the snap-back-voltage is higher.

(23) Moreover, the contact diffusions together with the underlying well form a symmetrical bipolar junction transistor. If the breakdown voltage of this bipolar junction transistor is smaller than or comparable to the breakdown voltage of the resistor then the condition for avalanche within the resistor cannot be reached. In this way it is secured that there is no avalanche and no snap back.

(24) The above described embodiments, i.e. the transient current suppressor, of the disclosure can be used within a signal line on a board. The transient current suppressor is placed between an outside connector, i.e. a socket, and the data-handling-integrated circuit.

(25) Together with an additional on-board protection device placed between the transient current suppressor and the external socket the total system robustness is further improved. This arrangement presents a two stage protection system as shown in FIG. 6. The two-stage protection system comprises a first protection stage 100 and a second protection stage 102. The first protection stage 100 and second protection stage 102 are connected between a signal line 106 and a supply line. The two-stage protection system further comprises a resistor 104 positioned within the signal line 106 between the first protection stage 100 and the second protection stage 102.

(26) The first protection stage 100 can be for example an on-board protection device or any other suitable device. The second protection stage 102 can be for example an internal electrostatic discharge protection structure in an integrated circuit or any other suitable device. A stress current is divided between a current through the first protection stage 100 and a current through the second protection stage 102. The internal protection structure of the IC can only survive a certain stress current. Therefore, the current through the second protection stage has to be minimized. The current through the second protection stage depends on the voltage drop across a resistor 104: the higher the voltage drop across the resistor the smaller the current through the second protection stage. A resistor according to the disclosure will present a large resistance value for a stress current and will therefore reduce the current through the second protection stage. For a given robustness of the second protection stage a larger stress can be applied when a resistor according to the disclosure is placed between the first protection stage and the second protection stage. This significantly improves the robustness of the system.

(27) Particular and preferred aspects of the disclosure are set out in the accompanying independent claims. Combinations of features from the dependent and/or independent claims may be combined as appropriate and not merely as set out in the claims.

(28) The scope of the present disclosure includes any novel feature or combination of features disclosed therein either explicitly or implicitly or any generalisation thereof irrespective of whether or not it relates to the claimed disclosure or mitigate against any or all of the problems addressed by the present disclosure. The applicant hereby gives notice that new claims may be formulated to such features during prosecution of this application or of any such further application derived therefrom. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in specific combinations enumerated in the claims.

(29) Features which are described in the context of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable sub combination.

(30) The term comprising does not exclude other elements or steps, the term a or an does not exclude a plurality. Reference signs in the claims shall not be construed as limiting the scope of the claims.