Method of manufacturing merged PiN Schottky (MPS) diode

Abstract

A merged PiN Schottky (MPS) diode includes a substrate, a first epitaxial layer of a first conductivity type, doped regions of a second conductivity type, a second epitaxial layer of the first conductivity type, and a Schottky metal layer. The first epitaxial layer is disposed on the first surface of the substrate. The doped regions are disposed in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions, the first portions are electrically floating, and the second portions are electrically connected to a top metal. The second epitaxial layer is disposed on the surface of the first epitaxial layer, wherein trenches are formed in the second epitaxial layer to expose the second portions of the doped regions. The Schottky metal layer is conformally deposited on the second epitaxial layer and the exposed second portions of the doped regions.

Claims

1. A method of manufacturing a merged PiN Schottky (MPS) diode, comprising: forming a first epitaxial layer of a first conductivity type on a first surface of a substrate; forming a plurality of doped regions of a second conductivity type in a surface of the first epitaxial layer, wherein the doped regions consist of first portions and second portions; forming a second epitaxial layer of the first conductivity type on the surface of the first epitaxial layer; forming a plurality of trenches in the second epitaxial layer to expose the second portions of the doped regions; and conformally depositing a Schottky metal layer on the second epitaxial layer and the second portions of the doped regions, wherein the first portions are electrically floating, and the second portions are electrically connected to a top metal.

2. The method of manufacturing the MPS diode of claim 1, wherein the first portions and the second portions are alternately arranged along a direction perpendicular to an extension direction of the trenches.

3. The method of manufacturing the MPS diode of claim 1, wherein a doping concentration of the second epitaxial layer is equal to or higher than that of the first epitaxial layer.

4. The method of manufacturing the MPS diode of claim 1, wherein a doping concentration of the second epitaxial layer is 1.2 times to 3 times that of the first epitaxial layer.

5. The method of manufacturing the MPS diode of claim 1, wherein after conformally depositing the Schottky metal layer, further comprising forming the top metal layer on the Schottky metal layer to fill the trenches.

6. The method of manufacturing the MPS diode of claim 5, wherein after forming the top metal layer, further comprising forming a backside metal disposed on a second surface of the substrate, and the second surface is opposite to the first surface.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The accompanying drawings are included to provide a further understanding of the disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the disclosure and, together with the description, serve to explain the principles of the disclosure.

(2) FIG. 1A is a cross-sectional view of a merged PiN Schottky (MPS) diode according to an embodiment of the disclosure.

(3) FIG. 1B is a plane view of the merged PiN Schottky diode of FIG. 1A.

(4) FIGS. 2A to 2F are cross-sectional views illustrating steps of a method of manufacturing a merged PiN Schottky diode according to another embodiment of the disclosure.

(5) FIG. 3 is a cross-sectional view showing the PN junction area ratio in Simulation Examples 1-2.

(6) FIG. 4 is a cross-sectional view showing the PN junction area ratio in Comparative Simulation Examples 1-2.

DESCRIPTION OF THE EMBODIMENTS

(7) With reference to the drawings attached, the disclosure will be described by means of the embodiments below. Nevertheless, the disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In the drawings, for the purpose of clarity and specificity, the sizes and the relative sizes of each layer and region may not be illustrated in accurate proportion.

(8) FIG. 1A is a cross-sectional view of a merged PiN Schottky diode according to an embodiment of the disclosure.

(9) Referring to FIG. 1A, the merged PIN Schottky diode 10 of the embodiment includes at least a substrate 100, a first epitaxial layer 102 of a first conductivity type, doped regions 104 of a second conductivity type, a second epitaxial layer 106 of the first conductivity type, and a Schottky metal layer 108. In one embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. In another embodiment, the first conductivity type is p-type, and the second conductivity type is n-type. The substrate 100 may be a high doping wideband semiconductor substrate such as a silicon carbide (SiC) substrate of the first conductivity type with a doping concentration of 1E18/cm.sup.3 to 2E20/cm.sup.3. The first epitaxial layer 102 is disposed on the first surface 100a of the substrate 100, wherein a thickness of the first epitaxial layer 102 is, for instance, 4 m to 15 m, and a doping concentration of the first epitaxial layer 102 is, for instance, 2E15/cm.sup.3 to 1E17/cm.sup.3.

(10) The doped regions 104 are disposed on a surface 102a of the first epitaxial layer 102, wherein the doped regions 104 consist of first portions 110.sub.1 and second portions 110.sub.2, the first portions 110.sub.1 are electrically floating, and the second portions 110.sub.2 are electrically connected (and biased) to a top metal 114. The so-called floating refers to a part of the body that is not connected to another part of the body, and thus electrically floating refers to the portions are not electrically connected to other portions, conductive layers, wires, interconnection, etc. The top metal 114 is formed on the Schottky metal layer 108. The floating first portions 110.sub.1 can prevent the electric field from the substrate 100 from flowing into the second epitaxial layer 106. That is, the first portions 110.sub.1 can pinch off the electrical field, and accordingly, the current leakage can be reduced by the floating doped regions even if the Schottky contact area becomes larger. Moreover, since the locations of the first portions 110.sub.1 do not occur depletion region, there is no potential difference at the first portions 110.sub.1 so as to improve the current density therein, thereby improving the forward voltage V.sub.F characteristics.

(11) The second epitaxial layer 106 is disposed on the surface 102a of the first epitaxial layer 102, wherein a thickness of the second epitaxial layer 106 is, for instance, 0.3 m to 2 m, and a doping concentration of the second epitaxial layer 106 is equal to or higher than that of the first epitaxial layer 102. In one embodiment, the doping concentration of the second epitaxial layer 106 is light higher than that of the first epitaxial layer 102 to obtain high enough reverse blocking voltage for the lower drift layer (i.e. the first epitaxial layer 102), while the higher doping concentration in drift layer (i.e. the second epitaxial layer 106) can lower Schottky barrier height of the Schottky contacts that results in lower V.sub.F of the disclosure. For example, the doping concentration of the second epitaxial layer 106 is 1.2 times to 3 times that of the first epitaxial layer 102. The doping concentration of the second epitaxial layer 106 is, for instance, 2.5E15/cm.sup.3 to 2E17/cm.

(12) In the second epitaxial layer 106, trenches 112 are formed to expose the second portions 110.sub.2 of the doped regions 104, and the trenches 112 are normally parallel each other. The width W of each of the second portions 110.sub.2 of the doped regions 104 is, for instance, 0.3 m to 2 m, which depends on the manufacturing technology. The spacing S between the first portion 110.sub.1 and the second portion 110.sub.2 is, for instance, 0.3 m to 3 m, which is the function of the doping concentration of the first epitaxial layer 102. In case the doping concentration of the first epitaxial layer 102 is 2E16/cm.sup.3, the spacing S is 0.3 m (for 600V device). In case the doping concentration of the first epitaxial layer 102 is 1E15/cm.sup.3, the spacing Sis 3 m (for 3300V device); and so on. As shown in FIG. 1A, the first portions 110.sub.1 and the second portions 110.sub.2 are alternately arranged along a direction perpendicular to an extension direction of the trenches 112; however, the disclosure is not limited thereto. For example, the arrangement of the doped regions 104 may be two second portions 110.sub.2 and one first portion 110.sub.1 alternately arranged, and so on.

(13) FIG. 1B is a plane view of the merged PiN Schottky diode of FIG. 1A, wherein some elements are omitted in FIG. 1B to clarify the positional relationship of the trenches 112, and the first portion 110.sub.1 and the second portion 110.sub.2 of the doped regions 104, and the top metal 114. It is clear that the trenches 112 are directly over the second portions 110.sub.2 of the doped regions 104, and the first portions 110.sub.1 and the second portions 110.sub.2 are alternately arranged along a direction perpendicular to the extension direction of the trenches 112.

(14) Referring to FIG. 1A again, the Schottky metal layer 108 is conformally deposited on the second epitaxial layer 106 and the exposed second portions 110.sub.2 of the doped regions 104. In particular, the Schottky metal layer 108 is on the top of the second epitaxial layer 106, sidewall of the trenches 112 as well as the bottom of the trenches 112, and the Schottky metal layer 108 is electrically connected to the second portions 110.sub.2 of the doped regions 104. The material of the Schottky metal layer 108 comprises a refractory metal silicide or a refractory metal, wherein the refractory metal is, for instance, Ti, Ni, W, or Mo; the refractory metal silicide is, for instance, titanium silicide, nickel silicide, tungsten silicide, or molybdenum silicide. The trenches 112 are filled with the top metal 114, wherein a material of the top metal 114 is, for instance, aluminum or gold. The merged PiN Schottky diode 10 further includes a backside metal 116 disposed on the second surface 100b of the substrate 100, wherein a material of the backside metal 116 is, for instance, metal silicide such as nickel silicide.

(15) FIGS. 2A to 2F are cross-sectional views illustrating a processing flow of manufacturing a merged PiN Schottky diode according to another embodiment of the disclosure, wherein the reference symbols used in above embodiment are used to equally represent the same or similar components. The description of the same components can be derived from above embodiment, and will not be repeated herein.

(16) Referring to FIG. 2A, a first epitaxial layer 102 of a first conductivity type is formed on a first surface 100a of a substrate 100. The substrate 100 may be a high doping wideband semiconductor substrate of the first conductivity type, and the thickness and the doping concentration of first epitaxial layer 102 can refer to above embodiment, and will not be repeated herein. An implant block layer 200 is formed on the surface 102a of the first epitaxial layer 102 and then patterned for subsequent implantation, wherein the implant block layer 200 is, for instance, a SiO.sub.2 layer or a Si.sub.3N.sub.4 layer.

(17) Then, referring to FIG. 2B, doped regions 104 of a second conductivity type is formed in the surface 102a of the first epitaxial layer 102 through an ion implantation 202 of the second conductivity type, wherein the doped regions 104 consist of first portions 110.sub.1 and second portions 110.sub.2. In one embodiment, the first portions 110.sub.1 and the second portions 110.sub.2 are parallel each other; however, the disclosure is not limited thereto. For example, shapes of the first portions 110.sub.1 may be square, circle, or rectangle.

(18) After that, referring to FIG. 2C, the implant block layer 200 is removed, and an anneal is performed to form a PN junction (between the doped regions 104 and the first epitaxial layer 102) at the surface 102a of the first epitaxial layer 102. A second epitaxial layer 106 of the first conductivity type is then formed on the surface 102a of the first epitaxial layer 102, wherein a doping concentration of the second epitaxial layer 106 is equal to or higher than that of the first epitaxial layer 102. In one embodiment, the doping concentration of the second epitaxial layer 106 is 1.2 times to 3 times that of the first epitaxial layer 102.

(19) Thereafter, referring to FIG. 2D, an etch block layer 204 is formed on the second epitaxial layer 106 and then patterned for subsequent etching. Trenches 112 are formed in the second epitaxial layer 106 by using the etch block layer 204 as an etching mask. The trenches 112 expose the second portions 110.sub.2 of the doped regions 104, wherein the first portions 110.sub.1 and the second portions 110.sub.2 are alternately arranged along a direction perpendicular to an extension direction of the trenches 112, and the second portions 110.sub.2 are covered by the second epitaxial layer 106.

(20) Referring to FIG. 2E, a Schottky metal layer 108 is conformally deposited on the second epitaxial layer 106 and the second portions 110.sub.2 of the doped regions 104 to form ohmic contact and Schottky contact at the same time. The first portions 110.sub.1 are electrically floating, and the second portions 110.sub.2 are electrically connected to a top metal 114. The top metal 114 may be formed on the Schottky metal layer 108 to fill the trenches 112.

(21) After that, referring to FIG. 2F, a backside metal 116 may be disposed on a second surface 100b of the substrate 100 followed by back side grinding, wherein the second surface 100b is opposite to the first surface 100a.

(22) The following is simulation experiments to verify the efficacy of the disclosure, but the disclosure is not limited to the description below.

Simulation Example 1

(23) Simulation software: Victory process as well as device simulator of Silvaco software, the complex physical phenomena of device level's behavior can be executed physics-based device simulations to predict and understand device performance. The simulation results are based on the N-type epi with concentration of 2E16/cm.sup.3 of SiC merge PN junction device. The spacing S between the first portion 110.sub.1 and the second portion 110.sub.2 is assumed 0.3 m. The N-type epi concentration of the second epitaxial layer 106 is 4E16/cm.sup.3, while the width W of the second portions 110.sub.2 is also assumed 0.2 m, herein, the width W of the second portions 110.sub.2 is derived from the PN junction area ratio of the Table 1 accordingly.

(24) Please refer to FIG. 3, some elements are omitted in FIG. 3 to clarify the positional relationship among the trenches 112, the Schottky metal layer 108, the first portion 110.sub.1 and the second portion 110.sub.2 of the doped regions 104, and the top metal 114. If the total area of the spacing S is X, and the total area of the buried PN junction is Y, the PN junction area ratio equals to 100%Y/(X+Y). The simulation results of IR leakage with the PN junction area ratio change are shown in Table 1 below.

Comparative Simulation Example 1

(25) The simulation conditions are the same as Simulation Example 1 except for all doped regions being in electrically contact with the Schottky metal layer as shown in FIG. 4. In FIG. 4, some elements are omitted to clarify the positional relationship of the doped regions 104, the Schottky metal layer 108, and the top metal 114. If the total area of the spacing between the doped regions 104 is X, and the total area of the doped regions 104 is Y, the PN junction area ratio equals to 100%Y/(X+Y).

(26) The simulation results of IR leakage with the PN junction area ratio change are also shown in Table 1 below.

(27) TABLE-US-00001 TABLE 1 90% of PN 75% of PN 50% of PN 25% of PN 10% of PN junction junction junction junction junction area ratio area ratio area ratio area ratio area ratio IR leakage Simulation 2.2 A 2.3 A 2.6 A 3.5 A 4.5 A at 600 V Example 1 IR leakage Comparative 2.2 A 6.5 A 14 A 61.6 A 84.2 A at 600 V Simulation Example 1

(28) According to Table 1, the IR leakage of Comparative Simulation Example 1 is significantly greater than that of Simulation Example 1, especially when the PN junction area ratio becomes smaller.

Simulation Example 2

(29) The simulation software is the same as Simulation Example 1, and the simulation results of the Current @V.sub.F=1.5 V with the PN junction area ratio change are shown in Table 2 below.

Comparative Simulation Example 2

(30) The simulation conditions are the same as Simulation Example 2 except for the second portions being electrically connected to a metal line connecting with the first portions via an interconnection.

(31) The simulation results of the Current @V.sub.F=1.5 V with the PN junction area ratio change are also shown in Table 2 below.

(32) TABLE-US-00002 TABLE 2 90% of PN 75% of PN 50% of PN 25% of PN 10% of PN junction junction junction junction junction area ratio area ratio area ratio area ratio area ratio Current Simulation 5.8 A 9.6 A 13 A 17.4 A 21.2 A @V.sub.F = 1.5 V Example 2 Current Comparative 2.7 A 7.0 A 11.2 A 15.5 A 19.8 A @V.sub.F = 1.5 V Simulation Example 2

(33) According to Table 2, the Current @V.sub.F=1.5 V of Comparative Simulation Example 2 is less than that of Simulation Example 2.

(34) In summary, since the merged PiN Schottky diode according to the disclosure has floating doped regions in the drift layer, the current leakage can be reduced even if the Schottky contact area becomes larger, and the forward voltage V.sub.F characteristics can also be improved due to the floating doped regions. Moreover, the doping concentration of the second epitaxial layer can be light higher than that of the first epitaxial layer resulting in further reduction in forward voltage V.sub.F characteristics for the low Schottky barrier height for the higher drift layer.

(35) It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.