Method for Manufacturing Integrated Metal Resistance Layer

Abstract

The present application provides a method for manufacturing an integrated metal resistance layer, comprising: step 1, selecting a formation position of a metal resistance layer, wherein the formation position of the metal resistance layer is located on the surface of an interlayer film inlaid with a copper connection; step 2, completing formation processes of the selected copper connection and the selected interlayer film; step 3, forming the metal resistance layer, comprising the following sub-steps: step 31, depositing a material layer of the metal resistance layer; and step 32, performing patterned etching on the material layer of the metal resistance layer to form the metal resistance layer in the selected region; and step 4, forming a next copper connection and a via at the bottom of the next copper connection, wherein the vias at the bottom of the next copper connection have two different heights.

Claims

1. A method for manufacturing an integrated metal resistance layer, comprising the following steps: step 1, selecting a formation position of a metal resistance layer, wherein the formation position of the metal resistance layer is located on a surface of an interlayer film inlaid with a copper connection in a back end of line process, an interlayer film below the metal resistance layer is a selected interlayer film, a copper connection embedded in the selected interlayer film is a selected copper connection, and the selected copper connection is selected from a first copper connection to a sub-top copper connection; step 2, completing formation processes of the selected copper connection and the selected interlayer film on a semiconductor substrate; step 3, forming the metal resistance layer, comprising the following sub-steps: step 31, depositing a material layer of the metal resistance layer, wherein a resistivity of the material layer of the metal resistance layer is greater than a resistivity of copper; and step 32, performing patterned etching on the material layer of the metal resistance layer to form the metal resistance layer in the selected region, wherein the formation region of the metal resistance layer is located on the surface of the selected interlayer film; and step 4, forming a next copper connection and a via at a bottom of the next copper connection, wherein the vias at the bottom of the next copper connection have two different heights, and a height of the via on the top of the metal resistance layer is less than a height of the via on the top of the selected copper connection.

2. The method for manufacturing the integrated metal resistance layer according to claim 1, wherein the semiconductor substrate provided in step 2 undergoes a front end of line process, a middle of line process, and the back end of line process before formation of the selected copper connection.

3. The method for manufacturing the integrated metal resistance layer according to claim 2, wherein a zeroth interlayer film and a contact plug passing through the zeroth interlayer film are formed in the middle of line process.

4. The method for manufacturing the integrated metal resistance layer according to claim 3, wherein the bottom of the first copper connection is connected to the contact plug.

5. The method for manufacturing the integrated metal resistance layer according to claim 4, wherein the first copper connection is formed by means of a single damascene process.

6. The method for manufacturing the integrated metal resistance layer according to claim 4, wherein each copper connection above the first copper connection and a via at the bottom of the same are formed by means of a dual damascene process.

7. The method for manufacturing the integrated metal resistance layer according to claim 1, wherein in step 31, the material layer of the metal resistance layer comprises a first titanium nitride layer or a second cobalt layer.

8. The method for manufacturing the integrated metal resistance layer according to claim 7, before depositing the material layer of the metal resistance layer in step 31, further comprising a step of depositing a third diffusion barrier layer.

9. The method for manufacturing the integrated metal resistance layer according to claim 8, wherein the third diffusion barrier layer is a carbon-doped silicon nitride layer.

10. The method for manufacturing the integrated metal resistance layer according to claim 8, wherein in step 32, the patterned etching of the material layer of the metal resistance layer stops at the third diffusion barrier layer.

11. The method for manufacturing the integrated metal resistance layer according to claim 7, after depositing the material layer of the metal resistance layer in step 31, further comprising a step of depositing a fourth silicon oxide layer.

12. The method for manufacturing the integrated metal resistance layer according to claim 7, wherein a thickness of the first titanium nitride layer is 50-150 nm, and a thickness of the second cobalt layer is 10-50 nm.

13. The method for manufacturing the integrated metal resistance layer according to claim 7, wherein in step 4, an etching process of an opening of the via at the bottom of the next copper connection stops at the surface of the selected copper connection or the metal resistance layer, so as to form the vias of two different heights at the bottom of the next copper connection.

14. The method for manufacturing the integrated metal resistance layer according to claim 1, wherein in step 32, a selected region of the patterned etching is defined by means of a photolithography process.

15. The method for manufacturing the integrated metal resistance layer according to claim 13, wherein in step 4, simultaneously forming the next copper connection and the via at the bottom of the next copper connection by means of a dual damascene process comprises the following sub-steps: forming a next interlayer film; forming a trench of the next copper connection and the opening of the via at the bottom of the next copper connection in the next interlayer film, the opening of the via at the bottom of the next copper connection being located at the bottom of the trench of the next copper connection; and forming a barrier layer and metal copper, and performing chemical mechanical polishing to obtain the next copper connection composed of the metal copper filling the trench of the next copper connection and the via composed of the metal copper filling the opening of the via at the bottom of the next copper connection.

16. The method for manufacturing the integrated metal resistance layer according to claim 2, wherein the front end of line process comprises step of forming a gate structure on the semiconductor substrate and forming a source region and a drain region on two sides of the gate structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0053] The present application is described in detail below with reference to the drawings and specific implementations:

[0054] FIG. 1 is a schematic structural diagram of a device formed by an existing method for manufacturing an integrated metal resistance layer.

[0055] FIG. 2 is a flowchart of a method for manufacturing an integrated metal resistance layer according to an embodiment of the present application.

[0056] FIGS. 3A-3G are diagrams of device structures in steps of the method for manufacturing an integrated metal resistance layer according to an embodiment of the present application.

DETAILED DESCRIPTION OF THE DISCLOSURE

[0057] Referring to FIG. 2, which is a flowchart of a method for manufacturing an integrated metal resistance layer 212 according to an embodiment of the present application, the method for manufacturing the integrated metal resistance layer 212 according to the embodiment of the present application includes the following steps:

[0058] Step 1. A formation position of a metal resistance layer 212 is selected, wherein the formation position of the metal resistance layer 212 is located on the surface of an interlayer film inlaid with a copper connection in a back end of line process, an interlayer film below the metal resistance layer is a selected interlayer film, a copper connection embedded in the selected interlayer film is a selected copper connection, and the selected copper connection is selected from a first copper connection 211a to a sub-top copper connection.

[0059] Step 2. Referring to FIG. 3A, formation processes of the selected copper connection and the selected interlayer film on a semiconductor substrate 201.

[0060] In the method of this embodiment of the present application, the first copper connection 211a is used as the selected copper connection to perform description. The selected interlayer film is a first interlayer film 210a.

[0061] The semiconductor substrate 201 undergoes a front end of line process, a middle of line process, and the back end of line process before formation of the selected copper connection.

[0062] The semiconductor substrate 201 includes a silicon substrate.

[0063] The front end of line process includes steps of forming a gate structure 105 on the semiconductor substrate 201 and forming a source region and a drain region on two sides of the gate structure 105. The semiconductor substrate 201 is usually integrated with both NMOS and PMOS. Both the NMOS and PMOS are formed in respective active regions, and it is necessary to form shallow trench isolation 102 to define the active region. An N-type well 203 is formed in a formation region of the PMOS, and a P-type well 204 is formed in a formation region of the NMOS.

[0064] The gate structure 205 includes a gate dielectric layer and a gate conductive material layer stacked in sequence, and the gate dielectric layer is a gate oxide layer or a high dielectric constant layer. The gate conductive material layer is a polysilicon gate or a metal gate. The specific structures of the gate dielectric layer and the gate conductive material layer can be selected according to actual requirements of the NMOS and PMOS. For example, the gate dielectric layer of an input-output device may be a gate oxide layer, and the gate dielectric layer of a core device may be a high dielectric constant layer. The gate conductive material layers of the NMOS and PMOS both can be polysilicon gates. Alternatively, the gate conductive material layers of the NMOS and PMOS both are metal gates, but materials of work function layers in the metal gates of the NMOS and PMOS are N-type work function layer and P-type work function layer, respectively.

[0065] A spacer 206 is formed on the side surface of the gate structure 205. The source region and the drain region are self-aligned with the spacer 206.

[0066] If the gate conductive material layer is a metal gate, a gate replacement process is required. Before the gate replacement, the gate conductive material layer is replaced with a dummy polysilicon gate, and then the spacer and the source and drain regions are formed until a bottom portion 207a of a zeroth interlayer film 207 is formed. The top surface of the bottom portion 207a of the zeroth interlayer film 207 is flush with the surface of the dummy polysilicon gate; and then the dummy polysilicon gate is removed and the metal gate is formed in a region where the dummy gate polysilicon is removed.

[0067] Referring to FIG. 3B, then the middle of line process is performed, wherein the zeroth interlayer film 207 and a contact plug 208 passing through the zeroth interlayer film 207 are formed in the middle of line process. The zeroth interlayer film 207 is formed by stacking the bottom portion 207a and a top portion 207b, wherein the top portion 207b of the zeroth interlayer film 207 needs to be formed in the middle of line process, and the top portion 207b of the zeroth interlayer film 207 is located above the top surface of the gate structure 205. The contact plug 208 is formed after the top surface of the zeroth interlayer film 207 is planarized, and the contact plug 208 is formed on the top of lead-out positions of the gate structure 205, the source region, and the drain region. The sectional view shown in FIG. 3B shows two contact plugs 208, wherein the contact plug 208 located on the top of the gate structure 205 passes through only the top portion 207b of the zeroth interlayer film 20, and the contact plug 208 located on the top of the source region or the drain region passes through the entire zeroth interlayer film 207.

[0068] Referring to FIG. 3C, the first copper connection 211a is formed after the contact plug 208 is formed. The bottom of the first copper connection 211a is connected to the contact plug 208. Since the bottom of the first copper connection 211a is directly connected to the contact plug 208, no via is formed at the bottom of the first copper connection 211a. Therefore, the first copper connection 211a is formed by means of a single damascene process.

[0069] In the single damascene process of forming the first copper connection 211a, a carbon-doped silicon nitride layer 209a is formed firstly. The carbon-doped silicon nitride layer 209a is used to prevent copper from diffusing between upper and lower interlayer films, i.e., the zeroth interlayer film 207 and the subsequent first interlayer film 210a.

[0070] Then the first interlayer film 210a is formed, and the first interlayer film 210a is usually composed of a low dielectric constant material (ULK). The low dielectric constant material includes black diamond (BD), wherein composition elements of the black diamond include silicon, oxygen, carbon, and hydrogen.

[0071] Subsequently, photolithography definition is performed, and an etching process is performed on the first interlayer film 210a and the carbon-doped silicon nitride layer 209a to form a trench.

[0072] Then, the trench is filled with a barrier layer and metal copper, and a chemical mechanical polishing process is performed to form the first copper connection 211a composed of the metal copper filling the trench.

[0073] Step 3. The metal resistance layer 212 is formed, including the following sub-steps:

[0074] Step 31. Referring to FIG. 3D, a material layer 212a of the metal resistance layer 212 is deposited, wherein the resistivity of the material layer 212a of the metal resistance layer 212 is greater than the resistivity of copper.

[0075] In the method of this embodiment of the present application, the material layer 212a of the metal resistance layer 212 includes a first titanium nitride layer or a second cobalt layer. That is, the material layer 212a of the metal resistance layer 212 may be composed of the first titanium nitride layer or the second cobalt layer, or may be formed by stacking the first titanium nitride and the second cobalt layer.

[0076] The thickness of the first titanium nitride layer is 50-150 nm.

[0077] The thickness of the second cobalt layer is 10-50 nm.

[0078] In some examples, the method further includes a step of depositing a third diffusion barrier layer 209b before depositing the material layer 212a of the metal resistance layer 212. The third diffusion barrier layer 209b is a carbon-doped silicon nitride layer. The third diffusion barrier layer 209b can prevent the diffusion of copper between the upper and lower interlayer films.

[0079] The method further includes a step of depositing a fourth silicon oxide layer 213a after depositing the material layer 212a of the metal resistance layer 212.

[0080] Step 32. Patterned etching is performed on the material layer 212a of the metal resistance layer 212 to form the metal resistance layer 212 in the selected region, wherein the formation region of the metal resistance layer 212 is located on the surface of the selected interlayer film.

[0081] In this embodiment of the present application, the selected region of the patterned etching is defined by a pattern of a photoresist 214 formed by means of a photolithography process.

[0082] Referring to FIG. 3E, the patterned etching of the material layer 212a of the metal resistance layer 212 stops at the third diffusion barrier layer 209b.

[0083] It can be seen that, after the metal resistance layer 212 is formed, the top surface of the metal resistance layer 212 is higher than the top surface of the first copper connection 211a.

[0084] Step 4. A next copper connection and a via at the bottom of the next copper connection are formed, wherein the vias at the bottom of the next copper connection have two different heights, and the height of the via on the top of the metal resistance layer 212 is less than the height of the via on the top of the selected copper connection.

[0085] Referring to FIG. 3G in this embodiment of the present application, since the first copper connection 211a is selected as the selected copper connection, the next copper connection is a second copper connection 211b. The height of the via 217b at the top of the metal resistance layer 212 is less than the height of the via 217a at the top of the second copper connection 211b. That is, under the condition that the top surfaces of the vias 217a and 217b are flush with each other, the bottom surface of the via 217a is lower, so that the height between the top surface and the bottom surface of the via 217a is greater than the height between the top surface and the bottom surface of the via 217b.

[0086] Referring to FIG. 3F, an etching process of openings 216a and 216b of the vias at the bottom of the second copper connection 211b stops at the surface of the selected copper connection or the metal resistance layer 212, so as to form the vias of two different heights at the bottom of the next copper connection.

[0087] Since vias are formed at the bottom of each copper connection above the first copper connection, each copper connection above the first copper connection and a via at the bottom of the same are formed by means of a dual damascene process. A formation process of each copper connection above the second copper connection and a via at the bottom of each copper connection above the second copper connection is similar to the formation process of the second copper connection 211b and vias 217a and 217b at the bottom of the second copper connection. The following description is carried out using only the formation process of the second copper connection 211b and the vias 217a and 217b at the bottom of the second copper connection as an example.

[0088] In step 4, simultaneously forming the next copper connection and the via at the bottom of the next copper connection by means of a dual damascene process includes the following sub-steps:

[0089] Referring to FIG. 3F, a next interlayer film, i.e., a second interlayer film 210b, is formed.

[0090] A trench 215 of the next copper connection and the openings 216a and 216b of the vias at the bottom of the next copper connection are formed in the next interlayer film. The openings 216a and 216b of the vias at the bottom of the next copper connection are located at the bottom of the trench of the next copper connection, wherein the opening 216a is located on the top of the first copper connection 211a, and the opening 216b is located on the top of the metal resistance layer 212.

[0091] Referring to FIG. 3G a barrier layer and metal copper are formed, and chemical mechanical polishing is performed to obtain the second copper connection 211b composed of the metal copper filling the trench 215 of the second copper connection 211b and the vias 217s and 217b composed of the metal copper filling the openings 216a and 216b of the vias at the bottom of the second copper connection 211b.

[0092] Different from the prior art in which the metal resistance layer is disposed in the zeroth interlayer film between the top surface of the gate structure and the bottom surface of the first copper connection, the present application configures the formation position of the metal resistance layer 212 on the surface of an interlayer film inlaid with a copper connection in the back end of line process, so that in a next layer process with respect to the metal resistance layer 212, only two vias of different heights need to be formed, while other processes do not need to be changed. Therefore, the present application can ensure that the metal resistance layer 212 imposes no adverse effect on the front end of line process and the middle of line process, and eventually can reduce the difficulty and risk in process control and expand the selectivity of a circuit design.

[0093] The present application is described in detail above by using specific embodiments, which, however, are not intended to limit the present application. Without departing from the principles of the present application, those skilled in the art can also make many modifications and improvements, which should also be regarded as the scope of protection of the present application.