TRIPLE-GATE MOS TRANSISTOR AND METHOD FOR MANUFACTURING SUCH A TRANSISTOR

Abstract

A triple-gate MOS transistor is manufactured in a semiconductor substrate including at least one active region laterally surrounded by electrically isolating regions. Trenches are etched on either side of an area of the active region configured to form a channel for the transistor. An electrically isolating layer is deposited on an internal surface of each of the trenches. Each of the trenches is then filled with a semiconductive or electrically conductive material up to an upper surface of the active region so as to form respective vertical gates on opposite sides of the channel. An electrically isolating layer is then deposited on the upper surface of the area of the active region at the channel of the transistor. At least one semiconductive or electrically conductive material then deposited on the electrically isolating layer formed at the upper surface of the active region to form a horizontal gate of the transistor.

Claims

1. A circuit, comprising: a non-volatile memory cell including a vertical gate transistor; and a triple-gate MOS transistor; wherein the vertical gate transistor of the non-volatile memory cell includes a first trench extending into a semiconductor substrate; wherein the triple-gate MOS transistor includes second trenches in the semiconductor substrate on either side of an area of an active region; an electrically isolating layer on an internal surface of each of said first and second trenches; a first semiconductive or electrically conductive material filling the first and second trenches, said first semiconductive or electrically conductive material forming a first vertical gate of the vertical gate transistor and respective second vertical gates on opposite sides of a channel of the triple-gate MOS transistor; a further electrically isolating layer on the upper surface of the active region at the channel; and a semiconductive or electrically conductive material on the further electrically isolating layer so as to form a horizontal gate of the triple-gate MOS transistor.

2. The circuit according to claim 1, wherein the first and second trenches have different depths in the substrate.

3. The circuit according to claim 1, wherein the respective second vertical gates and the horizontal gate are electrically isolated from each other.

4. The circuit according to claim 1, wherein the horizontal gate comprises a first polycrystalline silicon layer, an oxide-nitride-oxide stack and a second polycrystalline silicon layer.

5. The circuit according to claim 4, wherein the non-volatile memory cell further includes a floating gate transistor, and wherein a gate of the floating gate transistor comprises said first polycrystalline silicon layer, oxide-nitride-oxide stack and second polycrystalline silicon layer.

6. A circuit, comprising: a triple-gate MOS transistor; and a vertical gate transistor; a semiconductor substrate including a first substrate area and a second substrate area; wherein the semiconductor substrate includes a plurality of trenches, said plurality of trenches including a pair of trenches in the first substrate area and a further trench in the second substrate area; wherein a portion of the semiconductor substrate is located between a first trench and a second trench of said pair of trenches; an electrically isolating layer on an internal surface of each trench of said plurality of trenches; a semiconductive or electrically conductive material filling each trench of said plurality of trenches; wherein said semiconductive or electrically conductive material in the pair of trenches forms respective first and second vertical gates of the triple-gate MOS transistor on opposite sides of the portion of the semiconductor substrate; wherein said semiconductive or electrically conductive material fill in the further trench forms a vertical gate of the vertical gate transistor; a further electrically isolating layer on an upper surface of the semiconductor substrate; and a semiconductive or electrically conductive material layer on the further electrically isolating layer over the portion of the semiconductor substrate in the first area; wherein said semiconductive or electrically conductive material layer forms a horizontal gate of the triple-gate MOS transistor over the portion of the semiconductor substrate.

7. The circuit of claim 6, wherein said semiconductive or electrically conductive material layer extends on the further electrically isolating layer in the second area to form a further horizontal gate.

8. A circuit, comprising: a triple-gate MOS transistor; a semiconductor substrate; a pair of electrically isolating regions in the semiconductor substrate, wherein a portion of the semiconductor substrate is located between a first electrically isolating region and a second electrically isolating region of said pair of electrically isolating regions; a pair of trenches in and extending through the pair of electrically isolating regions, wherein said portion of the semiconductor substrate is located between a first trench and a second trench of said pair of trenches; an electrically isolating layer on an internal surface of each of said first trench and second trench of said pair of trenches; a semiconductive or electrically conductive material filling each of said first trench and second trench of said pair of trenches; wherein said semiconductive or electrically conductive material forms respective first and second vertical gates of the triple-gate MOS transistor on opposite sides of the portion of the semiconductor substrate; a further electrically isolating layer on an upper surface of the portion of the semiconductor substrate; and a semiconductive or electrically conductive material layer on the further electrically isolating layer; wherein said semiconductive or electrically conductive material layer forms a horizontal gate of the triple-gate MOS transistor over the portion of the semiconductor substrate.

9. The circuit of claim 8, wherein each of the electrically isolating layer and the further electrically isolating layer is a silicon oxide layer.

10. The circuit according to claim 8, wherein the semiconductive or electrically conductive material fill is polycrystalline silicon and wherein the semiconductive or electrically conductive material layer is polycrystalline silicon.

11. The circuit according to claim 8, further comprising doped regions of the semiconductor substrate forming a source of the triple-gate MOS transistor and a drain of the triple-gate MOS transistor.

12. The circuit according to claim 8, wherein the semiconductive or electrically conductive material layer comprises: a first polycrystalline silicon layer on the further electrically isolating layer; an oxide-nitride-oxide stack on the first polycrystalline silicon layer; and a second polycrystalline silicon layer on the oxide-nitride-oxide stack.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Other characteristics and advantages will emerge from the following detailed description with reference to the appended drawings, in which:

[0031] FIG. 1 is a block diagram of a triple-gate MOS transistor according to the state of the art;

[0032] FIG. 2A is a block diagram of a first step of manufacturing the transistor in FIG. 1;

[0033] FIG. 2B is a block diagram of a second step of manufacturing the transistor in FIG. 1;

[0034] FIG. 2C is a block diagram of a third step of manufacturing the transistor in FIG. 1;

[0035] FIG. 3 is a block diagram of a triple-gate transistor;

[0036] FIG. 4 is a block diagram in cross-section of the transistor in FIG. 3;

[0037] FIG. 5 is an electronic diagram of the transistor in FIG. 3;

[0038] FIGS. 6A-6D show steps of a method of manufacturing the transistor in FIG. 3;

[0039] FIG. 7A illustrates a cross-sectional view across the length of the channel of a triple-gate MOS transistor in an environment of integration with a non-volatile memory;

[0040] FIG. 7B illustrates a cross-sectional view across the width of the channel of the triple-gate MOS transistor in FIG. 7A; and

[0041] FIGS. 8A-8J illustrate steps of a method of manufacturing a device comprising the integration of the triple-gate MOS transistor and the non-volatile memory.

DETAILED DESCRIPTION

[0042] Only the elements necessary for understanding the figures were illustrated.

[0043] For reasons of readability of the figures, these elements were not necessarily represented to scale.

[0044] Reference signs identical from one figure to the other designate elements identical or fulfilling the same function; they are therefore not necessarily described in detail for each figure.

[0045] In the present text, the terms on, under, vertical, horizontal, upper, lower, lateral, etc. are understood in relation to the position and orientation of the elements considered in the figures. Particularly, the main surface of the substrate is considered to be horizontal, the thickness of the substrate extending in the vertical direction.

[0046] FIG. 3 schematically illustrates a triple-gate transistor.

[0047] Said transistor is formed in a semi-conductor substrate 1, for example a silicon substrate. The substrate 1 can be doped, typically P-type doped.

[0048] The source S and the drain D of the transistor are formed in an active region 10 formed in said substrate. Said active region is surrounded by an electrically isolating material 2, such as silicon oxide (SiO.sub.2) and/or silicon nitride (Si.sub.3N.sub.4) for example.

[0049] The region forming the channel of the transistor is arranged in the fin between the source S and the drain D. The length of the channel is on the order of 200 nm.

[0050] As better seen in FIG. 4, which is a sectional view in the plane of the dotted rectangle labeled IV in FIG. 3, the region forming the channel C is surrounded on three of its faces by a respective gate G.sub.V1, G.sub.V2 and G.sub.H by means of a gate oxide 11. Each vertical face is attached to a respective vertical gate G.sub.V1, G.sub.V2 surrounded by a gate oxide, while the upper horizontal face is covered with a horizontal gate G.sub.H surrounded by a gate oxide.

[0051] For the same surface imprint, the transistor in FIG. 4 benefits from a greater effective width, corresponding to the perimeter controlled by the gates, which is equal to the sum of the heights of the vertical gates G.sub.V1, G.sub.V2 and the width of the horizontal gate G.sub.H.

[0052] Since the gates G.sub.V1, G.sub.V2 and G.sub.H are separate and electrically isolated from each other, they can each be connected to a separate electrode and controlled (for example, biased with a control voltage) independently of each other.

[0053] This structure of the transistor is reflected in the electric diagram in FIG. 5.

[0054] Such a transistor could be formed by the method described with reference to FIGS. 6A to 6D.

[0055] Referring to FIG. 6A, active regions 100 separated by electrically isolating regions 2 are formed in a semi-conductor substrate 1.

[0056] Referring to FIG. 6B, an active region 100 and each of the two adjacent regions 2 are vertically etched to form a trench 101 extending up to the main surface of the substrate 1. Said etching can be advantageously a dry etching, in particular a plasma-assisted etching.

[0057] At the end of this etching, the active region 10 has two parallel vertical faces. The width of the active region is typically on the order of a few hundred nanometers, for example about 200 nm, but it is possible to obtain a thinner active region by using an etching process adapted to control such a width.

[0058] Referring to FIG. 6C, an electrically isolating layer 11 is then formed on the faces of each trench 101. The thickness of said electrically isolating layer is typically on the order of ten nanometers.

[0059] Then, each trench 101 is filled with a semi-conductive or electrically conductive material 12, constituting the gate material of the vertical gates G.sub.V1, G.sub.V2. This material can be, for example, polycrystalline silicon.

[0060] At the end of this step, the surface of the structure is polished, for example by a mechanical-chemical polishing (CMP).

[0061] Referring to FIG. 6D, an electrically isolating layer 11 is formed on the upper face of the active region 10, then a semi-conductor or electrically conductor gate material 12 is deposited on said layer 11 to form the horizontal gate G.sub.H. Said gate material may be identical to or different from the material used for the vertical gates G.sub.V1, G.sub.V2.

[0062] After the formation of said gates, dopant species are introduced into two opposite regions of the active region to form the source and the drain. Said species can be introduced, for example, by doping or by diffusion. Said dopant species are chosen to provide a doping of a type opposite to that of the substrate. Thus, if the substrate is made of slightly P-doped silicon, the source and the drain are N-type doped, for example with phosphorus.

[0063] Gate electrodes can then be formed on each of the gates G.sub.V1, G.sub.V2 and G.sub.H so as to allow the application of a potential to the horizontal gate on the one hand and to the vertical gates G.sub.V1, G.sub.V2 on the other hand. Thanks to the vertical gates, the threshold voltage of the transistor can then be modulated.

[0064] In some embodiments, the electric potential applied to the horizontal gate may be different from the potential applied to the vertical gates. The vertical gates can then allow modulating the threshold voltage of the MOS transistor.

[0065] In other applications, the electric potential applied to the horizontal gate may be identical to the potential applied to the vertical gates.

[0066] In some embodiments, an N-type doped isolation layer (called NISO) may be formed in the substrate 1 before the etching of the trenches 101. This layer implanted deep in the substrate allows delimiting therein a P-type doped well electrically isolated from the rest of the substrate. In this case, the trenches 101 are formed so as to extend up to the NISO layer, so that, when filling said trenches with the gate material, said gate material is in electrical contact with the material of the NISO layer. The source and the drain also being N-type doped regions, this arrangement of the vertical gates allows generating an electrical conduction mode across the thickness of the substrate. A vertical transistor is thus formed, in which a region of the NISO layer forms the source of the transistor, the N-doped region at the surface of the substrate forms the drain of the transistor, and the region of the substrate arranged between the source and the drain in the vicinity of the vertical gate forms the channel of the transistor.

[0067] This transistor architecture therefore allows forming three electric currents in the channel: a first horizontal electric current driven by the horizontal gate, a second horizontal electric current driven by the two vertical gates, and a vertical electric current also driven by the two vertical gates. In proportion, said electric currents have respectively about 20%, 60% and 20% of the total electric current flowing in the channel of the transistor.

[0068] Such a transistor can have applications in different types of circuits, in particular digital circuits, analog circuits, memories.

[0069] The manufacturing method described above is advantageous in that it uses technologies likely to be already implemented on the substrate on which the transistor is formed. Thus, the method can be easily integrated into existing industrial manufacturing lines and does not generate significant additional costs compared to the existing industrial methods.

[0070] Compared to a triple-gate FinFET transistor known from the state of the art, the triple-gate MOS transistor described above has, in the case where the horizontal gate is connected to the same electric potential as the two vertical gates, similar electrical performances, in particular a supplied electric current (noted I.sub.on) three times greater than in a tunnel-effect transistor.

[0071] Moreover, whether the gates are connected or not to the same potential, the method for manufacturing the triple-gate transistor described above advantageously allows integration with other electronic devices in an integrated circuit formed in the same substrate.

[0072] Thus, in some embodiments, the MOS transistor can be integrated with an embedded non-volatile memory, in particular of the embedded shallow trench memory (eSTM) type. A method for manufacturing such a non-volatile memory, which comprises a vertical transistor, is described in particular in U.S. Pat. No. 9,012,961 (FR 3000838) incorporated herein by reference. As explained in said document, each memory cell comprises a floating gate transistor having a horizontal channel region and a selection transistor having a vertical channel region extending along a vertical gate electrically isolated from the substrate by a gate oxide layer.

[0073] The integration is reflected in the fact that at least part of the steps of manufacturing the triple-gate MOS transistor are common to the steps of manufacturing an embedded non-volatile memory. Particularly, mask-formation, implantation, etching and deposition steps, necessary for the manufacture of the triple-gate MOS transistor and of the memory cell, can be carried out simultaneously in different areas of the semi-conductor substrate. Thus, the gate of the vertical transistor of the eSTM memory cell can be manufactured according to the same method as the vertical gates of the MOS transistor. The manufacture of the triple-gate MOS transistor therefore requires no or few specific steps (such as the formation of the fin in the case of the FinFET transistor of the state of the art) likely to increase the manufacturing cost or time of the non-volatile memory.

[0074] FIGS. 7A and 7B illustrate one embodiment of a triple-gate MOS transistor as described above in an environment of integration with a non-volatile memory. FIG. 7A corresponds to a cross-section across the length of the horizontal channel while FIG. 7B corresponds to a cross-section across the width of the horizontal channel.

[0075] The triple-gate MOS transistor is formed in a semi-conductor substrate, for example a silicon substrate. In the illustrated embodiment, the substrate 1 is P-doped. In other embodiments (not illustrated), the substrate could be N-doped; in this case, the present description would remain applicable by reversing the dopings of the different regions.

[0076] The triple-gate MOS transistor is arranged in a P-doped well, noted PW NVM, which is delimited, across the width and the length of the substrate, by two isolation trenches STI extending vertically in the substrate 1 and, across the thickness of the substrate, by an N-doped NISO isolation layer. N-doped source and drain regions, noted N+SD, are arranged on the surface of the well, and are separated by a region intended to form the horizontal channel of the MOS transistor.

[0077] The horizontal gate of the MOS transistor is formed on a tunnel oxide (OT) layer, forming the gate oxide, arranged on the surface of the substrate 1 facing the region of the channel. Said gate successively comprises, from the tunnel oxide layer, a first polycrystalline silicon layer Polyl, a dielectric layer advantageously comprising a stack of nitride silicon and oxide layers, designated by the acronym ONO (oxide-nitride-oxide), and a second polycrystalline silicon layer Poly2.

[0078] The electrically conductive trenches T described above to form the vertical gates of the MOS transistor extend into the PW NVM well between the OT oxide layer and the NISO well. In a particularly advantageous manner, the electrically conductive material of the trenches is in electrical contact with a doped NISO2 region of the NISO layer.

[0079] FIGS. 8A to 8J illustrate a method for manufacturing the transistor of FIGS. 7A and 7B integrated into a non-volatile memory. In these figures, the upper diagram corresponds to a cross-section across the length of the horizontal channel while the lower diagram corresponds to a cross-section across the width of the horizontal channel.

[0080] Referring to FIG. 8A, a plurality of isolation trenches STI (Shallow Trench Isolation) delimiting active areas of the substrate are formed in a P-doped semi-conductor substrate 1. The isolation trenches STI are formed by etching of the substrate 1 and filling with an electrically isolating material, such as silicon oxide (SiO.sub.2).

[0081] These areas comprise in particular, from left to right, an area eSTM intended for the formation of a memory cell eSTM, a MOS 3G area intended for the formation of a first triple-gate MOS transistor, the two areas eSTM and MOS 3G belonging to a non-volatile memory NVM environment, a MOS 3G T87 area intended for the formation of a second triple-gate MOS transistor and a MOS HV area intended for the formation of a high-voltage MOS transistor, the two MOS 3G T87 and MOS HV areas belonging to a high-voltage HV environment. By high voltage is meant in the present text an electrical voltage greater than or equal to 5 V. Although an area is illustrated for each type of component, it goes without saying that several components of the same type can be formed simultaneously in respective areas of the substrate.

[0082] Referring to FIG. 8B, N-doped NISO isolation layers were formed in the substrate 1 so as to delimit P-doped wells within the thickness of the substrate. Moreover, between the surface of the substrate 1 and each respective NISO layer, two PWELL HV wells were P-type doped in the MOS 3G T87 and MOS HV areas.

[0083] Referring to FIG. 8C, in the substrate 1, NISO2 isolation layers were formed on the NISO layers in the NVM environment. Furthermore, between the surface of the substrate 1 and each respective NISO2 layer, two PWELL NVM wells were P-type doped in the eSTM and MOS 3G areas. The doping of the wells is generally higher in the NVM non-volatile memory environment than in the high-voltage HV environment. Thus, the formation of the PWELL NVM wells requires more dopant implantation steps than that of the PWELL HV wells.

[0084] Referring to FIG. 8D, the electrically conductive trenches T described above are formed, both in the eSTM area and in the MOS 3G and MOS 3G T87 areas. As described above, the trenches T are formed by etching in the P-doped wells of the substrate 1 up to the respective NISO layer, deposition of the electrically isolating material forming the gate oxide and deposition of the electrically conductor material forming the gate. The NISO2 isolation layers allow establishing an electrical connection between each electrically conductor trench and the NISO isolation layer.

[0085] Referring to FIG. 8E, an OHV oxide layer is deposited on the surface of the substrate 1 on the PWELL HV wells, then an OT tunnel oxide layer is deposited on the surface of the substrate 1. Said OT tunnel oxide layer forms the gate oxide of the horizontal transistors of the memory cell and of the MOS transistors. The OHV layer has a greater thickness than that of the OT layer. For example, the thickness of the OHV layer may be on the order of 150 while the thickness of the OT layer may be on the order of 87 .

[0086] Referring to FIG. 8F, a first polycrystalline silicon layer Polyl is deposited on the OT tunnel oxide layer and then part of the layer Polyl is etched on the PWELL HV wells.

[0087] Referring to FIG. 8G, an ONO oxide-nitride-oxide layer is deposited on the entire surface of the substrate 1.

[0088] Referring to FIG. 8H, a second polycrystalline silicon layer Poly2 is deposited on the entire surface of the substrate and then said layer Poly2 as well as the ONO layer are etched on the

[0089] HV environment.

[0090] Referring to FIG. 81, the stack Polyl/ONO/Poly2 is locally etched in the NVM environment, in order to delimit the gate of the eSTM cell and of the MOS 3G transistor.

[0091] Referring to FIG. 8J, an implantation N+was implemented to form the source and drain regions N+SD in all of the wells.