QUANTUM DEVICE FOR FORMING AN ARRAY OF QUANTUM DOTS AND ASSOCIATED MANUFACTURING METHOD

Abstract

A quantum device configured to be able to form an array of quantum dots, the device including for this: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; a plurality of fourth gates, each fourth gate being disposed between two second gates along the rows and between two first gates along the columns.

Claims

1. A quantum device configured to form an array of quantum dots, the device comprising: an active layer made of a semiconductor material; a plurality of first gates disposed along a plurality of rows; a plurality of second gates disposed along a plurality of columns perpendicular to the rows of the plurality of rows; a plurality of third gates, each third gate of the plurality of third gates being disposed at the intersection of one row of the plurality of rows and one column of the plurality of columns, each third gate being separated from the nearest third gates, on a row by a first gate and on a column by a second gate; a plurality of fourth gates, each fourth gate being disposed between two second gates along two adjacent rows and between two first gates along two adjacent columns.

2. The device according to claim 1, wherein each fourth gate is configured to form an electrostatic barrier between two third gates located on either side of the said fourth gate along a diagonally; and wherein each third gate is configured to control the chemical potential of a portion of the active layer underlying said third gate.

3. The device according to claim 1, wherein each first gate of the plurality of first gates extends entirely over the active layer; and wherein each second gate of the plurality of second gates extends entirely over the active layer; and wherein each third gate of the plurality of third gates extends entirely over the active layer; and wherein each fourth gate of the plurality of fourth gates extends entirely over the active layer.

4. The device according to claim 1, wherein each gate of the pluralities of first, second, third and fourth gates extends over a first dimension, forming a first width, measured along a row or a column, the active layer having a second dimension, forming a second width, measured along said row or said column, greater than or equal to the first width.

5. The device according to claim 1, wherein each first gate has a length and a width, less than or equal to the length, each first gate being arranged so that its length is aligned with a row of the plurality of rows; and wherein each second gate has a length and a width, less than or equal to the length, each second gate being arranged so that its length is aligned with a column of the plurality of columns.

6. The device according to claim 1, wherein each third gate has the shape of a four-pointed star, a first diagonal of which, passing through two opposite points, being parallel to a row of the plurality of rows, and a second diagonal of which, distinct from the first diagonal and passing through two other opposite points, being parallel to a column of the plurality of columns.

7. The device according to claim 1, wherein the first, second, third and fourth gates are arranged at the same distance from the active layer.

8. The device according to claim 1, comprising a first dielectric layer extending over the active layer, each first gate, each second gate, each third gate and each fourth gate extending over the first dielectric layer, the first dielectric layer being common to all the gates.

9. The device according to claim 1, wherein the plurality of third grids is polarised independently of the plurality of fourth grids.

10. The device according to claim 1, wherein each of the first, second, third and fourth gates is polarisable independently of the other of the first, second, third and fourth gates.

11. The device according to claim 1, wherein two adjacent fourth gates, arranged parallel to a row, are separated by a second gate; and wherein two adjacent fourth gates, arranged parallel to a column, are separated by a first gate; and wherein two adjacent fourth grids, arranged along a diagonal, are separated by a third gate.

12. The device according to claim 1, comprising spacers arranged to: separate each first gate from the first, second, third and fourth adjacent gates; separate each second gate from the first, second, third and fourth adjacent gates; separate each third gate from the first, second, third and fourth adjacent gates; and separate each fourth gate from the first, second, third and fourth adjacent gates.

13. A method for manufacturing a quantum device according to claim 1, from a substrate including a semiconductor layer, forming an active layer, at a first surface of said substrate, the method comprising: depositing a first dielectric layer onto the first surface; depositing a support layer of a conductive or dielectric material onto the first dielectric layer; etching the support layer so as to form an array of first pillars forming a plurality of rows and a plurality of columns, the first pillars forming the fourth gates when the support layer is of a conductive material; conformally depositing a second dielectric layer onto the array of first pillars, the thickness deposited being chosen so as to fill the space between each first pillar and its nearest neighbours; etching the second dielectric layer so as to expose the first dielectric layer between each first pillar of the array of first pillars along the diagonals of said array of first pillars; depositing a first conductive layer so as to fill the apertures made during the step of etching the second dielectric layer; chemico-mechanically polishing the structure obtained at the end of the previous depositing step so as to obtain an array of second conductive pillars at the apertures made during the etching of the second dielectric layer, stopping polishing being performed on the support layer so that the second conductive pillars are no longer in contact with each other at the end of this step and form the third gates; selectively removing the second dielectric layer so as to keep only the array of first pillars and the array of second conductive pillars on the first dielectric layer; conformally depositing a third dielectric layer onto the array of first pillars and the array of second conductive pillars, the thickness deposited being chosen so as to fill the space between each first pillar and the second conductive pillars nearest to said first pillar; etching the third dielectric layer so as to expose the first dielectric layer between each first pillar of the array of first pillars along the rows and columns of said array of first pillars; depositing a second conductive layer so as to fill the apertures made during the etching of the third dielectric layer; chemico-mechanically polishing the structure obtained at the end of the previous step, so as to obtain an array of third conductive, conductive pillars at the apertures made during the etching of the third dielectric layer, stopping polishing being performed on the support layer so that the third conductive pillars are no longer in contact with each other at the end of this step and form the first gates and the second gates; when the material of the support layer is a dielectric material, selectively removing the first pillars of the plurality of first pillars so as to expose the first dielectric layer at the location of said first pillars; when the material of the support layer is a dielectric material, depositing a third conductive layer into the space left by the first pillars during the previous selective removal step; when the material of the support layer is a dielectric material, chemico-mechanically polishing the structure obtained at the end of the previous step, so as to obtain an array of fourth, conductive pillars at the location of the first pillars, stopping polishing being performed so that the fourth, conductive pillars are no longer connected to one another at the end of this step and form fourth gates.

14. The method according to claim 13, wherein the substrate is a SOI type substrate and the active layer is made in the silicon layer of the substrate.

15. The method according to claim 13, wherein a distance d separating two neighbouring first pillars and a height h of the first pillars at the end of etching of the support layer so as to form an array of first pillars are chosen such that h>d/2.

Description

BRIEF DESCRIPTION OF THE FIGURES

[0078] The figures are set forth by way of indicating and in no way limiting purposes of the invention.

[0079] FIG. 1 shows a schematic representation of a device according to an embodiment of the invention.

[0080] FIG. 2A to FIG. 2C show a schematic representation of different substrates likely to be used in a device or method according to an embodiment of the invention.

[0081] FIG. 3 shows a schematic representation of an SOI-type substrate used in a method according to an embodiment of the invention and serving to illustrate the different steps of the method.

[0082] FIG. 4A to FIG. 4J show a schematic representation of the steps of the method according to an embodiment of the invention (the step(s) associated with each figure are noted in brackets).

DETAILED DESCRIPTION

[0083] Unless otherwise specified, a same element appearing in different figures has a single reference.

Quantum Device for Forming an Array of Quantum Dots

[0084] A first aspect of the invention illustrated in [FIG. 1] relates to a quantum device DQ configured to form an array of quantum dots QD. For this, the device DQ comprises an active layer CA made of a semiconductor material. In an embodiment, this layer CA is a silicon (Si) or germanium (Ge) layer, but other semiconductor materials may be contemplated. It is in this active layer CA that the quantum dots QD are formed. For the record, a quantum dot QD is formed by an electrostatic potential well in which it is possible to trap one or more charged particles, for example one or more holes or one or more electrons.

[0085] The device QD according to an aspect of the invention also comprises a plurality of first gates G1 disposed along a plurality of rows LI, above the active layer CA. The device according to an aspect of the invention also comprises a plurality of second gates G2 disposed along a plurality of columns CO perpendicular to the rows LI of the plurality of rows LI, above the active layer CA. The device DQ according to an aspect of the invention further comprises a plurality of third gates G3, each third gate G3 of the plurality of third gates G3 being disposed at the intersection of a row LI of the plurality of rows LI and a column CO of the plurality of columns CO, above the active layer CA, each third gate G3 being separated from the nearest third gates G3, on a row LI by a first gate G1 and on a column CO by a second gate G2. Finally, the device DQ according to an aspect of the invention comprises a plurality of fourth gates G4, each fourth gate G4 being disposed between two second gates G2 along the rows LI and between two first gates G1 along the columns CO, above the active layer CA.

[0086] The first gates G1 are separated from each other. They are also separate from the second, third and fourth gates. In this way, each first gate G1 can be polarised independently of the other gates. This means that an electrical potential can be applied to each gate without simultaneously polarising the adjacent gates. In the same way, the second, third and fourth gates are separated from each other so that they can be polarised independently of the other gates.

[0087] Thus, in the device DQ according to an aspect of the invention, a quantum dot QD may be formed below each third gate G3 so as to form an array of quantum dots QD. Indeed, each first gate G1 of the plurality of first gates G1 makes it possible, when an electrical potential is applied thereto, to modify potential barrier separating two parts of the active layer CA located under two adjacent third gates G3 along the rows. Similarly, each second gate G2 of the plurality of second gates G2 makes it possible, when an electrical potential is applied thereto, to modify potential barrier separating two parts of the active layer CA located under two adjacent third gates G3 along the columns CO. Additionally, each fourth gate G4 of the plurality of fourth gates G4 makes it possible, when an electrical potential is applied thereto, to form a potential barrier ensuring absence of charged particles below said gates G4, that is, between the rows and columns of the array. Furthermore, the first gates G1, the second gates G2 and the fourth gates G4 allow this modification to be carried out locally, the latter G1, G2, G4 being above the active layer CA (in other words, there is no conductive layer between the oxide of the first gates G1, the second gates G3 and the fourth gates G4 and the active layer CA). Also, by virtue of the control of the potential barriers exerted by the first gates G1, the second gates G2 and the fourth gates G4, it is possible to achieve electrostatic confinement of charged particles below the third gates G3 of the plurality of third gates G3 to form a quantum dot QD below each third gate G3.

[0088] Moreover, in each quantum dot QD, the charged particle(s) present are associated with a chemical potential. But, since each third gate G3 is above the part of the active layer CA in which a quantum dot is formed (in other words, there is no conductive layer between the oxide of the third gates G3 and the active layer CA), each third gate G3 of the plurality of third gates G3 makes it possible, when an electric potential is applied thereto, to modify chemical potential of the charged particles present in the quantum dot QD associated with the third gate G3 considered.

[0089] In the embodiment shown in [FIG. 1], the device comprises a single active layer CA. All the first, second and third gates G1, G2, G3 and G4 extend entirely above the active layer CA. No gate extends only partially above the active layer CA. In other words, the active layer CA extends under each first, second, third and fourth gate G1, G2, G3, G4 and even beyond each aforementioned gate.

[0090] In the embodiment shown in [FIG. 1], each first gate G1 and each second gate G2 has a rectangular shape. Each gate thus has a length and a width, measured in the plane (i.e. parallel to the active layer CA), the length being greater than or equal to the width. Each first gate G1 is arranged so that its length is aligned parallel to the rows LI. Each second gate G2 is arranged so that its length is aligned parallel to the columns CO. This particular alignment may be the result of the manufacturing process according to an aspect of the invention, detailed below.

[0091] The first and second gates G1, G2 may also have a thickness, measured perpendicular to the plane. For each gate G1, G2, its thickness is beneficially less than its length.

[0092] In [FIG. 1], each third gate G3 has the shape of a four-pointed star. Each of the points is aligned along a row LI or a column CO. In other words, each third gate G3 has a first diagonal, passing through two of the opposite points of the star, parallel to the row LI on which said gate G3 is located. Each third gate G3 also has a second diagonal, distinct from the first diagonal, passing through two other opposite points of the star, parallel to the column CO on which said gate G3 is located. The shape and orientation of this shape for the third gates G3 may be the result of the manufacturing process implemented.

[0093] Thus, each first or second gate G1, G2, adjacent to a third gate G3, has its length aligned along one of the points of said third gate G3.

[0094] More specifically, the first and second gates G1, G2 may have points, due to their rectangular shape. Each of the first and second gates G1, G2 can have a third diagonal, passing through two of the opposite points on the said gate. This third diagonal beneficially has an angle with respect to a row LI which is less than or equal to 45. In other words, the third diagonal of a first or second gate G1, G2, has an angle with respect to one of the two diagonals of an adjacent third gate G3, which is less than or equal to 45.

[0095] The fourth gates G4 can be rectangular or square.

[0096] The fourth gates G4 can be arranged on a matrix of rows and columns according to the same distribution period as the third gates G3. However, they are offset so as to fit into the matrix of rows LI and columns CO formed by the first, second and third gates G1, G2 and G3. The fourth gates are, for example, arranged so that: [0097] two adjacent fourth grids G4, arranged parallel to a row LI, are separated by a second gate G2 and in an embodiment only one second gate G2; and [0098] two fourth adjacent grids G4, arranged parallel to a column CO, are separated by a first gate G1 and in an embodiment only one first gate G1; and [0099] two adjacent fourth grids G4, arranged parallel to a diagonal to the rows LI and columns CO (i.e. extending in a direction of 45 with respect to the rows LI and columns CO) are separated by a third grid G3 and in an embodiment only one third grid G3.

[0100] This arrangement of fourth gates G4 with respect to the third gates G3 makes it possible to form a potential barrier between two quantum dots located under two adjacent third gates G3 along a diagonal.

[0101] The third gates G3 can thus freely control the chemical potential of the quantum dots located above them, without risking modulating the chemical potential of the neighbouring quantum dots.

[0102] The first, second, third and fourth gates G1, G2, G3 and G4 beneficially have the same distance, to within 10%, from the active layer CA. This results in a substantially identical gate/active layer coupling. The first, second, third and fourth gates G1, G2, G3 and G4 are separated from the active layer CA by a dielectric layer, for example.

[0103] In one embodiment, the oxide of the first G1, second G2, third G3 and/or fourth gates G4 is chosen from SiO.sub.2, HfO.sub.2 or Al.sub.2O.sub.3. In one embodiment, the thickness of the oxide of the first gates G1, second gates G2, third gates G3 and/or fourth gates G4 is between 5 nm and 10 nm. In one embodiment, the electrodes of the first gates G1, second gates G2, third gates G3 and/or fourth gates G4 are made of a conductive material chosen from Ti, TiN or even W. In an embodiment, the device according to the invention is made in an SOI type substrate and the active layer is a silicon layer. In this embodiment, the first, second, third and fourth gates G1, G2 and G3 are in direct contact with the active layer CA.

[0104] In one alternative embodiment, the device is made from a bulk silicon substrate. Beneficially, the substrate comprises an epitaxial silicon layer (denoted as .sup.28Si in the figure) covered with a thermal oxide (denoted as SiO.sub.2 in the figure), this epitaxial silicon layer being deposited onto the intrinsic silicon layer (denoted as .sup.iSi in the figure) of the bulk silicon substrate. Such a substrate is illustrated in [FIG. 2A]. In this embodiment, the active layer CA is made in the silicon layer, beneficially the epitaxial silicon layer. It will be appreciated that the dimensions shown in the figure are given purely by way of illustration.

[0105] In one alternative embodiment, the device is made from an Si/SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [FIG. 2B]. This heterostructure comprises a layer whose Ge concentration (denoted as Si.sub.1-xGe.sub.x in the figure) changes linearly over time, on which an SiGe layer (denoted as Si.sub.0.7Ge.sub.0.3) lies, a quantum well for electrons formed in an Si layer (denoted as .sup.28Si in the figure), a spacer of (denoted as Si.sub.0.7Ge.sub.0.3 in the figure) located on the Si layer and a silicon layer (denoted as Si Cap in the figure). In this embodiment, the active layer is made in the Si layer. It will be appreciated that the dimensions indicated in the figure are given purely by way of illustration.

[0106] In one alternative embodiment, the device is made from a Ge/SiGe heterostructure. A substrate comprising such a heterostructure is illustrated in [FIG. 2C]. The latter comprises a layer whose Si concentration (denoted as Si.sub.1-xGe.sub.x in the figure) changes linearly over time, on which an SiGe layer (denoted as Si.sub.0.2Ge.sub.0.8) lies, a quantum well for holes formed in a Ge layer (denoted as Ge in the figure), a SiGe spacer (denoted as Si.sub.0.2Ge.sub.0.8 in the figure) located on the Ge layer and a silicon layer (denoted as Si Cap in the figure). In this embodiment, the active layer is made in the Ge layer. It will be appreciated that the dimensions indicated in the figure are purely given by way of illustration.

Method for Manufacturing a Quantum Device Including an Array of Islands

[0107] A second aspect of the invention illustrated in [FIG. 3] to [FIG. 4J] relates to a method for manufacturing a semiconductor device according to the invention from an SB substrate comprising a semiconductor layer, referred to as the active layer CA, on a first surface of said SB substrate or near the first surface. By near the first surface, it is meant that the distance separating the active layer from the first surface is less than the distance separating the active layer from the second surface of the substrate opposite to the first surface. In an embodiment the distance separating the active layer CA from the first surface of the substrate SB is less than 500 nm, in an embodiment less than 200 nm or even less than 100 nm. In one embodiment, the thickness of the active layer CA is between 5 and 20 nm, for example equal to 10 nm.

[0108] In one embodiment, the active layer CA is made of silicon, the substrate in an embodiment being an SOI (Silicon-On-Insulator) type substrate. In one alternative embodiment, the substrate is an SiMOS type substrate as previously described. In one alternative embodiment, the substrate comprises an Si/SiGe heterostructure as previously described at its first surface. In one alternative embodiment, the substrate comprises a Ge/SiGe heterostructure as previously described at its first surface.

[0109] The method according to an aspect of the invention comprises a step E1 of depositing a first dielectric layer D1 onto the first surface. When the active layer CA is at this first surface (as illustrated in [FIG. 3] to [FIG. 4J], then this deposition is performed onto the active layer CA. In one embodiment, the material of the first dielectric layer D1 is chosen from SiO.sub.2, HfO.sub.2 or Al.sub.2O.sub.3. In one embodiment, the first dielectric layer D1 is made of a high permittivity dielectric material. In one embodiment, the first dielectric layer D1 includes several dielectric sublayers. For example, it includes an SiO.sub.2 first sublayer ensuring a good quality interface with the layer onto which it is deposited (for example the Si active layer), then a HfO.sub.2 or Al.sub.2O.sub.3 second sublayer. It will be appreciated that this is only an example and other combinations may be contemplated.

[0110] The method then comprises a step E2 of depositing a support layer SP onto the first dielectric layer D1. In one embodiment, the material of the support layer SP is a dielectric material, for example silicon nitride. In one alternative embodiment, the material of the support layer SP is a conductive material, for example a metal. The structure obtained after these two steps is illustrated in [FIG. 4A].

[0111] As illustrated in [FIG. 4B], the method then comprises a step E3 of etching the support layer so as to form an array of first pillars PI forming a plurality of rows and a plurality of columns. In an embodiment, the distance d separating two neighbouring first pillars PI and the height h of the first pillars PI are chosen so that h>d/2. In an embodiment, the height h of the first pillars is between 50 nm and 500 nm, for example equal to 200 nm.

[0112] The method also comprises a step E4 of conformally depositing a second dielectric layer D2 onto the array of first pillars PI, the thickness deposited being chosen so as to fill the space between each first pillar PI and its nearest neighbours. In one embodiment, the dielectric layer D2 is made of SiO.sub.2. In one embodiment, the second dielectric layer D2 includes several dielectric sublayers.

[0113] The method then comprises a step E5 of etching the second dielectric layer D2 so as to expose the first dielectric layer D1 between each first pillar PI of the array of first pillars PI along the diagonals of said array of first pillars PI, the first dielectric layer D1 serving as an etching stop layer. In one exemplary embodiment, the second dielectric layer D2 is an SiO.sub.2 layer and the first dielectric layer D1 (serving as a barrier layer) is a HfO.sub.2 or Al.sub.2O.sub.3 layer. The structure obtained after these two steps E4, E5 is illustrated in [FIG. 4C], the exposed zones of the first dielectric layer D1 being marked by a dotted circle in the top representation at the bottom of the figure.

[0114] In one embodiment, the method also comprises a step E6 of chemico-mechanically polishing the structure obtained at the end of the previous step E5. Although optional, this step E6 makes it possible to flatten the surface of the structure and thus to improve the quality of the deposition of the first conductive layer described below. Furthermore, carrying out the chemical mechanical polishing in two stages avoids any selectivity problems with the chemical mechanical polishing performed at the end of the deposition of the first conductive layer described below.

[0115] The method according to an aspect of the invention then comprises a step E7 of depositing a first conductive layer so as to fill the apertures made during step E5 of etching the second dielectric layer D2. Thus, at these apertures, the conductive layer is in direct contact with the first dielectric layer D1. In one embodiment, the material of the conductive layer is chosen from Ti, TiN or even W.

[0116] The method according to an aspect of the invention further comprises a step E8 of chemico-mechanically polishing the structure obtained at the end of the previous step so as to obtain an array of second conductive pillars PC1 at the apertures made during the step E5 of etching the second dielectric layer D2. During this step E8, stopping polishing is performed on the support layer SP so that the second pillars PC1 are no longer in contact with each other at the end of this step E8. The structure obtained at the end of these two steps or three steps (when the optional chemical mechanical polishing step E6 is implemented) is illustrated in [FIG. 4D]. In the final structure obtained at the end of the method according to an aspect of the invention, the second conductive pillars PC1 will form the third gates G3 of [FIG. 1] making it possible to control the chemical potential of the charged particles at the quantum dots QD.

[0117] As illustrated in [FIG. 4E], the method then comprises a step E9 of selectively removing the second dielectric layer D2 so as to keep only the array of first pillars PI and the array of second pillars PC1 on the first dielectric layer (D1). During this removal step, the first dielectric layer D1 is preserved and serves as a stop layer.

[0118] The method then comprises a step E10 of conformally depositing a third dielectric layer D3 onto the array of first pillars PI and onto the array of second pillars PC1, the thickness deposited being chosen so as to fill the space between each first pillar PI and the second pillars PC2 nearest to said first pillar PI.

[0119] The method also comprises a step E11 of etching the third dielectric layer D3 so as to expose the first dielectric layer D1 between each first pillar PI of the array of first pillars PI along the rows and columns of said array of first pillars PI. The structure obtained at the end of these two steps is illustrated in [FIG. 4F], the exposed zones of the first dielectric layer D1 being marked by a dotted circle.

[0120] In one embodiment, the method comprises a step of chemico-mechanically polishing the structure obtained at the end of the previous step E11 (not represented in the figures). Although optional, this step makes it possible to flatten the surface of the structure and thus improve the quality of the deposition of the second conductive layer C2 described below. Furthermore, carrying out the chemical mechanical polishing in two stages avoids any selectivity problems with the chemical mechanical polishing performed at the end of the deposition of the second conductive layer C2 described below.

[0121] As illustrated in [FIG. 4G], the method then comprises a step E12 of depositing a second conductive layer C2 so as to fill the apertures made during step E11 of etching the third dielectric layer D3. Thus, at these apertures, the second conductive layer C2 is in direct contact with the first dielectric layer D1. In one embodiment, the material of the second conductive layer C2 is chosen from Ti, TiN or even W.

[0122] The method then comprises a step E13 of chemico-mechanically polishing the structure obtained at the end of the previous step, so as to obtain an array of third conductive pillars PC2, said third conductive pillars PC2 being in direct contact with the first dielectric layer D1 at the apertures made during step E11 of etching the third dielectric layer D3. During this step E13, stopping polishing is performed on the support layer SP so that the third pillars PC2 are no longer connected to each other at the end of this step E13. In one embodiment, in order to ensure that the third pillars are properly disconnected from one another, a step E14 of chemico-mechanically over-polishing the structure obtained at the end of previous step E13 is implemented. By over-polishing, it is meant continuing polishing when the stop layer has been reached. Indeed, detection that the stop layers have been reached by polishing is performed automatically by physical detection of a polishing signal from the stop layer. But, if there are thickness non-uniformities across the plate, the signal may be detected even though the barrier layer has not been reached on the whole plate, but only on part of it. Over-polishing therefore allows polishing to continue long enough after the signal has been detected so that all the zones on the plate are sufficiently polished. The structure obtained at the end of this step E13 or both steps (when the optional over-polishing step E14 is implemented) is illustrated in [FIG. 4H]. In the final structure, the third conductive pillars PC2 will form the first gates G1 and the second gates G2 of FIG. 1 to control the potential barrier between two adjacent quantum dots QD.

[0123] In the final structure, when the support material is a conductive material, then the first plurality of pillars PI will form the plurality of fourth gates G4 of [FIG. 1] for controlling the absence of charge between the rows LI and the columns CO. When, on the other hand, the support material is a dielectric material, it is necessary to remove the existing first plurality of pillars PI and replace them with conductive pillars.

[0124] For this, as illustrated in [FIG. 4I], the method then comprises, when the material of the support layer SP is a dielectric material, a step E15 of selectively removing the first pillars PI of the plurality of first pillars PI so as to expose the first dielectric layer D1 at the location of said first pillars PI. This removal step can be implemented by a selective wet etching method, for example based on H.sub.3PO.sub.4.

[0125] The method then comprises, when the material of the support layer SP is a dielectric material, a step E16 of depositing a third conductive layer into the space left by the first pillars PI during the previous selective removal step E15.

[0126] Finally, when the material of the support layer SP is a dielectric material, the method comprises a step E17 of chemico-mechanically polishing the structure obtained at the end of the previous step, so as to obtain an array of fourth conductive pillars PC3 at the location of the first pillars PI, stopping polishing being performed in such a way that the fourth conductive pillars are no longer connected to one another at the end of this step. The structure obtained at the end of this step is illustrated in [FIG. 4J]. In this final structure, the array of fourth pillars PC3 will form the plurality of fourth gates G4 of [FIG. 1], for controlling absence of charge between the rows LI and the columns CO.

[0127] As shown in [FIG. 1] and [FIG. 4J], in the device thus obtained, the third gates G3 in an embodiment have central symmetry and the distribution of the first gates G1 and second gates G2 adjacent to each third gate G3 is performed according to this symmetry. Similarly, the first, second and third gates G1, G2, G3 are in an embodiment distributed symmetrically with respect to the axis associated with each row LI and the axis associated with each column CO.

[0128] The articles a and an may be employed in connection with various elements and components of compositions, processes or structures described herein. This is merely for convenience and to give a general sense of the compositions, processes or structures. Such a description includes one or at least one of the elements or components. Moreover, as used herein, the singular articles also include a description of a plurality of elements or components, unless it is apparent from a specific context that the plural is excluded.

[0129] It will be appreciated that the various embodiments and aspects of the inventions described previously are combinable according to any technically permissible combinations.