CONTROL OF BIAS CURRENT TO A LOAD
20220345119 · 2022-10-27
Assignee
Inventors
Cpc classification
H03K3/353
ELECTRICITY
H03F2200/447
ELECTRICITY
H03F2200/453
ELECTRICITY
International classification
Abstract
A circuit portion comprises a load circuit portion and a bias circuit portion. The load circuit portion comprises a load transistor. The bias circuit portion comprises a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor. The bias circuit portion also comprises a current input for receiving an input current, a supply voltage input for receiving a supply voltage, and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current, and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.
Claims
1. A circuit portion comprising: a load circuit portion comprising a load transistor; and a bias circuit portion comprising: a replica transistor matched to the load transistor and connected to the load transistor at a node such that when a current flows through the replica transistor, a current proportional to the current through the replica transistor flows through the load transistor; a current input for receiving an input current; a supply voltage input for receiving a supply voltage; and a feedback loop arranged to: adjust a voltage at the node connecting the replica transistor and the load transistor such that the replica transistor conducts a current proportional to the input current; and counteract variations in the voltage at the node connecting the replica transistor and the load transistor arising from changes in the supply voltage.
2. The circuit portion as claimed in claim 1, arranged such that a bias current is provided by the bias circuit portion to the load circuit portion that is substantially proportional to the input current.
3. The circuit portion as claimed in claim 1, arranged such that process, voltage and temperature variations in the load transistor are replicated in the matched replica transistor.
4. The circuit portion as claimed in claim 1, wherein the load circuit portion comprises a second load transistor, and the bias circuit portion comprises a second replica transistor matched to the second load transistor.
5. The circuit portion as claimed in claim 4, wherein the first and second replica transistors are arranged to replicate an arrangement of the first and second load transistors.
6. The circuit portion as claimed in claim 4, wherein the first and second replica transistors are arranged to replicate a current branch of the load circuit portion, the current branch comprising the first and second load transistors.
7. The circuit portion as claimed in claim 1, wherein the feedback loop comprises a plurality of feedback transistors, at least one feedback transistor being matched to at least one other feedback transistor.
8. The circuit portion as claimed in claim 7, wherein one of the feedback transistors is arranged to supply a total current required by the first replica transistor and the load circuit portion.
9. The circuit portion as claimed in claim 1, wherein the first load transistor forms part of a load inverter, the first replica transistor forms part of a replica inverter, and the replica inverter is arranged to replicate the load inverter.
10. The circuit portion as claimed in claim 9, wherein the replica inverter comprises a plurality of replica transistors, the load inverter comprises a plurality of load transistors, and each replica transistor is matched to at least one load transistor.
11. The circuit portion as claimed in claim 9, further comprising a level shifter arranged to shift a voltage level of an output of the load inverter to a predetermined voltage.
12. The circuit portion as claimed in claim 9, arranged such that the load inverter is run in open loop.
13. A sinusoid-to-square wave buffer circuit portion comprising: the circuit portion as claimed in claim 9; a signal input for receiving a sinusoidal input signal coupled to an input of the load inverter, wherein the load inverter comprises a signal output arranged to output a square wave signal.
14. An electronic device comprising: the sinusoid-to-square wave buffer circuit portion as claimed in claim 13; an oscillator coupled to the signal input to provide said sinusoidal input signal; and a current source arranged to provide said input current.
15. A method of converting a sinusoidal input signal into a square wave output signal comprising providing said sinusoidal input signal to a circuit portion as claimed in claim 1 and using said circuit portion to generate said square wave output signal from said sinusoidal input signal.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0039] Certain preferred embodiments of the invention will now be described, by way of example only, with reference to the accompanying drawings, in which:
DETAILED DESCRIPTION
[0040]
[0041] The bias circuit portion 2 is coupled to the inverter amplifier portion 4, which is in turn coupled to the level shifter portion 6. The bias circuit portion 2 may also be referred to herein as a voltage regulator circuit portion 2.
[0042] The bias circuit portion 2 is coupled to a positive voltage supply rail VDDA 10, a negative voltage supply or ground rail V.sub.ss 14, and a current source (not shown) which produces an input current I.sub.bias provided to a current input 18. In this example, the positive voltage supply rail VDDA 10 provides a supply voltage to the bias circuit portion 2 and the inverter amplifier portion 4. The input current I.sub.bias typically exhibits predictable or small PVT variations. For example, the input current I.sub.bias may be proportional to absolute temperature (PTAT) in order to compensate for a decrease in transconductance (e.g. due to a temperature increase) in the transistors included in the sinusoid-to-square wave buffer 1. In other examples, the input current I.sub.bias may be substantially PVT-stable, though this is not essential. The input current Ibias is nominally equal to 3 nA in one example but is not limited as such—the input current I.sub.bias may have any appropriate value. The bias circuit portion 2 comprises three p-type metal-oxide-semiconductor (PMOS) field-effect transistors (FET) 20, 22 & 24, and four n-type metal-oxide-semiconductor (NMOS) field-effect transistors (FET) 26, 28, 30 & 32. The transistors described herein are not limited to PMOS and NMOS transistors as shown in this example, but may comprise any appropriate type of transistor.
[0043] The source terminals of two of the PMOS transistors 20 & 22 are coupled to the positive voltage supply rail VDDA 8 via the supply voltage input 10. The gate terminal of one of the PMOS transistors 20 is coupled to the gate terminal of the other PMOS transistor 22. The first PMOS transistor 20 is diode-connected and therefore the gate terminal thereof is coupled to the drain terminal thereof. The drain terminal of the first PMOS transistor 20 is coupled to the drain terminal of one of the NMOS transistors 28, and the drain terminal of the second PMOS transistor 22 is coupled to the source terminal of a third PMOS transistor 24 at a first node 34.
[0044] The drain terminal of another of the NMOS transistors 26 is coupled to the current source 16 producing the input current I.sub.bias via the current input 18. This second NMOS transistor 26 is diode-connected and therefore the gate terminal thereof is coupled to the drain terminal thereof. The gate terminal of the NMOS transistor 26 is coupled to the gate terminal of the first NMOS transistor 28. The source terminal of the second NMOS transistor 26 is coupled to the drain terminal of a third NMOS transistor 30. The third NMOS transistor 30 is diode-connected and therefore the gate terminal thereof is coupled to the drain terminal thereof. The source terminal of the third NMOS transistor 30 is coupled to the ground rail V.sub.ss 14. The gate terminal of the third NMOS transistor 30 is coupled to the gate terminal of a fourth NMOS transistor 32 and to the gate terminal of the third PMOS transistor 24 at a second node 36.
[0045] The drain terminal of the third PMOS transistor 24 is coupled to the drain terminal of the fourth NMOS transistor 32 and to the source terminal of the first NMOS transistor 28 at a third node 38. The source terminal of the fourth NMOS transistor 32 is coupled to the ground rail V.sub.ss 14.
[0046] The inverter amplifier portion 4 is coupled to the first node 34, to the ground rail V.sub.ss 14, and to a sinusoidal input signal V.sub.in 42. The sinusoidal input signal V.sub.in 42 may be generated by any appropriate source (not shown), e.g. a crystal oscillator, a resistor-capacitor (RC) oscillator, an inductor-capacitor (LC) oscillator, etc. The inverter amplifier portion comprises two PMOS transistors 44 & 46, two NMOS transistors 48 & 50, a resistor 52 and a capacitor 54.
[0047] The source terminal of one of the PMOS transistors 44 is coupled to the first node 34. The gate terminal of the PMOS transistor 44 is diode-connected and therefore the gate terminal thereof is coupled to the drain terminal thereof. One of the NMOS transistors 48 is diode-connected and therefore the gate terminal thereof is coupled to the drain terminal thereof. The gate and drain terminals of the first PMOS transistor 44 are coupled to the gate and drain terminals of the first NMOS transistor 48. The source terminal of the first NMOS transistor 48 is coupled to the ground rail V.sub.ss 14.
[0048] The source terminal of the second PMOS transistor 46 is also coupled to the node 34. The gate terminal of the second PMOS transistor 46 is coupled to the gate terminal of the second NMOS transistor 50. The drain terminal of the second PMOS transistor 46 is coupled to the drain terminal of the second NMOS transistor 50 at a fourth node 56. The source terminal of the second NMOS transistor 50 is coupled to the ground rail V.sub.ss 14. The gate terminals of the second PMOS transistor 46 and the second NMOS transistor 50 are coupled, via the resistor 52, to the gate and drain terminals of the first PMOS transistor 44 and the first NMOS transistor 48. The gate terminals of the second PMOS transistor 46 and the second NMOS transistor 50 are also coupled, via the capacitor 54, to the sinusoidal input signal V.sub.in 42.
[0049] The level shifter portion 6 is coupled to a second positive voltage supply rail V.sub.DDD 60, to the ground rail V.sub.ss 14, and to the fourth node 56. The level shifter portion 6 outputs a square wave clock signal CK.sub.out 64, which may be coupled to further components (not shown) requiring a square wave clock signal e.g. for timing purposes. The level shifter portion 6 comprises three PMOS transistors 66, 70 & 72, and three NMOS transistors 68, 74 & 76.
[0050] The source terminal of the first PMOS transistor 66 is coupled to the first node 34. The gate terminal of the first PMOS transistor 66 is coupled to the gate terminal of the first NMOS transistor 68 and to the fourth node 56. The drain terminal of the PMOS transistor 66 is coupled to the drain terminal of the first NMOS transistor 68. The source terminal of the first NMOS transistor 68 is coupled to the ground rail V.sub.ss 14.
[0051] The source terminals of the second and third PMOS transistors 70 & 72 are coupled to the positive voltage supply rail V.sub.DDD 60. The PMOS transistors second and third 70 & 72 are cross-coupled, therefore the gate terminal of the second PMOS transistor 70 is coupled to the drain terminal of the third PMOS transistor 72, and the gate terminal of the third PMOS transistor 72 is coupled to the drain terminal of the second PMOS transistor 70. The drain terminal of the second PMOS transistor 70 is coupled to the drain terminal of the second NMOS transistor 74, and to the clock signal output 64. The gate terminal of the second NMOS transistor 74 is coupled to the drain terminals of the first PMOS transistor 66 and the first NMOS transistor 68. The source terminal of the second NMOS transistor 74 is coupled to the ground rail V.sub.ss 14. The drain terminal of the third PMOS transistor 72 is coupled to the drain terminal of the third NMOS transistor 76. The gate terminal of the third NMOS transistor 76 is coupled to the fourth node 56. The source terminal of the third NMOS transistor 76 is coupled to the ground rail V.sub.ss 14.
[0052] The first and second PMOS transistors 20 & 22 of the bias circuit portion 2 are matched, with a multiplication factor (M-factor) ratio of 1:5 respectively as shown below each transistor, together forming a first matched transistor group 78. The third PMOS transistor 24 of the bias circuit portion 2, the first and second PMOS transistors of the inverter amplifier portion 44, 46 and the first PMOST transistor 66 of the level shifter 6 are also matched, with an M-factor ratio of 2:1:2:≈0.1 respectively as shown below each transistor, together forming a second matched transistor group 80. The corresponding NMOS transistors 30, 32, 48, 50 & 68 are also matched, with an M-factor ratio of 2:3:1:2:≈0.1 respectively, together forming a third matched transistor group 82.
[0053] In this example the second PMOS transistor 46 of the inverter amplifier 4 acts as a first load transistor and the second NMOS transistor 50 of the inverter amplifier 4 acts as a second load transistor. The second PMOS transistor 24 of the bias circuit portion 2 acts as a first replica transistor, the third NMOS transistor 30 of the bias circuit portion 2 acts as a second replica transistor and the first node 34 is therefore a node connecting the first replica transistor and the first load transistor. The second PMOS transistor 46 and the second NMOS transistor 50 of the inverter amplifier 4 together act as a current branch of the load circuit portion that is replicated in the bias circuit portion 2 (i.e. a replicated current branch of the load circuit portion).
[0054] Operation of the sinusoid-to-square wave buffer 1 will now be described in more detail. The bias circuit portion 2 biases the second PMOS transistor 46 and the second NMOS transistor 50 of the inverter amplifier with a bias current equal to I.sub.bias by adjusting the voltage V.sub.reg at the first node 34. The voltage V.sub.reg at the first node 34, provided by the bias circuit portion 2, provides a clean voltage supply to the inverter amplifier portion 4 thereby isolating it from the potentially noisy positive voltage supply rail VDDA 10. Inverter amplifiers typically suffer from a poor power supply rejection ratio (PSRR). This means that the noise level in the output voltage of an inverter amplifier is highly dependent on the noise level in the supply voltage provided thereto. It is therefore important to provide a clean voltage supply to the inverter amplifier portion 4 in order for it to output a low-noise voltage signal. It is also important to provide a controlled bias current to the inverter amplifier portion 4 in order to achieve consistent performance across PVT variations.
[0055] The way in which the bias circuit portion 2 provides a low-noise voltage supply V.sub.reg at the first node 34 and a controlled bias current equal to I.sub.bias to the transistors 46 & 50 of the inverter amplifier portion 4 will now be described in detail. The third PMOS and NMOS transistors 24 & 30 of the bias circuit portion 2 replicate the second PMOS and NMOS transistors 46 & 50 of the inverter amplifier portion 4, and the transistors first and second PMOS transistors 20, 22 and the second NMOS transistor 28 of the bias circuit portion 2 act as a feedback loop to control the voltage V.sub.reg at the first node 34 such that the second PMOS transistor 24 of the bias circuit 2 conducts a current equal to I.sub.bias. This feedback loop also functions as a voltage regulator by counteracting variations in the voltage V.sub.reg at the first node 34 generated as a result of variations in the positive voltage supply rail V.sub.DDA 10.
[0056] The current I.sub.bias flows through the diode-connected second and third NMOS transistors 26 and 30 of the bias circuit 2. The 2:3 M-factor ratio between the third and fourth NMOS transistors 30 and 32 respectively of the bias circuit 2 thereby causes a current equal to 1.5xI.sub.bias to flow through the transistor 32, drawn from the second node 38 at which the voltage is equal to V.sub.D.
[0057] The third PMOS transistor 24 of the bias circuit 2 and the second PMOS transistor 46 of the inverter amplifier 4 are matched as previously described and have an M-factor ratio of 2:2, and therefore have equal gate-source voltages (V.sub.gs). The reasons for this equal gate-source voltage (V.sub.gs) will be described in further detail below with reference to the operation of the inverter amplifier portion 4.
[0058] It can therefore be seen that the current through the second PMOS transistor 46 of the inverter amplifier is equal to is equal to the current through the third PMOS transistor 24 of the bias circuit 2, which current may be called l.sub.x. However due to the 2:1 M-factor ratio between the third PMOS transistor 24 of the bias circuit and the first PMOS transistor 44 of the inverter amplifier, the current through the latter transistor 44 is equal to (1/2)I.sub.x=0.5l.sub.x. The current through the first PMOS transistor 66 of the level shifter 6 is negligible, as the M-factor ratio between the third PMOS transistor 24 of the bias circuit and that transistor 66 is 2:≈0.1. As the second PMOS transistor 22 of the bias circuit supplies current to each of the transistors 24, 44, 46 & 66, the current through the second PMOS transistor 22 of the bias circuit is equal to (1+0.5+1)l.sub.x≈2.5l.sub.x, ignoring the negligible current through the level shifter transistor 66.
[0059] As the first and second PMOS transistors 20 and 22 of the bias circuit have a 1:5 M-factor ratio, the current through the first PMOS transistor 20 is equal to (2.5/5).sub.x=0.5l.sub.x. The current through the first NMOS transistor 28 is therefore also equal to 0.5l.sub.x. The total current entering the third node 38 (at which the voltage is equal to V.sub.D) is equal to the sum of the currents through the second PMOS transistor 24 and the first NMOS transistor 28, and the total current leaving the third node 38 is equal to the current through the transistor 32. The total current entering the node 38 is therefore equal to (1+0.5)l.sub.x=1.5l.sub.x, and the total current leaving the third node 38 is equal to 1.5I.sub.bias. As the total current entering a node must equal the total current leaving the node, this gives the result that 1.5I.sub.x=1.5I.sub.bias, and therefore l.sub.x=I.sub.bias. Therefore the current through the third PMOS transistor 24 of the bias circuit, and consequently the bias current provided to the second PMOS transistor 46 of the inverter amplifier portion 4, is equal to I.sub.bias.
[0060] The M-factor ratio between the first and second NMOS transistors 28, 26 of the bias circuit does not directly influence the bias current provided by the bias circuit portion 2 to the inverter amplifier portion 4, but sets the voltage V.sub.D at the third node 38. However, in this example the M-factor ratio between these transistors 26 and 28 is set to be 2:1. This causes the voltage V.sub.D at the third node 38 to be equal to the voltage V.sub.G at the second node 36, which in turn is equal to the mid-point output voltage of the inverter amplifier portion 4.
[0061] The output impedance of the bias circuit portion 2 at the first node 34 (at which the voltage is equal to V.sub.reg) is not negligible as it would be in an ideal voltage regulator, but is instead approximately equal to 1/(g.sub.m24(1+K)), where K is equal to the M-factor ratio between the first and second PMOS transistors 20 and 22 of the bias circuit and g.sub.m24 is equal to the conductance of the third PMOS transistor 24. As a result of this, in order for the bias circuit portion 2 to be most useful, the load current must be known and controlled. This is the case in the sinusoid-to-square wave buffer 1 implementation shown in
[0062] In order properly to adapt the bias circuit portion 2 to a different inverter amplifier load, the DC load current must be known and its variation must remain within a certain range depending on the design sizing. Any extra/less load current provided in the inverter amplifier portion 4 would cause current to be taken from/given to the third PMOS transistor 24 respectively, and thus changes to the load current would alter the bias point of the bias circuit 2. Additionally, the non-negligible output impedance of 1/(g.sub.m24(1+K)) leads to changes in the load current altering the voltage V.sub.reg at the first node 34. However, the bias circuit portion 2 can be adapted to a new load (with a known DC load current) by changing the input current I.sub.bias provided by the current source 16, or by changing the M-factor ratio between the transistors 20 and 22.
[0063] Inverter amplifiers are particularly susceptible to changes in bias voltage when compared to other applications for which the bias circuit portion 2 may be suitable, e.g. non-inverting amplifiers, buffer amplifiers, etc. In order to adapt the bias circuit portion 2 to a different application (i.e. other than an inverter amplifier), the input current I.sub.bias provided at the current source input 16 and the M-factor ratio between the first and second PMOS transistors 20 and 22 of the bias circuit simply need to be selected such that the voltage V.sub.reg generated at the first node 34 is suitable for the selected application, and that the bias circuit portion 2 provides a suitable current for the selected application's load current range.
[0064] Operation of the inverter amplifier portion 4 will now be described in more detail. The inverter amplifier portion 4 receives a sinusoidal input signal V.sub.in 42, at the gate terminals of the second PMOS and NMOS transistors 46 & 50. The capacitor 54 provides AC-coupling between the inverter amplifier portion 4 and the signal input 42 by filtering out unwanted DC components. The diode-connected first PMOS and NMOS transistors 44 & 48 provide a DC bias voltage to the gate terminals of the second transistors 46 & 50 via the resistor 52 that is equal to the voltage V.sub.G at the second node 36. Ideally, the voltage V.sub.G at the second node 36 would be directly coupled to the resistor 52, thereby causing the DC bias voltage provided to the inverter amplifier formed by the second transistors 46 & 50 to be exactly equal to V.sub.G, thus causing the gate-source voltages of the transistors 24 & 46 to be equal. However, such an arrangement would result in the sinusoidal input signal V.sub.in propagating into the bias circuit portion 2, disturbing operation. Instead, the diode-connected first transistors 44 & 48, which are arranged as an inverter in a negative feedback configuration, replicate the third PMOS transistor 24 and the third NMOS transistor 30 of the bias circuit portion so as to generate a voltage between their drain terminals that is equal to the voltage V.sub.G, at the second node 36. This means that the DC bias voltage provided to the gate terminals of the second transistors 46 & 50 via the resistor 52 is equal to the voltage V.sub.G at the second node 36, but any sinusoidal input signal V.sub.in propagating back through the resistor 52 does not disturb the operation of the bias circuit 2. Thus, the gate-source voltages (V.sub.gs) of the third PMOS transistor 24 of the bias circuit 2 and the second PMOS transistor 46 of the inverter amplifier 4 are equal.
[0065] The voltage at the gate terminals of the second transistors 46 & 50 therefore oscillates around the DC bias voltage provided by the first transistors 44 & 48 as a result of the superposition of the DC bias voltage and the AC-coupled sinusoidal input signal 42. The oscillating voltage at the gate terminals of the PMOS transistor 46 and the NMOS transistor 50 cause these transistors to alternately switch on and off, thereby driving the voltage V.sub.amp at the fourth node 56 alternately between the voltage V.sub.reg at the first node 34 and the voltage V.sub.ss at the ground rail 14. When the voltage at the gate terminals of the second transistors 46 and 50 is above the DC bias voltage, the NMOS transistor 50 is switched on and the voltage V.sub.amp at the fourth node 56 is driven to ground (V.sub.ss). When the voltage at the gate terminals of the second transistors 46 and 50 is below the DC bias voltage, the PMOS transistor 46 is switched on and the voltage V.sub.amp at the fourth node 56 is driven to V.sub.reg at the first node 34. When the voltage at the gate terminals of the second transistors 46 and 50 is near to the mid-point (i.e. the DC bias voltage), the transistors 46 & 50 function as a high-gain inverter amplifier. As a result, the voltage V.sub.amp at the fourth node 56 is a square wave oscillating between ground (V.sub.ss) and V.sub.reg at the first node 34 with the same frequency as the sinusoidal input signal V.sub.in 42 but with a phase difference of 180° (i.e. inverted).
[0066] The inverter amplifier portion 4 is run in open-loop (i.e. there is no feedback provided between the fourth node 56 and the gate terminals of the second transistors 46 & 50). This ensures that the inverter amplifier portion 4 converts the sinusoidal input signal V.sub.in 42 into a square wave voltage signal V.sub.amp at the node 56 with maximum gain.
[0067] Operation of the level shifter portion 6 will now be described in more detail. The amplitude of the square wave signal V.sub.amp at the fourth node 56, as described above, set by the internal voltage V.sub.reg at the first node 34 and therefore needs to be level-shifted to match a known system voltage domain in order to be useful. The level-shifter portion 6 performs this function by shifting the square wave signal V.sub.amp at the fourth node 56 to a known system voltage level V.sub.DDD provided by the second positive voltage supply rail 60. The voltage V.sub.DDD at the second supply rail 60 may be any suitable known system voltage, including by not limited to 1.8V, 3.3V, 5V, etc.
[0068] The square wave signal V.sub.amp at the fourth node 56 is fed to the gate terminal of the third NMOS transistor 76 of the level shifter 6. It is also fed to the gate terminals of the first PMOS and NMOS transistors 66 & 68. These transistors 66 & 68 act as an inverter in the same way as the second transistors 46 & 50 of the inverter amplifier portion 4, and therefore invert the square wave signal V.sub.amp at the fourth node 56. The inverted signal is then fed to the gate terminal of the second NMOS transistor 74. When the square wave signal V.sub.amp at the fourth node 56 is at V.sub.reg (i.e. HIGH), the third NMOS transistor 76 is switched on, and the second NMOS transistor 74 (which is fed an inverted version of the signal V.sub.amp) is switched off. Conversely, when the signal V.sub.amp is at ground (V.sub.ss) (i.e. LOW), the third NMOS transistor 76 is switched off, and the second NMOS transistor 74 is switched on. When this happens, the CK.sub.out signal 64 output by the level shifter portion 6 is driven to ground (V.sub.ss). This causes the cross-coupled second PMOS transistor 72 to switch on, causing the voltage at the drain terminal of the second PMOS transistor 72 to be driven to the voltage V.sub.DDD at the second positive voltage supply rail 58, thereby causing the other cross-coupled first PMOS transistor 70 to switch off.
[0069] When the third NMOS transistor 76 is switched on (i.e. when the signal V.sub.amp is HIGH, and therefore the second NMOS transistor 74 is switched off), the voltage at the drain terminal of the second PMOS transistor 72 is driven to ground (V.sub.ss). This causes the cross-coupled first PMOS transistor 70 to switch on, thereby driving the CK.sub.out signal 64 to V.sub.DDD. Hence the signal CK.sub.out 64 output by the level shifter portion 6 is a square wave signal with the same characteristics (e.g. frequency, phase, etc.) as the square wave signal V.sub.amp at the fourth node 56 but level shifted from the internal voltage V.sub.reg to the more useful known system voltage V.sub.DDD 60 .
[0070] It will be appreciated by those skilled in the art that the invention has been illustrated by describing one or more specific embodiments thereof, but is not limited to these embodiments; many variations and modifications are possible within the scope of the appended claims.