Diode array, arrangement, and system

Abstract

A diode array with at least two image elements. The diode array includes a distribution transistor as well as a feed line for receiving a reference current and a first supply terminal coupled to the distribution transistor for supplying the distribution transistor. A diode and an input transistor are provided for each image element, each of which is coupled to the diode for supplying the diode. The distribution transistor forms a distribution current mirror with the respective input transistor of at least two image elements.

Claims

1. A diode array with at least two successive image elements, wherein the diode array comprises a feed line for receiving a reference current and a first and a second supply terminal, a diode, an input current mirror, a bifurcation transistor and a supply transistor are provided for each image element, the bifurcation transistor forming with the supply transistor a supply current mirror which is coupled to the diode in order to supply the diode, the diode array comprises at least one output transistor disposed between two successive image elements and forming, with the bifurcation transistor of a first of the two successive image elements, an output current mirror coupled to the input current mirror of a successive second of the two successive image elements for supplying said input current mirror, wherein for supplying the input current mirror of the first of the successive image elements, said input current mirror is coupled to the feed line and to the first supply terminal.

2. The diode array according to claim 1, in which the respective input current mirror comprises an input transistor and an output transistor, wherein the input transistor of the first of the two image elements is coupled via its drain electrode to the feed line, and the input transistor of subsequent image elements is coupled via its drain electrode to a drain electrode of the output transistor of a preceding image element, the input transistor of the first or the subsequent image elements is coupled via its source electrode to the first supply terminal and via its control electrode to its drain electrode, the output transistor is coupled via its drain electrode to a drain electrode of the bifurcation transistor, via its source electrode to the first supply terminal, and via its control electrode to the control electrode of the input transistor, the bifurcation transistor is coupled via its source electrode to the second supply terminal and via its control electrode to its drain electrode, the supply transistor is coupled via its drain electrode to a first electrode of the diode, via its source electrode to the second supply terminal and via its control electrode to the control electrode of the bifurcation transistor, a second electrode of the diode is coupled to the first supply terminal, and the output transistor is coupled via its source electrode to the second supply terminal and via its control electrode to the control electrode of the bifurcation transistor.

3. An array comprising a plurality of image elements, wherein the image elements are arranged at least partially in at least one diode array according to claim 1, wherein the at least one diode array comprises a respective feed line.

Description

(1) Further advantages, advantageous embodiments and further embodiments result from the embodiment examples described below in connection with the figures.

(2) It show:

(3) FIG. 1 a voltage referenced array and its wiring,

(4) FIG. 2a a current referenced array and its wiring,

(5) FIG. 2b a schematic representation of a cascaded current mirror bank for current referencing according to FIG. 2a,

(6) FIG. 3a a first embodiment of a diode array for use in the system shown in FIG. 2a,

(7) FIG. 3b is a top view of a second embodiment of a diode array for use in the system shown in FIG. 2a,

(8) FIG. 4 a third embodiment of a diode array for use in the system shown in FIG. 2a,

(9) FIG. 5a a first embodiment of a wiring of the diode array shown in FIG. 4 in the system shown in FIG. 2a,

(10) FIG. 5b a second embodiment of a wiring of the diode array shown in FIG. 4 in the system shown in FIG. 2a, and

(11) FIG. 6 shows a fourth embodiment of two consecutive diode arrays for use in the system shown in FIG. 2a.

(12) Elements that are identical, similar or have the same effect are given the same reference signs in the figures. The figures and the proportions of the elements shown in the figures are not to be regarded as to scale. Rather, individual elements may be shown exaggeratedly large for better representability and/or for better comprehensibility. Dashed outlines indicate a functional unit of the elements arranged therein.

(13) In arrays such as LED arrays or in image sensors, active circuit parts are often used within an image element. The image elements usually require high-precision references, i.e. reference currents or voltages. The reference can, for example, refer to a bandgap of a pn junction; ideally, the same reference is available to each image element. However, reference generation within the image elements makes uniform referencing (so-called matching) across all image elements of the array difficult.

(14) FIG. 1 shows a system 1 for supplying an external reference voltage V.sub.ref to an LED array 30. The LED array has n columns and m rows of image elements 5a, 5b arranged in a matrix, each column being coupled to an output line 8 of a bandgap reference 2a for supplying the corresponding image elements 5a, 5b. Thus, only one output line 8 is required per column. However, the system 1 may be subjected to several error influences in the process, such as a mismatch of transistors installed in the respective image elements as current sources. Temperature differences, local ground or supply differences also strongly influence the system 1.

(15) To avoid these error effects, current-based referencing is preferable. FIG. 2a shows a system 1 for supplying the LED array 30 with an external reference current I.sub.ref, in which each image element 5a, 5b is coupled to an output line 8 of a reference current source 20. For this purpose, the bandgap reference 2a is coupled to an operational amplifier with a downstream resistor as a voltage-to-current converter 2b as well as a current mirror bank 2c. Since the reference current I.sub.ref is independent of local supply voltage levels, and transistors of the current mirror bank are each locally adjacent, this variant is less susceptible to the above-mentioned sources of error, but requires a great deal of wiring. Especially in arrays 30 with a large number of image elements 5a, 5b of small size (for example <40 m, in particular 10 m), the space for feed lines for the individual image elements 5a, 5b is limited.

(16) FIG. 3a shows a first embodiment of a diode array 3a for use as a subarray in the system 1 shown in FIG. 2a, which helps to keep the wiring effort low and at the same time enables highly accurate referencing of the image elements 5a, 5b.

(17) In this embodiment, the diode array 3a shown comprises two adjacent image elements 5a, 5b of the array 30. In other embodiments, the diode array 3a may also comprise more than two adjacent image elements 5a, 5b, in particular four, eight or sixteen. For both image elements 5a, 5b, the diode array 3a has only a single feed line 7, which is to be coupled to the output line 8 of the reference current source 20 for supplying the image elements 5a, 5b. On the input side, the diode array 3a has a distribution transistor .sub.TD whose drain electrode T.sub.D-D is connected to the feed line 7 for receiving the reference current I.sub.ref. A control electrode T.sub.D-G of the distribution transistor T.sub.D is connected to the drain electrode T.sub.D-D to form a distribution terminal V for the image elements 5a, 5b of the diode array 3a. Finally, a source electrode T.sub.D-S of the distribution transistor .sub.TD is connected to a ground terminal 9a of the array 30. A supply voltage terminal may also fall under the ground terminal 9a; in this context, the diode array 3a may be operated in the opposite current direction complementary to this embodiment, in which the n-channel MOSFETs described below are replaced by p-channel MOSFETs and vice versa.

(18) The two image elements 5a, 5b each have an input transistor T.sub.I on the input side, the control electrode T.sub.I-G of which is connected to the distribution terminal V. A source electrode of the input transistor T.sub.T is in turn connected to the ground terminal 9a of the array 30. On the output side, the input transistor T.sub.I essentially provides the reference current I.sub.ref supplied to the diode array 3a via the feed line 7 through its drain electrode T.sub.D-D by this interconnection. The distribution transistor T.sub.D thus forms a current mirror with the respective input transistor T.sub.I of the two image elements 5a, 5b in each case, which is referred to below as the distribution current mirror S.sub.D and is indicated by the dashed or dash-dotted box in FIG. 3a.

(19) The reference current I.sub.ref provided on the output side with respect to the distribution current mirror S.sub.D is supplied to a respective diode D associated with the corresponding image element 5a, 5b via its first electrode D.sub.1. A second electrode D.sub.2 of the diode D is connected to the ground terminal 9a.

(20) In this embodiment, a supply current mirror .sub.SS is connected downstream of the distribution current mirror .sub.SD for each image element 5a, 5b, via which the reference current I.sub.ref is supplied to the corresponding diode D. The supply current mirror .sub.SS comprises a bifurcation transistor .sub.TF on the input side and a supply transistor T.sub.S on the output side, which are each connected with their source electrodes T.sub.F-S, T.sub.S-S to a supply voltage terminal 9b. Here, the transistors T.sub.D, T.sub.I associated with the distribution current mirror S.sub.D are n-channel MOSFETs and the transistors T.sub.F, T.sub.S associated with the supply current mirror S.sub.S are p-channel MOSFETs. In other embodiments, the distribution current mirror .sub.SD per image element 5a, 5b may also be directly connected to the first electrode D.sub.2 of the corresponding diode D, the second electrode D.sub.2 of which is then connected to the supply voltage terminal 9b. By way of example, the transistors T.sub.D, T.sub.I associated with the distribution current mirror .sub.SD are then designed as p-channel MOSFETs.

(21) The transistors T.sub.D, T.sub.I, T.sub.F, T.sub.S assigned to the respective current mirrors S.sub.D, S.sub.S can in particular be arranged locally close to each other in order to keep a mismatch error low. Preferably, the transistors T.sub.D, T.sub.I, T.sub.F, T.sub.S assigned to the respective current mirrors S.sub.D, S.sub.S are formed according to the common-centroid layout, for example to compensate for a gradient in the gate oxide. In this regard, reference is made to the statements of Daniel Payne in A Review of an Analog Layout Tool called HiPer DevGen and Nurahmad Omar in Automated Layout Synthesis Tool for Op-Amp, the disclosure content of which is hereby incorporated by reference in its entirety.

(22) In particular, the layout of the individual image elements 5a, 5b can be mirrored as shown in FIG. 3b. In this second embodiment, the distribution transistor T.sub.D is arranged centrally with respect to four image elements 5a, 5b, 5c, 5d arranged in a matrix, each with an LED D1, D2, D3, D4, wherein an arrangement of the individual components of the image elements 5a, 5b, 5c, 5d is respectively mirrored with respect to a vertical axis along a column of the matrix by the distribution transistor T.sub.D and with respect to a horizontal axis along a row of the matrix by the distribution transistor T.sub.D.

(23) The structure of the diode array 3a shown in the embodiments of FIGS. 3a and 3b can also be referred to as input sharing and does not introduce any additional mismatch error. The number of feed lines 7 for wiring the image elements 5a, 5b, 5c, 5d can be reduced by a factor of f where f corresponds to the number of image elements 5a, 5b, 5c, 5d each assigned to a distribution transistor T.sub.D.

(24) FIG. 4 shows a third embodiment of a diode array 3c for use as a subarray in the system 1 shown in FIG. 2a, which also helps to keep wiring costs low while enabling highly accurate referencing of the image elements 5a, 5b.

(25) The diode array 3c differs from the diode array 3a in, among other things, that no central distribution transistor T.sub.D is arranged between the image elements 5a, 5b. Instead, a feed line 7 of the diode array 3c is directly connected to a first image element 5a for coupling to an output line 8 of the reference current source 20. The first image element 5a is thereby connected on the output side via an inheritance line 87 to a subsequent second image element 5b.

(26) The individual image elements 5a, 5b are assigned an input current mirror .sub.SI for this purpose, to which a corresponding current is supplied via the feed line 7 or the inheritance line 87. The first image element 5a is furthermore assigned an output transistor T.sub.O for this purpose, to which the input current mirror S.sub.I of the second image element 5b is connected via the inheritance line 87. In the embodiment shown, the second image element 5b is also assigned an output transistor .sub.TO for supplying subsequent image elements, which can be dispensed with in other embodiments.

(27) The input current mirror S.sub.I has an input transistor T.sub.E and an output transistor T.sub.A, which together are arranged to provide the reference current I.sub.ref supplied via the feed line 7 at a drain electrode T.sub.E-D of the input transistor T.sub.E on the output side at a drain electrode T.sub.A-D of the output transistor T.sub.A.

(28) Analogous to the first embodiment, the individual image elements 5a, 5b furthermore have a supply current mirror S.sub.S connected downstream of the input current mirror S.sub.S, via which the reference current I.sub.ref is fed to the corresponding diode D. In addition, however, the bifurcation transistor T.sub.F has its control electrode T.sub.E-G connected to a control electrode R.sub.F-G of the output transistor T.sub.O and forms an output current mirror S.sub.O with the latter (indicated by the two boxes with dash dots). The output current mirror so is arranged to provide the reference current I.sub.ref supplied via the drain electrode T.sub.A-D of the output transistor T.sub.A of the input current mirror S.sub.I to a drain electrode T.sub.F-D of the bifurcation transistor T.sub.F on the output side at a drain electrode T.sub.o-D of the output transistor T.sub.o.

(29) In the third embodiment, the transistors T.sub.E, T.sub.A associated with the input current mirror si are n-channel MOSFETs and the transistors T.sub.F, T.sub.S, T.sub.O associated with the supply current mirror S.sub.S and the output current mirror S.sub.O, respectively, are p-channel MOSFETs. In other embodiments, instead of driving the diodes D on the anode side, if the diodes D are each arranged rotated and the ground terminal 9a is designed as a supply voltage terminal and the supply voltage terminal 9b is designed as a ground terminal, for example, current for driving the respective diode D can be drawn from the cathode with a corresponding low side driver. In this case, the transistors T.sub.E, T.sub.A are p-channel MOSFETs and the transistors T.sub.F, T.sub.S, T.sub.O are n-channel MOSFETs.

(30) In an advantageous manner, a number of output lines 8 for supplying the diode array 3c can thus be kept low. The reference current I.sub.ref arriving via the feed line 7 is first mirrored (here from n to p) and then mirrored in parallel into the load and via an additional mirror transistor into the next image element. In extreme cases, a single reference line can thus be used to mirror an entire column (or row) of m (resp. n) image elements can be served. The mismatch error of the then used m (resp. n) mirrors then used spreads out to the last image element, however, in particular a convolution of the static distribution takes place in each mirror, hence the Gaussian widens out. As shown in FIGS. 5a and 5b, respectively, a compromise between number of lines and accuracy has to be made. FIG. 5a shows a first embodiment of a wiring of the diode array 3c shown in FIG. 4 in the system 1 according to FIG. 2a, where one output line 8 supplies all image elements of a column. In a second embodiment (FIG. 5b), on the other hand, only two successive image elements are supplied with an output line 8.

(31) The compromise solution to be selected can be made dependent in particular on the available space.

(32) Finally, on the basis of FIG. 6, a fourth embodiment example is shown which combines the approaches shown in the preceding embodiment examples. Here, two successive diode arrays 3a, 3b are interconnected in an arrangement 3 for use as a subarray in the system 1 shown in FIG. 2a.

(33) A distribution transistor T.sub.D is assigned to the first diode array 3a, which is connected to the feed line 7 and, analogously to the first and second embodiment examples, supplies the surrounding image elements 5a, 5b, 5c, 5d with the reference current I.sub.ref applied to the feed line 7. In this embodiment, only the image element 5d has an output transistor T.sub.O associated therewith, which is connected via an inheritance line 87 to the distribution transistor T.sub.D of the subsequent second diode array 3b. In other embodiments, a corresponding output transistor T.sub.O may also be assigned to more than one image element 5d, in particular to all image elements 5a, 5b, 5c, 5d, and the arrangement 3 may comprise correspondingly more image elements which are supplied by the same feed line 7. Analogously to the first and second embodiment examples, the image elements 5e, 5f, 5g, 5h located around the distribution transistor T.sub.D of the second diode array 3b are supplied with the reference current I.sub.ref applied to the inheritance line 87.

(34) The inheritance of the reference current I.sub.ref of an image element to an adjacent image element as well as the local sharing of an input current mirror transistor with adjacent image elements (input sharing) can be combined and scaled as shown in the fourth embodiment. Advantageously, this enables high-precision referencing, reduced wiring effort, or wiring of larger arrays at all, with comparatively low hardware effort.

(35) The invention is not limited to these by the description based on the embodiments. Rather, the invention encompasses any new feature as well as any combination of features, which in particular includes any combination of features in the patent claims, even if this feature or combination itself is not explicitly stated in the patent claims or embodiments.

LIST OF REFERENCE SIGNS

(36) 1, 1 System 2a Reference voltage source 2b Voltage-to-current converter 2c, 2c-1, 2c-2, 2c-3 Current mirror bench 20 Reference current source 3 Arrangement 3a, 3b, 3c Diode array 30 Array 5a, 5b, 5c, 5d, 5e, 5f, 5g, 5h Image element 7 Feed line 8 Output line 87 Inheritance line 9a, 9b Supply connection D, D1, D2, D3, D4 Diode D.sub.1, D.sub.2 Electrode S.sub.D Distribution current mirror S.sub.I Input current mirror S.sub.S Supply current level S.sub.O Output current level T.sub.D T Distribution transistor T.sub.I Input transistor T.sub.F Forking transistor T.sub.S Supply transistor T.sub.O Output transistor T.sub.E Input transistor T.sub.A Output transistor T.sub.D-D, T.sub.I-D, T.sub.F-D, T.sub.S-D, T.sub.O-D, T.sub.E-D, T.sub.A-D Drain electrode T.sub.D-S, T.sub.I-S, T.sub.F-S, T.sub.S-S, T.sub.O-S, T.sub.E-S, T.sub.A-S Source electrode T.sub.D-G, T.sub.I-G, T.sub.F-G, T.sub.S-G, T.sub.O-G, T.sub.F-G, T.sub.A-G Control electrode V.sub.ref Reference voltage I.sub.ref Reference current