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NON-VOLATILE MEMORY WITH AUXILIARY SELECT GATE LINE DRIVER

20250022511 ยท 2025-01-16

    Inventors

    Cpc classification

    International classification

    Abstract

    A non-volatile memory with an auxiliary select gate line driver is provided. The array structure of the non-volatile memory comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of non-volatile memory are enhanced.

    Claims

    1. A non-volatile memory, comprising: an array structure connected with a first word line, a second word line, a source line, an erase line, a first auxiliary select gate line, a second auxiliary select gate line and a bit line, and comprising a firs memory cell and a second memory cell, wherein the first memory cell is connected with the first word line, the first auxiliary select gate line, the erase line, the source line and the first bit line, and the second memory cell is connected with the second word line, the second auxiliary select gate line, the erase line, the source line and the first bit line; a word line decoder generating a decoded signal; a word line driver receiving the decoded signal and connected with the first word line and the second word, wherein the word line driver activates one of the first word line and the second word according to the decoded signal; an auxiliary select gate line driver receiving a mode signal and the decoded signal, wherein the auxiliary select gate line driver is connected with the first auxiliary select gate line and the second auxiliary select gate line; a bit line selector connected with the first bit line; and a sensing circuit connected with the bit line selector, wherein when a program action is performed, the first memory cell is determined as a selected memory cell, and the second memory cell is determined as an unselected memory cell, wherein according to the mode signal, the first auxiliary select gate line and the second auxiliary select gate line are not driven by the auxiliary select gate line driver in a first phase of a first program mode; a first driving voltage is provided to the first auxiliary select gate line by the auxiliary select gate line driver in a second phase of the first program mode; the second auxiliary select gate line is not driven by the auxiliary select gate line driver in the second phase of the first program mode; and the first driving voltage is a positive voltage, wherein according to the mode signal, a second driving voltage is provided to the first auxiliary select gate line and the second auxiliary select gate line by the auxiliary select gate line driver in a first phase of a second program mode; the first driving voltage is provided to the first auxiliary select gate line by the auxiliary select gate line driver in a second phase of the second program mode; the second auxiliary select gate line is not driven by the auxiliary select gate line driver in the second phase of the second program mode; and the second driving voltage is a negative voltage.

    2. The non-volatile memory as claimed in claim 1, wherein the first memory cell comprises: a first select transistor, wherein a source terminal of the first select transistor is connected with the source line, a gate terminal of the first select transistor is connected with the first word line; a first floating gate transistor, wherein a source terminal of the first floating gate transistor is connected with a drain terminal of the first select transistor, and a drain terminal of the first floating gate transistor is connected with the first bit line; a first capacitor, wherein a first terminal of the first capacitor is connected with a floating gate of the first floating gate transistor, and a second terminal of the first capacitor is connected with the erase line; and a second capacitor, wherein a first terminal of the second capacitor is connected with the floating gate of the first floating gate transistor, and a second terminal of the second capacitor is connected with the first auxiliary select gate line.

    3. The non-volatile memory as claimed in claim 2, wherein the second memory cell comprises: a second select transistor, wherein a source terminal of the second select transistor is connected with the source line, a gate terminal of the second select transistor is connected with the second word line; a second floating gate transistor, wherein a source terminal of the second floating gate transistor is connected with a drain terminal of the second select transistor, and a drain terminal of the second floating gate transistor is connected with the first bit line; a third capacitor, wherein a first terminal of the third capacitor is connected with a floating gate of the second floating gate transistor, and a second terminal of the third capacitor is connected with the erase line; and a fourth capacitor, wherein a first terminal of the fourth capacitor is connected with the floating gate of the second floating gate transistor, and a second terminal of the fourth capacitor is connected with the second auxiliary select gate line.

    4. The non-volatile memory as claimed in claim 1, wherein according to the mode signal, the first auxiliary select gate line and the second auxiliary select gate line are not driven by the auxiliary select gate line driver in a first read mode, wherein according to the mode signal, a third driving voltage is provided to the first auxiliary select gate line and the second auxiliary select gate line by the auxiliary select gate line driver in a second read mode, wherein the third driving voltage is a positive voltage.

    5. The non-volatile memory as claimed in claim 4, wherein according to the mode signal, the first auxiliary select gate line and the second auxiliary select gate line are not driven by the auxiliary select gate line driver in a first erase mode, wherein according to the mode signal, a fourth driving voltage is provided to the first auxiliary select gate line and the second auxiliary select gate line by the auxiliary select gate line driver in a second erase mode, wherein the third driving voltage is a negative voltage.

    6. The non-volatile memory as claimed in claim 5, wherein according to the mode signal, a fifth driving voltage is provided to the first auxiliary select gate line by the auxiliary select gate line driver in a third erase mode, a sixth driving voltage is provided to the second auxiliary select gate line by the auxiliary select gate line driver in the third erase mode; wherein a storage state of the first memory cell is an erase state, and a storage state of the second memory cell is not changed; wherein the fifth driving voltage is a negative voltage, and the sixth driving voltage is a positive voltage.

    7. The non-volatile memory as claimed in claim 6, wherein the auxiliary select gate line driver comprises: a pull-up controller receiving the decoded signal and the mode signal, and generating a first control signal and a second control signal; a pull-down controller receiving the decoded signal and the mode signal, and generating a third control signal and a fourth control signal; a first driving element comprising a first P-type transistor and a first N-type transistor, wherein a source terminal of the first P-type transistor receives a first supply voltage, a gate terminal of the first P-type transistor receives the first control signal, and a drain terminal of the first P-type transistor is connected with the first auxiliary select gate line, wherein a drain terminal of the first N-type transistor is connected with the drain terminal of the first P-type transistor, a gate terminal of the first N-type transistor receive the third control signal, and a source terminal of the first N-type transistor receives a second supply voltage; and a second driving element comprising a second P-type transistor and a second N-type transistor, wherein a source terminal of the second P-type transistor receives a third supply voltage, a gate terminal of the second P-type transistor receives the second control signal, and a drain terminal of the second P-type transistor is connected with the second auxiliary select gate line, wherein a drain terminal of the second N-type transistor is connected with the drain terminal of the second P-type transistor, a gate terminal of the second N-type transistor receive the fourth control signal, and a source terminal of the second N-type transistor receives a fourth supply voltage.

    8. The non-volatile memory as claimed in claim 7, wherein in the third erase mode, the first supply voltage is a control voltage, the second supply voltage is a fifth driving voltage, the third supply voltage is a sixth driving voltage, the fourth supply voltage is a ground voltage, the first control signal is the control voltage, each of the second control signal, the third control signal and the fourth control signal is the ground voltage, the first auxiliary select gate line outputs the fifth driving voltage, and the second auxiliary select gate line outputs the sixth driving voltage.

    9. The non-volatile memory as claimed in claim 5, wherein the auxiliary select gate line driver comprises: a pull-up controller receiving the decoded signal and the mode signal, and generating a first control signal and a second control signal; a pull-down controller receiving the decoded signal and the mode signal, and generating a third control signal and a fourth control signal; a first driving element comprising a first P-type transistor and a first N-type transistor, wherein a source terminal of the first P-type transistor receives a first supply voltage, a gate terminal of the first P-type transistor receives the first control signal, and a drain terminal of the first P-type transistor is connected with the first auxiliary select gate line, wherein a drain terminal of the first N-type transistor is connected with the drain terminal of the first P-type transistor, a gate terminal of the first N-type transistor receive the third control signal, and a source terminal of the first N-type transistor receives a second supply voltage; and a second driving element comprising a second P-type transistor and a second N-type transistor, wherein a source terminal of the second P-type transistor receives the first supply voltage, a gate terminal of the second P-type transistor receives the second control signal, and a drain terminal of the second P-type transistor is connected with the second auxiliary select gate line, wherein a drain terminal of the second N-type transistor is connected with the drain terminal of the second P-type transistor, a gate terminal of the second N-type transistor receive the fourth control signal, and a source terminal of the second N-type transistor receives the second supply voltage.

    10. The non-volatile memory as claimed in claim 9, wherein in the first phase of the first program mode, the first supply voltage is a first program voltage, the second supply voltage is a ground voltage, each of the first control signal, the second control signal, the third control signal and the fourth control signal is the first program voltage, the first auxiliary select gate line outputs the ground voltage, and the second auxiliary select gate line outputs the ground voltage.

    11. The non-volatile memory as claimed in claim 10, wherein in the second phase of the first program mode, the first supply voltage is the first drive voltage, the second supply voltage is the ground voltage, the first control signal is the ground voltage, the second control signal is the first driving voltage, the third control signal is the ground voltage, the fourth control signal is the first driving voltage, the first auxiliary select gate line outputs the first driving voltage, and the second auxiliary select gate line outputs the ground voltage.

    12. The non-volatile memory as claimed in claim 9, wherein in the first phase of the second program mode, the first supply voltage is a control voltage, the second supply voltage is the second driving voltage, the first control signal is the control voltage, the second control signal is the control voltage, the third control signal is a ground voltage, the fourth control signal is the ground voltage, the first auxiliary select gate line outputs the second driving voltage, and the second auxiliary select gate line outputs the second driving voltage.

    13. The non-volatile memory as claimed in claim 12, wherein in the second phase of the second program mode, the first supply voltage is the first driving voltage, the second supply voltage is the ground voltage, the first control signal is the ground voltage, the second control signal is the first driving voltage, the third control signal is the ground voltage, the fourth control signal is the first driving voltage, the first auxiliary select gate line outputs the first driving voltage, and the second auxiliary select gate line outputs the ground voltage.

    14. The non-volatile memory as claimed in claim 9, wherein in the first read mode, the first supply voltage is a system operation voltage, the second supply voltage is a ground voltage, each of the first control signal, the second control signal, the third control signal and the fourth control signal is the system operation voltage, the first auxiliary select gate line outputs the ground voltage, and the second auxiliary select gate line outputs the ground voltage.

    15. The non-volatile memory as claimed in claim 9, wherein in the second read mode, the first supply voltage is the third driving voltage, the second supply voltage is a ground voltage, each of the first control signal, the second control signal, the third control signal and the fourth control signal is the ground voltage, the first auxiliary select gate line outputs the third driving voltage, and the second auxiliary select gate line outputs the third driving voltage.

    16. The non-volatile memory as claimed in claim 9, wherein in the first erase mode, the first supply voltage is a system operation voltage, the second supply voltage is a ground voltage, each of the first control signal, the second control signal, the third control signal and the fourth control signal is the system operation voltage, the first auxiliary select gate line outputs the ground voltage, and the second auxiliary select gate line outputs the ground voltage.

    17. The non-volatile memory as claimed in claim 9, wherein in the second erase mode, the first supply voltage is a control voltage, the second supply voltage is the fourth driving voltage, the first control signal is the control voltage, the second control signal is the control voltage, the third control signal is a ground voltage, the fourth control signal is the ground voltage, the first auxiliary select gate line outputs the fourth driving voltage, and the second auxiliary select gate line outputs the fourth driving voltage.

    Description

    BRIEF DESCRIPTION OF THE DRAWINGS

    [0017] The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

    [0018] FIGS. 1A and 1B (prior art) schematically illustrate associated bias voltages for performing a program action on a memory cell of a conventional non-volatile memory cell;

    [0019] FIGS. 1C and 1D (prior art) schematically illustrate associated bias voltages for performing a read action on the memory cell of the conventional non-volatile memory cell;

    [0020] FIG. 1E (prior art) schematically illustrates associated bias voltages for performing an erase action on the memory cell of the conventional non-volatile memory cell;

    [0021] FIG. 2 is a schematic equivalent circuit diagram illustrating an array structure of a non-volatile memory according to an embodiment of the present invention;

    [0022] FIG. 3 is a schematic circuit block diagram illustrating the non-volatile memory according to the embodiment of the present invention;

    [0023] FIG. 4 is a schematic circuit diagram illustrating the auxiliary select gate line driver of the non-volatile memory according to the embodiment of the present invention;

    [0024] FIG. 5A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first program mode (PGM mode1);

    [0025] FIG. 5B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0026] FIGS. 5C and 5D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the first phase PH1 of the program cycle;

    [0027] FIGS. 5E and 5F schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the second phase PH2 of the program cycle;

    [0028] FIG. 6A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second program mode (PGM mode2);

    [0029] FIG. 6B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0030] FIGS. 6C and 6D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the first phase PH1 of the program cycle;

    [0031] FIGS. 6E and 6F schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the second phase PH2 of the program cycle;

    [0032] FIG. 7A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first program mode (READ mode1);

    [0033] FIG. 7B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0034] FIGS. 7C and 7D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the read action is performed;

    [0035] FIG. 8A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second program mode (READ mode2);

    [0036] FIG. 8B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0037] FIGS. 8C and 8D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the read action is performed;

    [0038] FIG. 9A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first erase mode (ERS mode1);

    [0039] FIG. 9B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0040] FIGS. 9C and 9D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed;

    [0041] FIG. 10A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second erase mode (ERS mode2);

    [0042] FIG. 10B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver;

    [0043] FIGS. 10C and 10D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed;

    [0044] FIG. 11A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a third erase mode (ERS mode3);

    [0045] FIG. 11B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver; and

    [0046] FIGS. 11C and 11D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed.

    DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

    [0047] The present invention provides a 2T2C memory cell and an array structure of a non-volatile memory. The array structure comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The non-volatile memory of the present invention further comprises an auxiliary select gate line driver. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of the non-volatile memory are enhanced.

    [0048] FIG. 2 is a schematic equivalent circuit diagram illustrating an array structure of a non-volatile memory according to an embodiment of the present invention. As shown in FIG. 2, the array structure 100 of the non-volatile memory 200 comprises MN memory cells c.sub.11c.sub.MN, wherein M and N are positive integers. The structures of the memory cells c.sub.11c.sub.MN are identical. In addition, the memory cells are MTP memory cells.

    [0049] Firstly, the memory cell c.sub.11 of the array structure 100 will be described as follows. As shown in FIG. 2, the memory cell c.sub.11 comprises a select transistor M.sub.S, a floating gate transistor M.sub.F, a first capacitor C.sub.1 and a second capacitor C.sub.2. Since this memory cell comprises two transistors and two capacitors, this memory cell is also referred as a 2T2C memory cell.

    [0050] The select transistor M.sub.S and the floating gate transistor M.sub.F are p-type transistors and formed in an N-well region NW. The source terminal of the select transistor M.sub.S is connected with a source line SL. The gate terminal of the select transistor M.sub.S is connected with a word line WL.sub.1. The source terminal of the floating gate transistor M.sub.F is connected with the drain terminal of the select transistor M.sub.S. The drain terminal of the floating gate transistor M.sub.F is connected with a bit line BL.sub.1. The first capacitor C.sub.1 is composed of an n-type transistor and formed in a P-well region PW. The gate terminal of the n-type transistor is formed as a first terminal of the first capacitor C.sub.1. The drain and source terminals of the n-type transistor are connected with each other and formed a second terminal of the first capacitor C.sub.1. The first terminal of the first capacitor C.sub.1 is connected with a floating gate 36 of the floating gate transistor M.sub.F. The second terminal of the first capacitor C.sub.1 is connected with an erase line EL. The second capacitor C.sub.2 is a plate capacitor. The first terminal of the second capacitor C.sub.2 is connected with the floating gate 36 of the floating gate transistor M.sub.F. The second terminal of the second capacitor C.sub.2 is connected with an auxiliary select gate line ASG.sub.1. It is noted that the example of the second capacitor C.sub.2 is not restricted to the plate capacitor. In a variant example, the second capacitor C.sub.2 is similar to the first capacitor C.sub.1, i.e., a transistor. Alternatively, the second capacitor C.sub.2 comprises plural parallel-connected capacitors of various types.

    [0051] When the program actions are performed on the memory cells c.sub.11c.sub.MN in the array structure 100, the electrons injecting paths are similar to those shown in FIGS. 1A and 1B. When the erase actions are performed on the memory cells c.sub.11c.sub.MN in the array structure 100, the electrons ejecting paths are similar to those shown in FIG. 1E. When the read actions are performed on the memory cells c.sub.11c.sub.MN in the array structure 100, the judging methods are similar to those shown in FIGS. 1C and 1D.

    [0052] In accordance with a technical feature of the present invention, the memory cells c.sub.11c.sub.MN in the array structure 100 are also connected with the corresponding auxiliary select gate lines ASG.sub.1ASG.sub.M. When the program action, the erase action or the read operation is performed, specified driving voltages are provided to the corresponding auxiliary select gate lines ASG.sub.1ASG.sub.M. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of the non-volatile memory are enhanced.

    [0053] Please refer to FIG. 2. The N memory cells c.sub.11c.sub.1N in the first row of the array structure 100 are connected with the same word line WL.sub.1 and the same auxiliary select gate line ASG.sub.1. The N memory cells c.sub.11c.sub.1N in the first row of the array structure 100 are respectively connected with N bit lines BL.sub.1BL.sub.N. The N memory cells c.sub.21c.sub.2N in the second row of the array structure 100 are connected with the same word line WL.sub.2 and the same auxiliary select gate line ASG.sub.2. The N memory cells c.sub.21c.sub.2N in the second row of the array structure 100 are respectively connected with the N bit lines BL.sub.1BL.sub.N. The rest may be deduced by analogy. The N memory cells c.sub.M1c.sub.MN in the M-th row of the array structure 100 are connected with the same word line WL.sub.M and the same auxiliary select gate line ASG.sub.M. The N memory cells c.sub.M1c.sub.MN in the M-th row of the array structure 100 are respectively connected with the N bit lines BL.sub.1BL.sub.N. In addition, all memory cells c.sub.11c.sub.MN are connected with the same source line SL, and all memory cells c.sub.11c.sub.MN are connected with the same erase line EL.

    [0054] FIG. 3 is a schematic circuit block diagram illustrating the non-volatile memory according to the embodiment of the present invention. As shown in FIG. 3, the non-volatile memory 200 comprises a word line decoder 210, a word line driver 220, an auxiliary select gate line driver 230, the array structure 100, a bit line selector 250 and a sensing circuit 260. The array structure 100 is identical to the array structure 100 shown in FIG. 2, and not redundantly described herein.

    [0055] The word line decoder 210 is connected with the word line driver 220 and the auxiliary select gate line driver 230. The word line driver 220 is connected with the word lines WL.sub.1WL.sub.M. The auxiliary select gate line driver 230 is connected with the auxiliary select gate lines ASG.sub.1ASG.sub.M. The bit line selector 250 is connected with the bit lines BL.sub.1BL.sub.N. The sensing circuit 260 is connected with the bit line selector 250. The sensing circuit 260 generates an output data D.sub.OUT.

    [0056] In the array structure 100, the memory cells c.sub.11c.sub.MN are MTP memory cells. Consequently, the program action, the erase action or the read action can be performed on the memory cells c.sub.11c.sub.MN of the non-volatile memory 200.

    [0057] The word line decoder 210 issues a decoded signal So to the word line driver 220. According to the decoded signal SD, the word line driver 220 activates one of the M word lines WL.sub.1WL.sub.M. Consequently, one of the M rows in the array structure 100 is the selected row. In addition, the bit line selector 250 activates one of the bit lines. Consequently, a selected memory cell in the selected row is determined.

    [0058] For example, the word line driver 220 activates the word line WL.sub.1. In other words, the first row in the array structure 100 is the selected row. When only the bit line BL.sub.1 is activated by the bit line selector 250, only the memory cell c.sub.11 is the selected memory cell. When the bit lines BL.sub.1BL.sub.8 are activated by the bit line selector 250, the memory cells c.sub.11c.sub.18 are the selected memory cells.

    [0059] When the program action is performed, the word line driver 220 provides an on voltage Von to one of the M word lines WL.sub.1WL.sub.M. Consequently, one of the M word lines WL.sub.1WL.sub.M is activated. In addition, the auxiliary select gate line driver 230 provides various driving voltages to the M auxiliary select gate lines ASG.sub.1ASG.sub.M. According to the activated word line, one row in the array structure 100 is determined as the selected row. In addition, at least one bit line is activated by the bit line selector 250. According to the activated word line and the activated bit line, at least one selected memory cell in the selected row is determined. After the program action is performed on the at least one selected memory cell, the at least one selected memory cell is programmed to the program state.

    [0060] When the read action is performed, one of the M word lines WL.sub.1WL.sub.M is activated. According to the activated word line, one row in the array structure 100 is determined as the selected row. In addition, the auxiliary select gate line driver 230 provides various driving voltages to the M auxiliary select gate lines ASG.sub.1ASG.sub.M. In addition, at least one bit line is activated by the bit line selector 250. According to the activated word line and the activated bit line, at least one selected memory cell in the selected row is determined. The selected memory cell generates a cell current. The cell current is transmitted to the sensing circuit 260 through the bit line selector 250. Consequently, the sensing circuit 260 performs the read action to judge the storage state of the selected memory cell and generate the output data D.sub.OUT.

    [0061] As mentioned above, the memory cells c.sub.M1c.sub.MN in the array structure 100 are connected with the erase line EL. When the erase action is performed, the auxiliary select gate line driver 230 provides the same driving voltage to the M auxiliary select gate lines ASG.sub.1ASG.sub.M. Consequently, all memory cells c.sub.M1c.sub.MN in the array structure 100 are erased simultaneously, and all memory cells c.sub.M1c.sub.MN are changed to the erase state.

    [0062] In an embodiment, the driving voltages provided from the auxiliary select gate line driver 230 to the M auxiliary select gate lines ASG.sub.1ASG.sub.M are different. Consequently, a portion of the memory cells determined by the auxiliary select gate line driver 230 are erased, and another portion of the memory cells in the array structure 100 are not erased.

    [0063] As mentioned above, the memory cells c.sub.M1c.sub.MN in the array structure 100 are MTP memory cells. That is, each of the memory cells c.sub.M1c.sub.MN can be subjected to the program action and the erase action many times. After the non-volatile memory 200 is just manufactured, the memory cells c.sub.11c.sub.MN have better characteristics and are less prone to program fail or ease fail. On the contrary, after the memory cells c.sub.11c.sub.MN has been subjected the program action and the erasing action many times, the characteristics of the memory cells c.sub.11c.sub.MN deteriorate, and the program failure or erase failure may occur. For example, if the erase count of the memory cells c.sub.11c.sub.MN does not exceed a specified count (e.g., 1000), it is considered that the memory cells have better characteristics. Whereas, if the erase count of the memory cells c.sub.11c.sub.MN exceeds the specified count, it is considered that the memory cells have inferior characteristics. In the above embodiment, the characteristics of the memory cells are determined according to the erase count. Of course, in the variant examples, the characteristics of the memory cells may be determined according to the program failure count or the erase failure count.

    [0064] For example, if a memory cell has better characteristics and is in the erase state, the threshold voltage Vt of the floating gate transistor is 1V. However, if the characteristics of the memory cell become inferior, the memory cell may be over-erased after the erase action is performed. If the memory cell has inferior characteristics and is over-erased, the threshold voltage Vt of the floating gate transistor is possibly shifted to 1.2V. After the over-erased memory cell is subjected to the program action again, it is difficult to turn on the floating gate transistor M.sub.F. Since the program current is too low, the program fail problem occurs. Under this circumstance, it is necessary to perform the program action many times to eliminate the program fail problem.

    [0065] In order to cope with the memory cells with different characteristics, the auxiliary select gate line driver 230 can be operated in different modes when the program action, the erase action or the read action is performed. Furthermore, when the program action is performed, the auxiliary select gate line driver 230 provides different driving voltages in different phases of the program cycle. Consequently, the program efficiency is enhanced. Similarly, when the erase action is performed, the auxiliary select gate line driver 230 provides different driving voltages in different mode. Consequently, the erase efficiency is enhanced. Similarly, when the read action is performed, the auxiliary select gate line driver 230 provides different driving voltages in different mode. Consequently, the read efficiency is enhanced.

    [0066] FIG. 4 is a schematic circuit diagram illustrating the auxiliary select gate line driver of the non-volatile memory according to the embodiment of the present invention. As shown in FIG. 4, the auxiliary select gate line driver 230 comprises a pull-up controller 412, a pull-down controller 414 and M driving elements 42142M. The circuitry structures of these driving elements 42142M are identical. For example, the driving element 421 comprises a P-type transistor P.sub.1 and an N-type transistor N.sub.1. The source terminal of the P-type transistor P.sub.1 receives a first supply voltage V.sub.ASGP. The gate terminal of the P-type transistor P.sub.1 receives a control signal GP.sub.1. The drain terminal of the P-type transistor P.sub.1 is connected with the drain terminal of N-type transistor N.sub.1. The gate terminal of the N-type transistor N.sub.1 receive a control signal GN.sub.1. The source terminal of the N-type transistor N.sub.1 receives a second supply voltage V.sub.ASGN. The drain terminal of the P-type transistor P.sub.1 is connected with the auxiliary select gate line ASG.sub.1. In addition, the driving element 421 can output a driving voltage to the auxiliary select gate line ASG.sub.1.

    [0067] As shown in FIG. 4, the pull-up controller 412 and the pull-down controller 414 are connected with the word line decoder 210 to receive the decoded signal S.sub.D. Also, the pull-up controller 412 and the pull-down controller 414 receive a mode signal S.sub.M. In addition, the pull-up controller 412 and the pull-down controller 414 are connected with the M driving elements 42142M. The M driving elements 42142M are respectively connected with the auxiliary select gate lines ASG.sub.1ASG.sub.M. According to the decoded signal S.sub.D and a mode signal S.sub.M, the pull-up controller 412 generates the control signals GP.sub.1GP.sub.M, and the pull-down controller 414 generates the control signal GN.sub.1GN.sub.M. The M driving elements 42142M receive the corresponding control signals GP.sub.1GP.sub.M and the corresponding control signal GN.sub.1GN.sub.M. Consequently, the M driving elements 42142M output various driving voltages to the auxiliary select gate lines ASG.sub.1ASG.sub.M. Each of the driving elements 42142M comprises two transistors. In a normal working state, one of the two transistors is turned on, and the other transistor is turned off.

    [0068] According to the mode signal S.sub.M, the M driving elements 42142M output various driving voltages to the auxiliary select gate lines ASG.sub.1ASG.sub.M under control of the pull-up controller 412 and the pull-down controller 414. That is, in different modes, the voltage levels of the first supply voltage V.sub.ASGP and the second supply voltage V.sub.ASGN are changed, and the voltage levels of the control signals GP.sub.1GP.sub.M and the control signal GN.sub.1GN.sub.M are changed. For example, the pull-up controller 412 can provide the first supply voltage V.sub.ASGP with different voltage levels and provide the control signals GP.sub.1GP.sub.M with different voltage levels in different modes to control the on/off states of the P-type transistors P.sub.1P.sub.M in the driving elements 42142M. Similarly, the pull-down controller 414 can provide the second supply voltage V.sub.ASGN with different voltage levels and provide the control signals GN.sub.1GN.sub.M with different voltage levels in different modes to control the on/off states of the N-type transistors N.sub.1N.sub.M in the driving elements 42142M.

    [0069] The operations of the auxiliary select gate line driver 230 in different modes will be described as follows. In the following examples, the first memory cell c.sub.11 in the first row of the array structure 100 is the selected memory cell, and the other memory cells are the unselected memory cells. That is, the first row is the selected row, and the other rows are the unselected rows. According to the decoded signal S.sub.D, the auxiliary select gate line driver 230 provides the corresponding driving voltages to the auxiliary select gate line ASG.sub.1 (i.e., the selected row) and the auxiliary select gate lines ASG.sub.2ASG.sub.M (i.e., the unselected rows). The driving voltages provided to the auxiliary select gate lines ASG.sub.2ASG.sub.M (i.e., the unselected rows) are identical. For brevity, only the driving element 42M corresponding to the unselected row will be described as follows. In the following examples, the driving voltages provided from the auxiliary select gate line driver 230 to the auxiliary select gate lines ASG.sub.1ASG.sub.M will be described. The bias voltages provided to the word lines WL.sub.1WL.sub.M, the source line SL and the erase line EL are similar to those of FIGS. 1A to 1E, and not redundantly described herein.

    [0070] According to the mode signal S.sub.M, the non-volatile memory 200 can be operated in a first program mode (PGM mode1), a second program mode (PGM mode2), a first read mode (READ mode1), a second read mode (READ mode2), a first erase mode (ERS mode1), a second erase mode (ERS mode2) or a third program mode (ERS mode3).

    [0071] FIG. 5A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first program mode (PGM mode1). FIG. 5B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 5C and 5D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the first phase PH1 of the program cycle. FIGS. 5E and 5F schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the second phase PH2 of the program cycle.

    [0072] The non-volatile memory 200 receives a first system operation voltage V.sub.DD and a second system operation voltage V.sub.SS. For example, the first system operation voltage V.sub.DD is 3.3V, and the second system operation voltage V.sub.SS is the ground voltage (0V). A first program voltage V.sub.PP1 is higher than a second program voltage V.sub.PP2. For example, the first program voltage V.sub.PP1 is 10V, and the second program voltage V.sub.PP2 is 7V. A first driving voltage V.sub.DV1 is a positive voltage, and the first driving voltage V.sub.DV1 is higher than or equal to the second program voltage V.sub.PP2. For example, the first driving voltage V.sub.DV1 is 9V.

    [0073] In addition, the program cycle of the program cycle contains a first phase PH1 and a second phase PH2. The time period of the first phase PH1 is about 5 s, and the time period of the second phase PH2 is about 45 s. As long as the time period of the second phase PH2 is larger than the time period of the first phase PH1, the time period of the first phase PH1 and the time period of the second phase PH2 are not restricted.

    [0074] In the first phase PH1, the first supply voltage V.sub.ASGP is V.sub.PP1, and the second supply voltage V.sub.ASGN is V.sub.SS. Each of the control signal GP.sub.1, the control signal GN.sub.1, the control signal GP.sub.M and the control signal GN.sub.M is the first program voltage V.sub.PP1. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.SS (0V). In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.SS (0V).

    [0075] In the second phase PH2, the first supply voltage V.sub.ASGP is V.sub.DV1, and the second supply voltage V.sub.ASGN is V.sub.SS. The control signal GP.sub.1 is V.sub.SS. The control signal GN.sub.1 is V.sub.SS. The control signal GP.sub.M is V.sub.DV1. The control signal GN.sub.M is V.sub.DV1. In the driving element 421, the P-type transistor P.sub.1 is turned on, and the N-type transistor N.sub.1 is turned off. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.DV1. In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.SS (0V).

    [0076] FIG. 6A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second program mode (PGM mode2). FIG. 6B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 6C and 6D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the first phase PH1 of the program cycle. FIGS. 6E and 6F schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver during the second phase PH2 of the program cycle. A second driving voltage V.sub.DV2 is a negative voltage. For example, the second driving voltage V.sub.DV2 is 2V.

    [0077] In the first phase PH1, the first supply voltage V.sub.ASGP is V.sub.DD/2, and the second supply voltage V.sub.ASGN is the second driving voltage V.sub.DV2. The control signal GP.sub.1 is V.sub.DD/2. The control signal GN.sub.1 is V.sub.SS. The control signal GP.sub.M is V.sub.DD/2. The control signal GN.sub.M is V.sub.SS. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.DV2 (2V). In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.DV2 (2V).

    [0078] In the second phase PH2, the first supply voltage V.sub.ASGP is the first driving voltage V.sub.DV1, and the second supply voltage V.sub.ASGN is V.sub.SS. The control signal GP.sub.1 is V.sub.SS. The control signal GN.sub.1 is V.sub.SS. The control signal GP.sub.M is V.sub.DV1. The control signal GN.sub.M is V.sub.DV1. In the driving element 421, the P-type transistor P.sub.1 is turned on, and the N-type transistor N.sub.1 is turned off. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.DV1. In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.SS (0V).

    [0079] In the first phase PH1 of the second program mode (PGM mode2), the first supply voltage V.sub.ASGP is not restricted to V.sub.DD/2. For example, the first supply voltage V.sub.ASGP is a control voltage. The control voltage is lower than V.sub.DD and higher than or equal to 0V. Alternatively, in the first phase PH1, the first supply voltage V.sub.ASGP is decreased to a negative voltage. For allowing the transistors P.sub.1, P.sub.M, N.sub.1 and N.sub.M in the driving elements 421 and 42M to be operated in a safe operating area (SOA), the first supply voltage and the second supply voltage need to be properly adjusted. For example, at the beginning of the first phase PH1, the first supply voltage V.sub.ASGP is firstly decreased to V.sub.DD/2, and then the second supply voltage V.sub.ASGN is decreased to the second driving voltage V.sub.DV2. At the end of the first phase PH1, the second supply voltage V.sub.ASGN is firstly increased to V.sub.SS, and then first supply voltage V.sub.ASGP is increased to V.sub.DV1.

    [0080] In accordance with the present invention, the first program mode (i.e., PGM mode1) can be applied to the memory cells with better characteristics, and the second program mode (i.e., PGM mode2) can be applied to the memory cells with inferior characteristics.

    [0081] When the program action of FIG. 5A and the program action of FIG. 6A are performed, the voltage levels of the corresponding auxiliary select gate lines in the first phase PH1 are distinguished. Please refer to FIG. 6A. In the first phase PH1 of the second program mode (PGM mode2), the second driving voltage V.sub.DV2 with the negative voltage is provided to the auxiliary select gate line ASG.sub.1. Therefore, the floating gate transistor in the selected memory cell can be turned on more easily, and more electrons are injected into the floating gate, which allows the selected memory cell with inferior characteristics to quickly transit from the over-erased state to the program state. In the situation of FIG. 5A, the memory cell has the better characteristics, and V.sub.SS (0V) is provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 in the first phase PH1. That is to say, in the first phase PH1, electrons can be efficiently injected into the floating gate of the floating gate transistor even if no negative voltage is applied to the auxiliary select gate line ASG.sub.1.

    [0082] When the program action of FIG. 5A and the program action of FIG. 6A are performed, the auxiliary select gate line ASG.sub.1 of the selected memory cell receives the first driving voltage V.sub.DV1 in the second phase PH2. Consequently, the program efficiency of the selected memory cell is enhanced. In addition, the auxiliary unselect gate line ASG.sub.M is not driven and the select transistor of the unselected memory cell is turned off. Consequently, electrons will not be injected into the floating gate of the unselected memory cell.

    [0083] In the two program modes of the above embodiment, the program action performed on a single selected memory cell is illustrated. It is noted that the two program modes can be applied to the process of programming plural memory cells in the array structure 100. For example, a byte program action is performed on eight memory cells.

    [0084] In an implementation example, a byte program action is performed on the memory cells in the first row of the array structure 100. When the byte program action is performed, the word line WL.sub.1 is activated, and thus the first row is the selected row. Then, the eight bit lines BL.sub.1BL.sub.8 are activated sequentially. Consequently, in the first phase PH1 of the second program mode, the eight selected memory cells c.sub.11c.sub.18 are activated sequentially. After the above procedure is completed, the eight bit lines BL.sub.1BL.sub.8 are activated simultaneously. Then, in the second phase PH2 of the second program mode, the eight selected memory cells c.sub.11c.sub.18 are activated simultaneously. Consequently, the total program time of the byte program action is 85 s (i.e., 58+45=85).

    [0085] FIG. 7A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first read mode (READ mode1). FIG. 7B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 7C and 7D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the read action is performed. For example, the read voltage V.sub.READ is 2V.

    [0086] During the read cycle, the first supply voltage V.sub.ASGP is V.sub.DD, and the second supply voltage V.sub.ASGN is V.sub.SS. Each of the control signal GP.sub.1, the control signal GN.sub.1, the control signal GP.sub.M and the control signal GN.sub.M is V.sub.DD. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.SS (0V). In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.SS (0V). That is, in the first read mode (READ mode1), all driving voltages provided to auxiliary select gate lines ASG.sub.1ASG.sub.M are V.sub.SS (0V). That means all the auxiliary select gate lines ASG.sub.1ASG.sub.M are not driven.

    [0087] FIG. 8A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second read mode (READ mode2). FIG. 8B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 8C and 8D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the read action is performed. A third driving voltage V.sub.DV3 is lower than the first system operation voltage V.sub.DD. In addition, the third driving voltage V.sub.DV3 is higher than the second system operation voltage V.sub.SS. For example, the third driving voltage V.sub.DV3 is 1V.

    [0088] During the read cycle, the first supply voltage V.sub.ASGP is V.sub.DV3, and the second supply voltage V.sub.ASGN is V.sub.SS. Each of the control signal GP.sub.1, the control signal GN.sub.1, the control signal GP.sub.M and the control signal GN.sub.M is V.sub.SS. In the driving element 421, the P-type transistor P.sub.1 is turned on, and the N-type transistor N.sub.1 is turned off. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 of the selected row is V.sub.DV3 (1V). In the driving element 42M, the P-type transistor P.sub.M is turned on, and the N-type transistor NM is turned off. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M of the unselected row is V.sub.DV3 (1V). That is, in the second read mode (READ mode2), all driving voltages provided to auxiliary select gate lines ASG.sub.1ASG.sub.M are V.sub.DV3 (1V).

    [0089] In accordance with the present invention, the first read mode (READ mode1) can be applied to the memory cells with better characteristics, and the second read mode (READ mode2) can be applied to the memory cells with inferior characteristics. When the read action of FIG. 8A is performed, the voltage level of the driving voltage provided to the auxiliary select gate line ASG.sub.1 is V.sub.DV3 (1V) because the memory cells have inferior characteristics. Consequently, the memory cell generates a larger read current, and the sensing circuit 260 is able to judge the storage state of the memory cell more easily. In the situation of FIG. 7A, the memory cell has the better characteristics. Even if the driving voltage provided to the auxiliary select gate line ASG.sub.1 is 0V (i.e., the auxiliary select gate line ASG.sub.1 is not driven), the memory cell can generate the sufficient read current for allowing the sensing circuit 260 to judge the storage state of the memory cell.

    [0090] FIG. 9A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a first erase mode (ERS mode1). FIG. 9B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 9C and 9D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed.

    [0091] During the erase cycle, the first supply voltage V.sub.ASGP is V.sub.DD, and the second supply voltage V.sub.ASGN is V.sub.SS. Each of the control signal GP.sub.1, the control signal GN.sub.1, the control signal GP.sub.M and the control signal GN.sub.M is V.sub.DD. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 is V.sub.SS (0V). In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M is V.sub.SS (0V). That is, in the first erase mode (ERS mode1), all driving voltages provided to auxiliary select gate lines ASG.sub.1ASG.sub.M are V.sub.SS (0V). That means all the auxiliary select gate lines ASG.sub.1ASG.sub.M are not driven.

    [0092] FIG. 10A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a second erase mode (ERS mode2). FIG. 10B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 10C and 10D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed. A fourth driving voltage V.sub.DV4 is a negative voltage. For example, the fourth driving voltage V.sub.DV4 is 2.5V.

    [0093] During the erase cycle, the first supply voltage V.sub.ASGP is V.sub.DD/2, and the second supply voltage V.sub.ASGN is the fourth driving voltage V.sub.DV4. The control signal GP.sub.1 is V.sub.DD/2. The control signal GN.sub.1 is V.sub.SS. The control signal GP.sub.M is V.sub.DD/2. The control signal GN.sub.M is V.sub.SS. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the auxiliary select gate line ASG.sub.1 is the fourth driving voltage V.sub.DV4 (2.5V). In the driving element 42M, the P-type transistor P.sub.M is turned off, and the N-type transistor N.sub.M is turned on. The voltage level of the driving voltage provided from the driving element 42M to the auxiliary select gate line ASG.sub.M is the fourth driving voltage V.sub.DV4 (2.5V). That is, in the second erase mode (ERS mode2), all driving voltages provided to auxiliary select gate lines ASG.sub.1ASG.sub.M are the fourth driving voltage V.sub.DV4 (2.5V).

    [0094] In the second erase mode (ERS mode2), the first supply voltage V.sub.ASGP is not restricted to V.sub.DD/2. For example, the first supply voltage V.sub.ASGP is a control voltage. The control voltage is lower than V.sub.DD and higher than or equal to 0V. Alternatively, in the erase cycle, the second supply voltage V.sub.ASGN is decreased to a negative voltage. For allowing the transistors P.sub.1, P.sub.M, N.sub.1 and N.sub.M in the driving elements 421 and 42M to be operated in a safe operating area (SOA), the first supply voltage and the second supply voltage need to be properly adjusted. For example, at the beginning of the erase cycle, the first supply voltage V.sub.ASGP is firstly decreased to V.sub.DD/2, and then the second supply voltage V.sub.ASGN is decreased to the fourth driving voltage V.sub.DV4. At the end of the erase cycle, the second supply voltage V.sub.ASGN is firstly increased to V.sub.SS, and then first supply voltage V.sub.ASGP is increased to V.sub.DD.

    [0095] In accordance with the present invention, the first erase mode (ERS mode1) can be applied to the memory cells with better characteristics, and the second erase mode (ERS mode2) can be applied to the memory cells with inferior characteristics. Please refer to FIG. 10A. In the second erase mode (ERS mode2), the fourth driving voltage V.sub.DV4 with the negative voltage is provided to the auxiliary select gate lines ASG.sub.1ASG.sub.M. Consequently, the voltage difference between the floating gate transistor in each of the memory cells c.sub.11c.sub.MN and the erase line EL (i.e., V.sub.EE-V.sub.DV4) is increased, and the electrons stored in the floating gate are more easily ejected to the erase line EL. After the erase action is completed, all of the memory cells c.sub.11c.sub.MN are in the erase state.

    [0096] In the situation of FIG. 9A, the memory cells c.sub.11c.sub.MN have the better characteristics. Even if the driving voltage provided to each of the auxiliary select gate lines ASG.sub.1ASG.sub.M is 0V (i.e., the auxiliary select gate lines ASG.sub.1ASG.sub.M are not driven), the erase action can be performed. That is, in the erase cycle of the first erase mode (ERS mode1), the voltage V.sub.SS (0V) is provided to the auxiliary select gate lines ASG.sub.1ASG.sub.M. Consequently, the electrons stored in the floating gate are ejected to the erase line EL. After the erase action is completed, all of the memory cells c.sub.11c.sub.MN are in the erase state.

    [0097] In the two erase modes of the above embodiment, all of the memory cells c.sub.11c.sub.MN in the array structure 100 are changed to the erase state after the erase action is completed. Furthermore, the non-volatile memory may be operated in a third erase mode (ERS mode3). When the erase action is performed, the auxiliary select gate line driver 230 provides various driving voltages to the M auxiliary select gate lines ASG.sub.1ASG.sub.M. Under the control of the auxiliary select gate line driver 230, a portion of the memory cells in the array structure 100 are erased, and another portion of the memory cells in the array structure 100 are not erased.

    [0098] FIG. 11A is a table about the bias voltages provided to the array structure when the non-volatile memory is in a third erase mode (ERS mode3). FIG. 11B is a schematic timing waveform diagram illustrating associated signals of the auxiliary select gate line driver. FIGS. 11C and 11D schematically illustrate bias voltages provided to the driving elements of the auxiliary select gate line driver when the erase action is performed. A fifth driving voltage V.sub.DV5 is a negative voltage, e.g., 2V. A sixth driving voltage V.sub.DV6 is a positive voltage, e.g., 5V. In addition, the pull-up controller 412 and the pull-down controller 414 can provide more supply voltages to the driving elements 42142M.

    [0099] During the erase cycle, the driving element 421 receives a first supply voltage and a second supply voltage, and the driving element 42M receives a third supply voltage and a fourth supply voltage. The first supply voltage V.sub.ASGP is V.sub.DD/2. The second supply voltage V.sub.ASGN is the fifth driving voltage V.sub.DV5. The third supply voltage V.sub.ASGP is the sixth driving voltage V.sub.DV6. The fourth supply voltage V.sub.ASGN is V.sub.SS. The control signal GP.sub.1 is V.sub.DD/2. The control signal GN.sub.1 is V.sub.SS. The control signal GP.sub.M is V.sub.SS. The control signal GN.sub.M is V.sub.SS. In the driving element 421, the P-type transistor P.sub.1 is turned off, and the N-type transistor N.sub.1 is turned on. The voltage level of the driving voltage provided from the driving element 421 to the selected auxiliary select gate line ASG.sub.1 is the fifth driving voltage V.sub.DV5 (2V). In the driving element 42M, the P-type transistor P.sub.M is turned on, and the N-type transistor N.sub.M is turned off. The voltage level of the driving voltage provided from the driving element 42M to the unselected auxiliary select gate line ASG.sub.M is the sixth driving voltage V.sub.DV6 (5V). That is, in the third erase mode (ERS mode3), the driving voltages provided to auxiliary select gate lines ASG.sub.1ASG.sub.M are different.

    [0100] For example, in the third erase mode (ERS mode3), the fifth driving voltage V.sub.DV5 (2V) is provided to the auxiliary select gate line ASG.sub.1, and the sixth driving voltage V.sub.DV6 (5V) is provided to the other the auxiliary select gate lines ASG.sub.2ASG.sub.M. Consequently, the voltage difference between the floating gate transistor in each of the memory cells c.sub.11c.sub.1N (i.e., in the first row of the array structure 100) and the erase line EL (i.e., V.sub.EE-V.sub.DV5) is larger. Consequently, the electrons stored in the floating gate are ejected to the erase line EL. After the erase action is completed, the memory cells c.sub.11c.sub.1N in the first row of the array structure 100 are in the erase state.

    [0101] In addition, the voltage difference between the floating gate transistor in each of the memory cells c.sub.21c.sub.MN (i.e., in the other rows of the array structure 100) and the erase line EL (i.e., V.sub.EE-V.sub.DV6) is smaller. Consequently, the electrons stored in the floating gate cannot be ejected to the erase line EL. After the erase action is completed, the storage states of the memory cells c.sub.21c.sub.MN in the other rows of the array structure 100 are kept unchanged (i.e., not changed to the erase state).

    [0102] From the above descriptions, the present invention provides a non-volatile memory with an auxiliary select gate line driver. The array structure of the non-volatile memory comprises plural 2T2C memory cells in an array arrangement. The memory cells in the array structure are connected with the corresponding auxiliary select gate lines. The auxiliary select gate line driver can output specified driving voltages to the auxiliary select gate lines. Consequently, the programming efficiency, the erasing efficiency and the reading efficiency of non-volatile memory are enhanced.

    [0103] In the above embodiments, the auxiliary select gate line driver of the non-volatile memory is selectively operated in one of seven modes according to the mode signal SM. The seven modes include the first program mode (PGM mode1), the second program mode (PGM mode2), the first read mode (READ mode1), the second read mode (READ mode2), the first erase mode (ERS mode1), the second erase mode (ERS mode2) and the third erase mode (ERS mode3). In some other embodiments, the auxiliary select gate line driver can be operated in one of less modes. For example, when the program action is performed, the auxiliary select gate line driver is selectively operated in the first program mode (PGM mode1) or the second program mode (PGM mode2). When the read action is performed, the auxiliary select gate line driver is operated in the second read mode only. When the erase action is performed, the auxiliary select gate line driver is operated in the second erase mode only.

    [0104] While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.