Abstract
The present disclosure provides a high voltage device built from modular low voltage cells. Each low voltage cell includes a plurality of low voltage semiconductor devices and one or more low voltage passive components. Each cell can be a current-bidirectional two-quadrant switch or a four-quadrant switch. All the cells may be identical and controlled with a delay time in between. Therefore, the total on and off time of the high voltage device can be controlled to reduce the output equivalent dv/dt. The cell's voltage balancing can be achieved through a control algorithm disclosed herein.
Claims
1. A high voltage device, comprising: a plurality of modular cells, each comprising a first terminal, a second terminal, and a control terminal; wherein the modular cells are connected in series, such that the first terminal of one of the modular cells is connected to the second terminal of a neighboring one of the modular cells; and wherein each of the modular cells comprises a plurality of low voltage semiconductor devices and one or more low voltage passive components.
2. The high voltage device of claim 1, wherein said one or more low voltage passive components comprises a capacitor.
3. The high voltage device of claim 1, wherein said plurality of low voltage semiconductor devices comprises at least two power MOSFETs.
4. The high voltage device of claim 1, wherein each of the modular cells is a current-bidirectional two-quadrant switch.
5. The high voltage device of claim 4, wherein the current-bidirectional two-quadrant switch comprises a main active switch, an auxiliary active switch, and a capacitor connected to form a circuit loop, wherein a first point between the main active switch and the auxiliary active switch is connected to the first terminal and a second point between the main active switch and the capacitor is connected to the second terminal.
6. The high voltage device of claim 4, wherein the current-bidirectional two-quadrant switch comprises a first circuit loop connected to the first terminal and a second circuit loop connected to the second terminal, wherein the first circuit loop includes a first main active switch, a first auxiliary switch, and a first capacitor connected in series, and the second circuit loop includes a second main active switch, a second auxiliary switch, and a second capacitor connected in series, and wherein a first point of the first circuit loop between the first main active switch and the first capacitor is connected to a second point of the second circuit loop between the second auxiliary switch and the second capacitor.
7. The high voltage device of claim 1, wherein each of the modular cells is a four-quadrant switch.
8. The high voltage device of claim 7, wherein the four-quadrant switch comprises first, second, and third circuit legs connected in parallel between the first and second terminals, the first circuit leg comprising a first auxiliary switch and a first capacitor connected in series, the second circuit leg comprising a first main switch and a second main switch connected in series, and the third circuit leg comprising a second auxiliary switch and a second capacitor connected in series.
9. The high voltage device of claim 8, wherein sources of the first and second main switches are connected with each other.
10. The high voltage device of claim 9, wherein the four-quadrant switch comprises a first circuit loop connected to the first terminal and a second circuit loop connected to the second terminal, wherein the first circuit loop includes a first main active switch, a first auxiliary switch, and a first capacitor connected in series, and the second circuit loop includes a second main active switch, a second auxiliary switch, and a second capacitor connected in series, and wherein a first point of the first circuit loop between the first main active switch and the first capacitor is connected to a second point of the second circuit loop between the second main active switch and the second capacitor.
11. The high voltage device of claim 1, wherein the control terminal of the modular cells is configured to receive a control signal shifted by a delay time for a respective one of the modular cells.
12. A high voltage half bridge device, comprising: first, second, and third terminals; a top arm connected between the first terminal and the second terminal, the top arm comprising a first quantity of low voltage modular cells connected in a cascaded form; and a bottom arm connected between the first terminal and the third terminal, the top arm comprising a second quantity of low voltage modular cells connected in a cascaded form; wherein the second quantity is equal to the first quantity.
13. The high voltage half bridge device of claim 12, wherein each of first and second quantities of the modular cells is a current-bidirectional two-quadrant switch.
14. The high voltage half bridge device of claim 12, further comprising a control terminal configured to receive a control signal for each of the low voltage modular cells, the control signal being shifted by a delay time for a respective one of the low voltage modular cells.
15. A method for controlling the high voltage device of claim 1, the method comprising: transmitting a control signal to the control terminal of each of the modular cells, the control signal being shifted by a delay time for a respective one of the modular cells; and sensing cell voltages of the modular cells; and balancing the cell voltages.
16. The method of claim 15, wherein balancing the cell voltages comprises, for each of the modular cells: determining a voltage difference by comparing a respective one of the cell voltages with a reference voltage; determining a duty cycle difference based on the voltage difference; and modifying a duty cycle of the control signal for a respective one of the modular cells by the duty cycle difference.
17. The method of claim 16, further comprising sensing an output current polarity of the high voltage device, wherein modifying the duty cycle comprises: subtracting the duty cycle difference from the duty cycle, if said respective one of the cell voltages is greater than the reference voltage and the output current polarity is greater than zero, and if said respective one of the cell voltage is not greater than the reference voltage and the output current polarity is not greater than zero; and adding the duty cycle different to the duty cycle, if said respective one of the cell voltage is greater than the reference voltage and the output current polarity is not greater than zero, and if said respective one of the cell voltages is not greater than the reference voltage and the output current polarity is greater than zero.
18. The method of claim 15, wherein balancing the cell voltages comprises: sensing an output current polarity of the high voltage device; sorting the cell voltages of the modular cells from large to small in sequence; wherein, if the output current polarity is greater than zero, one of the modular cells having a larger cell voltage than another one of the modular cells is sequenced to a leading position; and wherein, if the output current polarity is not greater than zero, one of the modular cells having a larger cell voltage than another one of the modular cells is sequenced to a lagging position.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0046] FIG. 1 shows a conventional cascaded high voltage device structure.
[0047] FIG. 2 shows another conventional cascaded high voltage device structure.
[0048] FIG. 3 shows a conventional dynamic voltage (dv/dt) control for semiconductor devices connected in a cascaded configuration.
[0049] FIG. 4 shows another conventional dynamic voltage (dv/dt) control for semiconductor devices connected in a cascaded configuration.
[0050] FIG. 5 shows a conventional high voltage phase leg configuration using a flying capacitor converter as a basic structure.
[0051] FIG. 6 shows a conventional circuit including two integrated capacitor blocked transistor (ICBT) cells, each having two active semiconductor devices (e.g., MOSFETs) and one capacitor.
[0052] FIG. 7 shows a typical modular multi-level converter (MMC) structure in high voltage DC (HVDC) applications.
[0053] FIG. 8 illustrates a high voltage device having a super switch configuration with a plurality of cells connected in series, in accordance with an embodiment of the present disclosure.
[0054] FIG. 9 illustrates an example cell of FIG. 8, having a half bridge two level two quadrant cell structure.
[0055] FIG. 10 illustrates another example cell of FIG. 8, having a cascaded half bridge three level two quadrant cell structure.
[0056] FIG. 11 illustrates still another example cell of FIG. 8, having a T-type four quadrant cell structure.
[0057] FIG. 12 illustrates yet another example cell of FIG. 8, having a four quadrant cell structure.
[0058] FIG. 13 illustrates an application of the T-type four quadrant cell structure of FIG. 11 in a Vienna rectifier.
[0059] FIG. 14 illustrates an application of using cells of FIG. 9 having a half bridge two quadrant cell structure in a typical phase leg configuration
[0060] FIGS. 15A and 15B illustrate an exemplary modulation strategy for the phase leg configuration as shown in FIG. 14.
[0061] FIG. 16 illustrates exemplary waveforms and gate signals for phase leg configuration as shown in FIG. 14.
[0062] FIG. 17 illustrates a control algorithm in accordance with an embodiment of the present disclosure.
[0063] FIG. 18 illustrates a balancing scheme for the control algorithm shown in FIG. 17.
[0064] FIG. 19 illustrates a control algorithm in accordance with another embodiment of the present disclosure.
[0065] FIG. 20 illustrates a balancing scheme for the control algorithm shown in FIG. 19.
[0066] FIG. 21 illustrates a 3-level flying capacitor converter using two-quadrant super switches in accordance with an embodiment of the present disclosure.
[0067] FIG. 22 illustrates a 3-level diode neutral point clamp converter using two-quadrant super switches in accordance with an embodiment of the present disclosure.
[0068] FIG. 23 illustrates a 3-level active neutral point clamp converter using two-quadrant super switches in accordance with an embodiment of the present disclosure.
[0069] FIG. 24 illustrates a Taipei rectifier using two-quadrant super switches in accordance with an embodiment of the present disclosure.
DETAILED DESCRIPTION
[0070] The present disclosure provides a high voltage device that can be built from modular low voltage cells. FIG. 8 illustrates a high voltage device 800 having a super switch configuration, in accordance with an embodiment of the present disclosure. As used herein, a “super switch” is a high voltage switch made up from many low voltage switches in series configuration. As shown in FIG. 8, device 800 includes a plurality of modular cells 810_1, 810_2, . . . , 810_N connected in series. Each of modular cells 810_1, 810_2, . . . , 810_N comprises a first terminal, a second terminal, and a control terminal, such that the first terminal of one of modular cells 810_1, 810_2, . . . , 810_N is connected to the second terminal of a neighboring one of modular cells 810_1, 810_2, . . . , 810_N. Each of cells 810_1, 810_2, . . . 810_N can constitute a current-bidirectional two-quadrant switch or a four-quadrant switch. The cell structure can also have a two level output or a multilevel output. Terminal 1 and terminal 2 are considered as the two output terminals for the super switch configuration. This is a modular solution and each of cells 810_1, 810_2, . . . 810_N is identical. In one example, each of cells 810_1, 810_2, . . . 810_N comprises a plurality of low voltage semiconductor devices and one or more low voltage passive components, and controllable by sending a control signal (e.g., a PWM signal) to a control terminal of cells 810_1, 810_2, . . . 810_N (e.g., the gate of the low voltage semiconductor devices). Cells 810_1, 810_2, . . . 810_N can also have a two level or multilevel structure, as shown from FIGS. 9 through 12. In one embodiment, a low voltage semiconductor device is a power MOSFET and a low voltage passive component is a capacitor, both being operable in the range of about 50V to 600V or about 500V to 1200V.
[0071] FIG. 9 illustrates an example cell 910 of cells 810_1, 810_2, . . . 810_N in FIG. 8, having a half bridge two level two quadrant cell structure. As shown in FIG. 9, cell 910 includes a terminal p between a main active switch Sim and an auxiliary active switch S.sub.1A and a terminal n between main active switch Sim and a capacitor C.sub.1A. Main active switch Sim, auxiliary active switch S.sub.1A, and capacitor C.sub.1A of cell 910 are connected to form a circuit loop. In this embodiment, the drain of switch Sim and the source of switch S.sub.1A are connected at an upper point leading to terminal p, while the source of switch Sim and capacitor C.sub.1A are at a lower point leading to terminal n. Cell 910 can be controlled by sending control signals (e.g., PWM signals) to the gates of switch Sim and switch S.sub.1A. For MV applications, a plurality of cells 910 composed of low voltage semiconductor devices can be connected in series by connecting terminal p of one cell with terminal n of a neighboring cell.
[0072] FIG. 10 illustrates another example cell 1010 of cells 810_1, 810_2, . . . 810_N in FIG. 8, having a cascaded half bridge three level two quadrant cell structure. As shown in FIG. 10, cell 1010 includes a terminal p connected to a first circuit loop 1011 and a terminal n connected to a second circuit loop 1012. First circuit loop 1011 includes first main switch Sim, first auxiliary switch S.sub.1A, and first capacitor C.sub.1A connected in series. Second circuit loop 1012 includes second main switch S.sub.2M, second auxiliary switch S.sub.2A, and second capacitor C.sub.2A connected in series. A point of first circuit loop 1011 (between first main switch Sim and first capacitor C.sub.1A) is connected to a point of second circuit loop 1012 (between second main switch S.sub.2M and second capacitor C.sub.2A). Cell 1010 can be controlled by sending control signals (e.g., PWM signals) to the gates of switches S.sub.1M, S.sub.1A, S.sub.2M, and S.sub.1A. For MV applications, a plurality of cells 1010 composed of low voltage semiconductor switches can be connected in series by connecting terminal p of one cell with terminal n of a neighboring cell.
[0073] FIG. 11 illustrates still another example cell 1110 of cells 810_1, 810_2, . . . 810_N in FIG. 8, having a T-type four quadrant cell structure. As shown in FIG. 11, cell 1110 includes a terminal p/n and a terminal n/p. Three (top, central, and bottom) circuit legs are connected in parallel between terminals p/n and n/p. Top circuit leg includes, from terminal p/n to terminal n/p, a first auxiliary switch S.sub.1A and a first capacitor C.sub.1A connected in series. Bottom circuit leg includes, from terminal p/n to terminal n/p, a second auxiliary switch S.sub.2A and a second capacitor C.sub.2A connected in series. Central circuit leg includes, from terminal p/n to terminal n/p, a first main switch S.sub.1T and a second main switch S.sub.2T connected in series. In this embodiment, sources of switches S.sub.1T and S.sub.2T are connected with each other. Cell 1110 can be controlled by sending control signals (e.g., PWM signals) to the gates of switches S.sub.1A, S.sub.1T, S.sub.2A, and S.sub.1T. For MV applications, a plurality of cells 1110 composed of low voltage semiconductor switches can be connected in series by connecting terminal p/n of one cell with terminal n/p of a neighboring cell.
[0074] FIG. 12 illustrates yet another example cell 1210 of cells 810_1, 810_2, . . . 810_N in FIG. 8, having a four quadrant cell structure. As shown in FIG. 12, cell 1210 includes a terminal p/n connected to a first circuit loop 1211 and a terminal n/p connected to a second circuit loop 1212. Cell 1210 of FIG. 12 is substantially the same as cell 1010 of FIG. 10, except that second circuit loop 1212 in FIG. 12 is flipped or upside down as second circuit loop 1012 of FIG. 10 so as to achieve a four quadrant device. That is, a point of first circuit loop 1211 (between first main switch Sim and first capacitor C.sub.1A) is connected to a point of second circuit loop 1212 (between second main switch S.sub.2M and second capacitor C.sub.2A). Cell 1210 can be controlled by sending control signals (e.g., PWM signals) to the gates of switches S.sub.1M, S.sub.1A, S.sub.2M, and S.sub.1A. For MV applications, a plurality of cells 1210 composed of low voltage semiconductor switches can be connected in series by connecting terminal p/n of one cell with terminal n/p of a neighboring cell.
[0075] FIG. 13 illustrates an application of the T-type four quadrant cell structure of FIG. 11 in a Vienna rectifier, a unidirectional single-phase three-switch three-level Pulse-width modulation (PWM) rectifier, which can be seen as a single-phase diode bridge with an integrated boost converter. As shown in FIG. 13, a plurality of cells 1110 of FIG. 11 are connected in a cascaded configuration for use in a higher voltage application.
[0076] FIG. 14 illustrates an application of using cells 910 of FIG. 9 having a half bridge two quadrant cell structure in a typical phase leg configuration. As shown in FIG. 14, a half bridge 1400 includes a top super switch or a top arm (from a terminal SW to a terminal P) having a plurality of cascaded cells 1410_1 . . . 1410_n connected in series, and a bottom super switch or a bottom arm (from a terminal SW to a terminal N) having a plurality of cascaded cells 1420_1 . . . 1420_n connected in series. In this embodiment, each of cells 1410_1 . . . 1410_n and 1420_1 . . . 1420_n is the same as cell 900 of FIG. 9. In the present disclosure, all the cells are identical, but are controlled with a delay time in between. Therefore the total on and off time of the high voltage device can be controlled to reduce the output equivalent dv/dt. This controlled dv/dt can provide benefits of shaping the output harmonics especially in the medium frequency range which could reduce the need or the footprint for the output filter.
[0077] Half bridge 1400 can be controlled in a quasi-two level (Q2L) mode. In one embodiment, four cells are connected in the top arm from terminal SW to terminal P and four cells connected in the bottom arm from terminal SW to terminal N. Each of top and bottom arms can be controlled using complimentary signals. For example, switch S.sub.P1M in the upper arm is turned on while switch S.sub.N1M in the bottom arm is turn off. Likewise, for each cell, S.sub.PnM and S.sub.PnA are controlled using complimentary signals, namely, switch S.sub.PnM is turned on while switch S.sub.PnA is turned off.
[0078] FIGS. 15A and 15B illustrate an exemplary modulation strategy for the phase leg configuration as shown in FIG. 14. In this embodiment, a total of four cells are connected in cascaded form for the top arm and another four cells are connected in cascaded form for the bottom arm. FIG. 16 illustrates exemplary waveforms and gate signals for phase leg configuration as shown in FIG. 14. For simplicity, FIG. 16 only shows the waveforms of two cells that are connected in cascaded form for the top arm and two cells that are connected in cascaded form for the bottom arm.
[0079] In order to achieve the delay time for each cell, delay time to needs to be inserted between the gating of each cell, as shown in FIG. 15. For simplicity of illustration, only the waveforms P1M, P2M, P3M, and P4M for the top arm switches S.sub.PnM are shown. With predefined delay time, some of the cells are switched on or off in the leading position, and some of the cells are switched on or off in the lagging position. The switching node Vsw shows quasi-two level waveforms.
[0080] With a certain load current polarity, the leading or lagging position on the control results in unbalanced charging or discharging for energy storage in each cell, which may create a voltage imbalance across all of the series-connected super switch cells. To solve the imbalance with Q2L operation, a rotating sequence was implemented. As shown in FIG. 15, sequence counter is counting from 0 to 3 for every switching period and thus, the leading and lagging position of the each cell physically changes through the cascaded cells. This will ensure the symmetrical charge or discharge for each cell. Each cell voltage needs to be sensed and compared with a voltage reference, which is typically the same for all cell voltages to ensure modularity. The voltage difference is fed into a voltage compensator, which tunes the duty cycle of each cell.
[0081] FIG. 17 illustrates a control algorithm in accordance with an embodiment of the present disclosure. FIG. 18 illustrates a balancing scheme for the control algorithm shown in FIG. 17. Referring to FIGS. 17 and 18, in one embodiment, a Q2L generation module 1710 generates delay time t.sub.d1, t.sub.d2, t.sub.d3, t.sub.d4, t.sub.d5, and t.sub.d6, as shown in FIGS. 15A and 15B, based on a PWM signal for upper super switches of half bridge 1400 of FIG. 14. A rotation sequence module 1720 generates a rotating sequence of signals P1M, P2M, P3M, and P4M based on delay time t.sub.d1, t.sub.d2, t.sub.d3, t.sub.d4, t.sub.d5, and t.sub.d6. Signals P1M, P2M, P3M, and P4M are then fed into cells 1410_1 . . . 1410_4 of half bridge 1400. The voltage V.sub.C of each cell is sensed and compared with a reference voltage V.sub.C_ref. The voltage difference is sent to a controller 1730 to generate the duty cycle difference ΔD to tune the duty cycle for each cell. To achieve correct behavior, the output current polarity I.sub.O (or I.sub.out) also needs to be sensed and applied. If V.sub.C is greater than V.sub.C ref and I.sub.O is greater than zero, then the voltage difference ΔD should be negative and subtracted from main duty cycle given through the PWM control terminal. If V.sub.C is greater than V.sub.C_ref and I.sub.O is not greater than zero, then the voltage difference ΔD should positive and added to the main duty cycle given through the PWM control terminal. If V.sub.C is not greater than V.sub.C_ref and I.sub.O is not greater than zero, then the voltage difference ΔD should negative and subtracted from the main duty cycle given through the PWM control terminal. If V.sub.C is not greater than V.sub.C_ref and I.sub.O is greater than zero, then the voltage difference ΔD should positive and added to the main duty cycle given through the PWM control terminal.
[0082] FIG. 19 illustrates a control algorithm in accordance with another embodiment of the present disclosure. FIG. 20 illustrates a balancing scheme for the control algorithm shown in FIG. 19. In this embodiment, the sequence of leading and lagging is utilized to balance cell voltages. As a result, no sequence rotating is required. All the cell voltages are sensed and sorted in sequence. With the load current polarity, the cell in leading or lagging position can be determined according to the cell voltages.
[0083] Referring to FIGS. 19 and 20, a Q2L generation module 1810 generates delay time t.sub.d1, t.sub.d2, t.sub.d3, t.sub.d4, t.sub.d5, and t.sub.d6, as shown in FIGS. 15A and 15B, based on a PWM signal for super switch 1400 of FIG. 14. A sequence controller 1820 generates a sequence of leading and lagging U.sub.c1 . . . U.sub.cn utilized to balance cell voltage. Accordingly, no sequence rotating is required and no duty cycle control is required as well. All the cell voltages are sensed and then sorted from large to small in sequence. With the load current polarity I.sub.O (or I.sub.out), the cell in leading or lagging position can be determined according to the cell voltages. If I.sub.O is greater than zero, then sequence the large voltage cell to a leading position; otherwise, sequence the large voltage cell to a lagging position.
[0084] Because of the modular solution, the switching loop impedance for each cell can be well maintained and thus the switching loss of the disclosed solution can be quite small even in hard switching applications. The present disclosure provides a building block solution and can be extended to other applications, such as multilevel converter, such as those shown in FIGS. 21 through 24.
[0085] For the purposes of describing and defining the present disclosure, it is noted that terms of degree (e.g., “substantially,” “slightly,” “about,” “comparable,” etc.) may be utilized herein to represent the inherent degree of uncertainty that may be attributed to any quantitative comparison, value, measurement, or other representation. Such terms of degree may also be utilized herein to represent the degree by which a quantitative representation may vary from a stated reference (e.g., about 10% or less) without resulting in a change in the basic function of the subject matter at issue. Unless otherwise stated herein, any numerical value appearing in the present disclosure are deemed modified by a term of degree (e.g., “about”), thereby reflecting its intrinsic uncertainty.
[0086] Although various embodiments of the present disclosure have been described in detail herein, one of ordinary skill in the art would readily appreciate modifications and other embodiments without departing from the spirit and scope of the present disclosure as stated in the appended claims.
