METHOD OF MAKING METAL SUBSTRATES WITH STRUCTURES FORMED THEREIN

Abstract

A method of forming In-Substrate Structures (ISS) and isolation regions, including, but not limited to Through Metal Vias (TMV), Dielectric Isolation Vias (DIV), and Dielectric Isolation Pockets (DIP) in a metal substrate to provide enhanced operations for semiconductor packages incorporating a metal substrate.

Claims

1. A method of forming in-substrate structures in a substrate body consisting of metal, the method comprising: forming shapes partially into a front side of the metal substrate body; filling the formed shapes with a dielectric material; and removing a back side of the metal substrate body until a deepest dielectric material is exposed.

2. The method according to claim 1, wherein the forming shapes is performed by laser ablating.

3. The method according to claim 2, further comprising: electropolishing the formed shapes.

4. The method according to claim 1, wherein the forming shapes is performed by an etching process.

5. The method according to claim 1, wherein at least one through metal via (TMV) is formed.

6. The method according to claim 1, wherein the removing of the back side of the metal substrate body is performed by a laser ablating process.

7. The method according to claim 1, wherein the removing of the back side of the metal substrate body is performed by a mechanical removal process including one of planarization, grinding, lapping or polishing.

8. The method according to claim 1, wherein the in-substrate structures formed includes at least one of an in-substrate plane (ISP), an in-substrate waveguide (ISW), an in-substrate antenna (ISA), a through metal dielectric isolation via (DIV), and a substrate integrated passive (SIP).

9. The method according to claim 1, wherein the in-substrate structures formed includes at least one of a through substrate port (TSP) shape, a through substrate channel (TSC) shape, and a substrate integrated microchannel (SIM) shape.

10. The method according to claim 1, wherein the forming shapes includes shallow pocket shapes such that the filling dielectric material therein forms a dielectric isolation pocket (DIP).

11. The method according to claim 1, further comprising: forming at least one shape partially into at least one of the front side and the back side of the metal substrate body to a predetermined depth to form a cavity.

12. A method of forming in-substrate structures in a substrate body consisting of metal, the method comprising: forming at least one shape partially into a front side of the metal substrate body to a predetermined depth; filling the at least one formed shape with a dielectric material; forming at least one shape partially into a back side of the metal substrate body to a predetermined depth in alignment with the at least one shape formed in the front side of the metal substrate body to meet the at least one shape formed into the front side of the metal substrate; and filling the at least one formed shape formed partially into the back side of the metal substrate body to form at least one respective in-substrate structure through the metal substrate body.

13. The method according to claim 11, wherein the forming at least one shape is performed by laser ablating.

14. The method according to claim 11, further comprising: electropolishing the at least one formed shape.

15. The method according to claim 11, wherein the forming at least one shape is performed by an etching process.

16. The method according to claim 11, wherein at least one through metal via (TMV) is formed.

17. The method according to claim 11, further comprising: forming at least one shape partially into a back side of the metal substrate body to a predetermined depth to form a cavity.

18. The method according to claim 11, wherein the forming in-substrate structures includes forming at least one of an in-substrate plane (ISP), an in-substrate waveguide (ISW), an in-substrate antenna (ISA), a through metal dielectric isolation via (DIV), and a substrate integrated passive (SIP).

19. The method according to claim 11, wherein the forming in-substrate structures includes forming at least one of a through substrate port (TSP) shape, a through substrate channel (TSC) shape and a substrate integrated microchannel (SIM) shape.

20. The method according to claim 11, further comprising: forming at least one shallow pocket into at least one of the front side and back side of the metal substrate body such that the filling dielectric material therein forms a dielectric isolation pocket (DIP).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] These and/or other features and utilities of the present inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

[0049] FIG. 1 illustrates a conventional 2.5D packaging architecture to form an electronic package.

[0050] FIG. 2 illustrates: A) a conventional 2.5D stack-up; and B) a System-on-Foil electronic package.

[0051] FIGS. 3A through 3D illustrate cross-sectional views of in-substrate structures (ISS) formed within the metal substrate, according to example embodiments of the present inventive concept.

[0052] FIG. 4 illustrates a planar top view of a metal substrate including electrically isolated metal regions and dielectric isolation regions formed through the substrate, according to an example embodiment of the present inventive concept.

[0053] FIG. 5A illustrates a planar top view of a TMV formed in a metal substrate, according to the example embodiment of FIG. 4.

[0054] FIG. 5B illustrates a cross-sectional view of the TMV illustrated in FIG. 5A.

[0055] FIG. 6 illustrates a planar top view of diameter dimensions of the through metal via (TMV) hole and pin, according to the example embodiment of FIG. 5A.

[0056] FIG. 7 illustrates a process of laser ablating regions into a metal substrate, according to example embodiments of the present inventive concept.

[0057] FIG. 8 illustrates a cross-section of laser ablated regions in the metal substrate to form the basis of dielectric isolation regions, according to example embodiments of the present inventive concept.

[0058] FIG. 9 illustrates a cross-sectional view of the laser drilled regions in FIG. 7 filled with a dielectric material, according to an example embodiment of the present inventive concept.

[0059] FIG. 10 illustrates a cross-sectional view of the laser ablated and dielectric material filled regions in FIGS. 8 and 9 with a backside grind to remove the metal substrate material to expose the TMVs and DIVs, according to example embodiments of the present inventive concept.

[0060] FIG. 11 illustrates a cross-sectional view of the laser ablated and dielectric material filled regions in FIGS. 8 and 9 and an additional process of laser ablating a backside of the metal substrate down to the laser ablated and dielectric material filled regions, according to another example embodiment of the present inventive concept.

[0061] FIG. 12 illustrates a cross-sectional view of the laser ablated regions of the backside of the metal substrate as illustrated in FIG. 11, filled with a dielectric material to form TMVs and DIVs in the metal substrate, according to another example embodiment of the present inventive concept.

[0062] FIG. 13 illustrates a microscope image of a laser ablated circular blind via in a metal substrate, according to an example embodiment of the present inventive concept.

[0063] FIG. 14 illustrates a top view of a microscope image of a laser ablated rectangular pocket on a polymer coated metal substrate, according to an example embodiment of the present inventive concept.

[0064] FIG. 15 illustrates a top view of a laser confocal image of two TMVs connected by a DIP, according to an example embodiment of the present inventive concept.

[0065] The drawings illustrate a few example embodiments of the present inventive concept and are not to be considered limiting in its scope, as the overall inventive concept may admit to other equally effective embodiments. The elements and features shown in the drawings are to scale and attempt to clearly illustrate the principles of exemplary embodiments of the present inventive concept. In the drawings, reference numerals designate like or corresponding, but not necessarily identical, elements throughout the several views.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0066] Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures. Also, while describing the present general inventive concept, detailed descriptions about related well-known functions or configurations that may diminish the clarity of the points of the present general inventive concept are omitted.

[0067] It will be understood that although the terms first and second are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of this disclosure.

[0068] Expressions such as at least one of, when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.

[0069] All terms including descriptive or technical terms which are used herein should be construed as having meanings that are obvious to one of ordinary skill in the art. However, the terms may have different meanings according to an intention of the inventor(s), case precedents, or the appearance of new technologies. Also, some terms may be arbitrarily selected by the applicant, and in this case, the meaning of the selected terms will be described in detail in the detailed description of the invention. Thus, the terms used herein have to be defined based on the meaning of the terms together with the description throughout the specification.

[0070] Hereinafter, one or more exemplary embodiments of the present general inventive concept will be described in detail with reference to accompanying drawings.

[0071] Example embodiments of the present general inventive concept are directed to semiconductor substrates and interposer packaging having ISSs, and methods of making the same.

[0072] FIGS. 3A through 3D illustrate a few different in-substrate structures that can be formed in the metal substrate 300, according to example embodiments of the present inventive concept. The different ISSs illustrated in FIGS. 3A through 3D can be formed by effectively removing sections of the metal substrate 300 and filling these sections with dielectric material 300i or leaving these sections open 300v. One of the most important ISS structures is a through metal via (TMV). Semiconductor packaging substrates with interposer, TMV, is formed of a metal through pin material 300m surrounded by a dielectric material 300i. These TMVs transport signals from one side of the metal substrate to the other side of the substrate. High frequency 50 ohm TMV ports can be formed by controlling the size and properties of the metal pin 300m and the dielectric material 300i. In-substrate planes (ISP) can be formed through the substrates 300 by creating large complex-shaped dielectrically isolated regions within the substrate to transport power, ground or electronic signals. These ISPs can take on any shape or size and can have large sections to transport high currents through the substrate 300. Another important ISS feature is a dielectric isolation via (DIV), which is essentially a hole in the metal substrate 300 filled with the dielectric material 300i. The DIVs can serve many different functions, such as, for example electrically or thermally isolate two sections of the metal substrate 300. The DIVs can also serve to electrically separate the substrate 300 from an electronic chip that is subsequently attached to the substrate 300. Electrical isolation to a subsequent component or metal trace on the substrate 300 can also be accomplished using a dielectric isolation pocket (DIP). A DIP is similar to a DIV except it does not extend through the substrate 300 and is only a dielectric 300i filled pocket in the surface of the metal substrate 300. The term substrate can be interchangeable with the term wafer throughout the detailed description, as the two terms are commonly used interchangeably in semiconductor technology. These DIPs and DIVs can also serve as substrate thermal channels (STCs), which are used to thermally isolate one section of the substrate 300 from an adjacent section so heat can be effectively spread or channeled within the substrate 300. DIVs and DIPs can also be combined to form in-substrate waveguides (ISWs). These ISWs serve as electrical traces or conduits within the substrate 300 that can start from the top or bottom surface and go through any path within the metal substrate 300 and exit at any location or locations on either side of the substrate 300. The ISWs can be used for GND, power, or signals. The size and shape of the DIVs and DIPs used to form the ISSs can be controlled to create in-substrate waveguides that are tuned to provide a 50-ohm impedance at high frequencies. Being able to remove portions of the metal substrate 300 to different depths and filling the removed portions with the dielectric material 300i can form a slanted pin 300m or steps in the ISWs through the substrate 300. The DIVs and DIPs can also be combined to form in-substrate antennas (ISAs), which can be powered from one side of the substrate 300 and radiate out the other side of the substrate 300. After etching the metal substrates 300 and filling the etched portions with dielectric 300i to form many different types of ISSs, additional ISSs can be formed by removing portions of the substrate 300 and leaving a void 300v. There are several advantages of forming a substrate integrated microchannel (SIM), or a through substrate port (TSP), or a through substrate channel (TSC). The open voids 300v can be used as a fluidic port, as an optical port, as an open area to house a chip, to fix something to the substrate 300, or for other reasons. An SIM can also be placed over a TMV or array of TMVs to recess a chip into the substrate surface and allow the chip to communicate to the other side of the substrate for power, ground or signals.

[0073] FIG. 4 illustrates a top view of a metal substrate 300, according to an example embodiment of the present inventive concept. The metal substrate 300 illustrated in FIG. 4 includes electrically isolated metal regions 302s, 302m, 302b, 304d, 304r, 306c, 306r, 308x, 308y, 308z and 309a-309b, and dielectric isolation regions 302i, 304i, 306i, 308i and 309i formed through the metal substrate 300, according to an example embodiment of the present inventive concept. Referring to FIG. 4, different shapes and size ISSs can be formed in the metal substrate 300, such as, for example, cylindrical TMVs in small 302s, medium 302m and large 302b sizes. In addition, coupled differential vias 304t, 304d and 304r can also be formed in metal substrates 300. The coupled differential vias 304t, 304d and 304r can be formed in the metal substrates 300 to reduce noise. Coupled differential vias, such as differential via 304r, can be formed to include pins 304p with a separate return ground 304gr. The coupled differential vias 304t, 304d and 304r can provide noise immunity. More specifically, differential lines/nets can subtract out common noise coupled on the two adjacent vias of the differential vias 304t, 304d and 304r.

[0074] Ports formed through the substrate 300, which are non-circular in shape, can also be formed, such as a rectangular port 306r or a more complex shaped port 306c. These ports 306r and 306c can be formed by etching rectangular or complex shaped trenches 306ri and 306ci, respectively, into the metal substrate 300 and then filling the trenches 306ri and 306ci with a dielectric material, which will be described in more detail below. These ports 306r and 306c can act as floating ground planes and are very important for high-frequency electronic devices. For example, many microwave devices use isolated ground planes, such as ground planes 306r and 306c. Further, many highspeed CPUs and FPGAs require multiple voltage sources with high current capabilities, which will benefit from using isolated metal substrate feedthroughs, such as ground planes 306r and 306c.

[0075] Still referring to FIG. 4, isolated metal regions 308x, 308y and 308z that share the same isolation regions 308i will have crosstalk between the isolated metal regions 308x, 308y and 308z. Sharing a same dielectric isolation region 309i will allow for capacitors 309 (with an anode 309a and a cathode 309b) to be formed within the metal substrate 300.

[0076] The metal substrate 300 can be made from many different metal compositions, such as, for example, Molybdenum, Iron, Titanium, Chromium, Tantalum, Tungsten, Titanium, Copper, Nickel, Vanadium, Aluminum, Cobalt, or any metal alloy. One of the most useful metal alloys in the hermetic seal industry is 52 alloy, which consists of 50.5% Ni with a balance of Fe. 52 alloy and usually has a little Chromium to help the bonding to the dielectric insulating glass. The high Nickel content in 52 alloy gives the substrate a low CTE, on the order of 5410.sup.7/ C. (5.4 ppm/ C.), which makes the substrate a good candidate for the electronic packaging industry. Molybdenum with a CTE of 4810.sup.7/ C. (4.8 ppm/ C.) at 25 C. and a high thermal conductivity (138 W/m K) makes the substrate an even better candidate for electronic packaging.

[0077] FIG. 5A illustrates a planar top view of a TMV according to the example embodiment of FIG. 4, and FIG. 5B illustrates a cross-sectional view of the TMV illustrated in FIG. 5A. Referring to FIGS. 5A and 5B, a standard TMV with a circular profile is illustrated. The metal substrate 300 and a center pin 302 are of the same substrate metal. More specifically, the center pin 302 is formed from the metal substrate 300 during the fabrication process, which is described in more detail with reference to FIGS. 7-12, below. It is to be noted that both ends of the metal pin 302, as illustrated in FIG. 5B, end in the same plane as the surfaces of the metal substrate 300. The metal substrate 300 and the conductive electrical pin 302 are electrically isolated from each other by an insulating dielectric material 302i. The dielectric material 302i can be composed of a polymer, silicone, glass, ceramic, or a combination of them, such as a glass or ceramic filled silicone or polymer, or a glass-ceramic. The word polymer as used herein is intended to include all carbon-based long chain molecules, like thermoplastics and thermosets, and where silicone includes all silicon/oxygen-based molecules. The key property of the dielectric isolation region is to not allow current to flow across the region.

[0078] There are many applications that require hermetic vias 302 or vias 302 that are sealed and do not leak gas from one side of the substrate 300 to the other side. Hermetic TMVs will require an inorganic dielectric material surrounding the vias, which is impervious to gas. Helium and other gases readily transport through polymer materials. A good bond between the metal 300 and dielectric material 302i, and between the metal 302 and dielectric material 302i, will be required. At least one continuous sealed ring around the center metal pin 302 and the dielectric material 302i and a sealed ring around the metal substrate 300 and the dielectric material 302i will be required for hermiticity. To reduce the stress at the dielectric/metal interface during thermal cycling a good thermal expansion match between the metal 300 and dielectric material 302i, and the metal 302 and dielectric material 302i, will be required. If the dielectric material 302i makes a strong bond with the metals 300, 302 and if their difference in coefficients of thermal expansion is less than 510.sup.7/ C., then there should be no loss of hermeticity during thermal cycling. Hermetically sealed vias 302 will also be important for cleanliness in subsequent processes, especially during post vacuum based processes. If the dielectric material 302i is porous or if there are cracks in the dielectric material 302i or at the interface then contamination, moisture or gas can contaminate processing steps or can cause vacuum processes to pump down very slowly due to outgassing. Therefore, for post processing it is very advantageous to have non-porous, hermetically sealed in package ports including, but not limited to TMVs, DIVs, dielectric isolation pockets (DIPs) and in-plane ports (IPP).

[0079] FIG. 6 illustrates a planar top view of diameter 302d dimensions of the TMV pin 302d and shell 302id, according to the example embodiment of FIG. 5A. An important aspect of TMVs for high frequency applications is that the size and shape of the TMVs 302 are designed to match the 50 Ohm requirements of the electronics. To achieve the optimum 50 Ohm coax capabilities, a diameter 302d of the pin 302 and a diameter 302id of a dielectric filled hole or shell must be properly chosen. The optimum diameters of the pin 302d and shell 302id in order to generate a 50 ohm coax are also dependent on the electrical conductivity of the metal pin 302 and shell 300 (substrate), and the dielectric constant of the fill material 302i. TABLE 1 below illustrates the sizes of the hole diameter or shell 302id that houses the dielectric isolation material 302i and the metal pin 302 for TMVs, Ball Grid Array (BGA) vias and C4 vias. The results assume that the substrate 300 and metal pin 302 are composed of Molybdenum and that the dielectric isolation material 302i is polyimide with a dielectric constant of 3.2.

TABLE-US-00001 TABLE 1 50 Ohm Coax TMV BGA Via C4 Via Shell Diameter 302id (m) 120 560 160 Pin diameter 302d (m) 27 125 35

[0080] The results in TABLE 2 below for the calculated diameters of the shell 302id and pin 302d assume that the dielectric isolation material 302i is changed to a glass with a dielectric constant of 5.1. Note that the shell diameters 302id are kept the same diameter and only the pin diameter 302d changes. For the BGA and C4 solder bumps not to capacitively couple to the metal substrate 300, the material under them must be an insulator 302i, therefore requiring the diameter of the dielectric isolation 302i to be 560 m for BGAs and 160 m for C4 bumps. Note that the higher dielectric constant requires a small pin diameter for a given diameter shell or a wider dielectric isolation material 302i.

TABLE-US-00002 TABLE 2 50 Ohm Coax TMV BGA Via C4 Via Shell Diameter 302id (m) 120 560 160 Pin diameter 302d (m) 18.3 85 24.3

[0081] FIG. 7 illustrates a process of laser ablating/drilling regions in a metal substrate 400, according to example embodiments of the present inventive concept, and FIG. 8 illustrates a cross-section of laser ablated/drilled regions in the metal substrate 400 to form the basis of dielectric isolation regions, according to example embodiments of the present inventive concept.

[0082] Referring to FIGS. 7 and 8, a first process step to form TMV cylindrical shaped cavities 410, pockets 412 for DIVs, pockets of varying depths 413 for DIPs, and complex shaped trenches 414 for DIVs and all other ISSs is illustrated. More specifically, a laser beam LB from a laser L can be used to cut complex shapes 410-414 into the surface of the metal substrate 400. The laser beam LB can be used to drill different depths down into the metal substrate 400 to form cylindrical cavities 410, pockets 412, DIP cavities 413, and/or complex shaped trenches 414. The patterned via cavities(s) 410, pocket(s) 412, DIP cavities 413, and complex shaped trench(es) 414 can be ablated by having a stationary laser beam LB while the substrate 400 is moved around using a motor-controlled stage, or the substrate 400 can remain stationary while a Galvo (Galvanometer) can be used to scan the laser beam LB across the substrate 400 surface. To effectively cut into the metal substrate 400, it is preferred to use a pulsed laser beam LB. If the laser pulse is less than 1 to 10 picoseconds, then the metal material of the metal substrate 400 will be ablated with minimal debris around the laser cut traces. A short pulse length laser L, such as a picosecond or femtosecond laser, traditionally ablates less than 1 m deep down into the metal substrate 400 per pulse. Therefore, the TMV holes 410 and traces 414, DIP cavities 413, and DIV pockets 412 will require many pulses to etch the required depth down into the metal substrate 400.

[0083] According to example embodiments of the present inventive concept, the cuts 410, 412, 413 and 414 are formed to extend by a predetermined depth into the metal substrate 400, as illustrated in FIG. 8. An important aspect of this example embodiment is to leave a center pin 402 in the substrate 400 which will serve as the conductive center pin 402 for the final TMV. The depth of the cut down into the metal substrate 400 can easily be controlled using a high-speed laser L, such as a picosecond laser or a femtosecond laser, by controlling the number of pulses at each cut location or passes to cut out the shape. The width of the cut or effective kerf loss can also be controlled by step scanning the laser beam LB. A TMV with a large hole diameter 402od and a small center pin diameter 402id can be accomplished by step scanning the laser and ablating concentric circles. Cutting part of the way down into the metal substrate 400 is referred to as forming a blind via.

[0084] Laser ablation is only one method of removing the material in the metal substrate 400 surface to form via cavities 410, traces 414, DIP cavities 413, and pockets 412 for subsequent dielectric material 410i, 414i, 413i, and 412i, respectively, to be filled therein. The vias 410, traces 414, DIP cavities 413, and pockets 412 can also be patterned and etched using chemicals (wet chemical etching and dry chemical etching) as well as using ions from a reactive plasma, or other methods known in the art. One problem with wet chemical etching and some reactive ion etching processes is the difficulty in creating straight high-aspect ratio channels down into the metal surface of the substrate 400. Because a reactive ion etch process etches all of the features across a large wafer at once (a parallel process), this type of process is advantageous for processing speed over a serial process such as laser ablation. However, if different depth TMVs and DIPs are required then a two layer mask process or two mask layers will be required for parallel process, such as reactive ion etching.

[0085] FIG. 9 illustrates a cross-section of the laser ablated regions in FIG. 8 being filled with a dielectric material. To provide brevity to the detailed description below, only the laser ablated regions 410, 413, and 412 will be described herein, although similar processes to form the complex shaped trenches 414 and corresponding dielectric material 414i can also be performed, without departing from the spirit and scope of the present inventive concept.

[0086] Referring to FIG. 9, once the via cavities 410, DIP cavities, and pockets 412 are formed in the metal substrate 400 a process step of filling the laser ablated cavities 410 (blind vias), DIP cavities 413, and pockets 412 (blind vias) with a dielectrically isolating material 410i, 413i, and 412i, respectively, can be performed. It is to be noted that there are many different dielectric materials 410i, 413i, and 412i that can be used to fill the laser ablated regions 410, 413, and 412. Such dielectric materials can range from polymers, silicone, glasses, ceramics, and combinations thereof. An inorganic material, such as glass, is used as the dielectric material 410i, 413i, or 412i to fabricate a hermetic via. To make the vias truly hermetic, not only will an inorganic dielectric material 410i, 413i, 412i be required, but the proper bonding between the metal substrate 400 and the dielectric material 410i, 413i, 412i will have to be achieved, as well as a reasonable CTE match between the metal substrate 400 and the dielectric material 410i, 413i, 412i.

[0087] The dielectric isolation material 410i, 413i, and 412i can be filled in the laser ablated regions 410, DIP cavities 413, and pockets 412, respectively, using many different techniques, including, but not limited to spin coating, screen printing, pressing, and particle settling with wafer shaking, or other methods known in the art. For inorganic isolation materials 410i, 413i, 412i the inorganic material is heat treated in order to burn off any binders and to sinter the glass, ceramic, or glass-ceramic. Because the laser ablated regions 410, 413, and 412 do not go all the way through the metal substrate 400, any filling process will be filling blind vias in the substrate surface. Filling non-through vias (or blind vias) is very different than most through via processes generally performed in the industry. In addition, having a center metal conductive pin 402 and only filling the ablated (or etched) region 410 with a dielectric material 410i is also different than other through via processes. Virtually all other through via processes either deposit Copper using an electrochemical process or a conductive paste using a screen-printing process to form the pin. Here an advantage of forming center metal conductive pins 402 from the same metal substrate 400 is that a more even flow (greater continuity) of electrical conductivity exists between a common ground 400 and the conductive pins 402. In contrast, filling blind vias by either depositing Copper by using an electrochemical process or a conductive paste using a screen-printing process results in less continuity of flow of electrical conductivity. Additionally, ablating only partially through the substrate to form the conductive pins 402 has a much greater chance of obtaining true vertical depth results.

[0088] A spinning process is a very simple process to fill the laser ablated regions 410 and pockets 412, 413 with any of the dielectric isolation materials as listed above. If a polymer is desired for the dielectric material 410i, 413i, or 412i then one method is to spin coat a photosensitive positive-tone dielectric based on polybenzoxazole (PBO) like HD-8820. HD-8820 is a good dielectric polymer because it has a high glass transition temperature >300 C, a low dielectric constant of 2.94, a low dissipation factor of 0.0089, good dielectric strength of 470 kV/mm, and high volume resistivity of 3.410.sup.16 U-cm. Choosing the correct spinner conditions, PBO HD-8820 can be spun on the surface of the metal wafer 400 to fill all the laser ablated regions 410 and pockets 412, 413. The HD-8820 can then be baked at the highest temperature possible in a Nitrogen atmosphere. Using a UV laser, the positive-tone photosensitive PBO can be exposed by placing the substrate 400 on a spinning chuck and scanning the laser across the surface at a very steep angle. The exposed surface can then be removed using the aqueous developer tetramethylammonium hydroxide (TMAH). The PBO polyimide can be further cured up to 350 C. to 450 C.

[0089] Glass or ceramic particles can also be filled in the laser ablated regions 410, DIP cavities 413, and pockets 412 using a wafer spinning technique. Particles loaded in a liquid binder can be spun on the surface of the substrate 400. As the liquid binder wicks down into the laser ablated regions 410, DIP cavities 413, and pockets 412 it will pull the particles with it. The glass or ceramic particles with fluid will have to be dried and potentially fired in a furnace to drive off the liquid and consolidate the glass or ceramic. Multiple spin filling and drying/sintering processes may need to be performed in order to fully fill the laser ablated channels in the surface of the substrate 400.

[0090] One popular method to fill TGVs is using conductive paste with a screen-printing process. A similar screen-printing process can be used to fill the TMVs and DIVs with a dielectric paste. The dielectric paste can be composed of glass, ceramic or a mixture of glass and ceramic particles as well as an organic vehicle and binder. A screen will have to be fabricated with openings at the locations of the laser ablated regions 410, DIP cavities 413, and pockets 412. The screen will have to be aligned to the laser ablated regions 410, DIP cavities 413, and pockets 412 and the dielectric paste can be squeegeed through the screen and into the regions 410, 413, and pockets 412 in the metal substrate 400. The metal substrate 400, with the dielectrically filled regions 410, 413 and pockets 412, can then be run through a furnace profile to burn out the organics and sinter the inorganics. Because the inorganics will shrink during burn-out and sintering a second screen-printing paste process is usually required. One issue with using a screen-printing paste process is that the ablated regions 410, DIP cavities 413, and pockets 412 that are being filled are blind, meaning they do not go all the way through the metal substrate 400. Therefore, air tends to get trapped in the ablated regions 410, 413, and pockets 412, thus creating large voids, which can have a negative effect on the electrical properties of the final TMVs. A vacuum can be used to remove the large voids in the paste filled dielectric.

[0091] Another method of filling the laser ablated regions 410, DIP cavities 413, and pockets 412 is to use a settling and vibrating process with inorganic dielectric particles, such as glass. Allowing the glass particles to settle on the metal substrate 400 and move the substrate 400 around will enable the particles to settle down into the laser ablated regions 410, 413, and pockets 412. The simplest process is to have the dielectric particles in a liquid with the laser scored metal substrate 400 in the bottom of the container. Applying ultrasonic pulses to the glass particle filled liquid will move the glass around on the metal substrate 400 surface and allow them to fall into the ablated regions 410, 413, and pockets 412. Once the ablated regions 410, 413, and pockets 412 are filled the metal substrate 400 can be carefully removed from the liquid-particle solution. Note that for settling to occur the glass dielectric particles must be denser than the liquid. The glass dielectric particles can also be mechanically moved around the surface of the metal substrate 400 to further enable them to fall into the laser ablated regions 410, 413, and pockets 412. Vibrating the metal substrate 400 will also help the glass particles fall down into the laser ablated regions 410, 413, and pockets 412 and pack tighter together, hence causing less shrinking during the sintering process.

[0092] Regardless as to which process is used to fill the laser ablated blind regions 410, DIP cavities 413, and pockets 412 with a dielectric material 410i, 413i, and 412i, respectively, the surface of the metal substrate 400 will have to be cleaned to remove any remaining dielectric contamination.

[0093] FIG. 10 illustrates a process of forming the TMVs and DIVs, according to an example embodiment of the present inventive concept. According to this example embodiment, the dielectric material 410i, 412i is exposed on the back surface of the substrate 400 by removing the metal material from the back side of the substrate 400, which will electrically isolate the center pin 402 from the metal substrate 400, thus creating an electrical port 402 through the metal substrate 400 that is electrically isolated by the dielectric isolation material 410i, thus forming a TMV. Note that the top and bottom major surfaces of the metal substrate 400 and the ends of the conductive pin 402 are along the same planar surfaces. Therefore, subsequent device interconnect metallization layers on both the top and bottom surfaces of the substrate 400 can use these conductive ports 402 to carry ground, voltage, or electronic signals from one surface of the substrate 400 to the other substrate 400 surface. These electrically isolated conductive regions 402 through the metal substrate 400 can take on any shape or size, as illustrated in FIG. 4. Removing the material from the backside of the substrate 400 up to the dielectric material 410i and 412i can also create through metal dielectric isolation regions DIV (i.e., 412i) in the substrate 400. The end result of a DIV is equivalent to cutting out a chunk of the substrate 400 and filling it with a dielectric material 412i, thus removing the coupling capacitance of any device or pad placed above the DIV. These DIV areas can take on any shape and size and are very important for high-speed devices. Arrays of these DIVs can be made to support integration of connectors, bumps for flip-chip die attach, wire bond pads, probe pads, and Surface Mount Technology (SMT) landing pads, among other components. Note that the dielectric material 413i within DIP cavities 413 is not exposed during the removal of metal material from the backside of the substrate 400, thus leaving a dielectric isolation pocket (i.e., 413i) on the topside of the surface. By adjusting the depth and area of the DIPs, the impedance of structures placed on top can be tuned for high speed signal transmission.

[0094] Still referring to FIG. 10, the material from the backside of the substrate 400 can be removed using any technique or method known in the art. Using a removal process, such as surface grinding or lapping, is the most straightforward and cost-effective process when parallel surfaces of the substrate 400 is required for subsequent post processing. These mechanical processes, including a post Chemical Mechanical Process (CMP), can produce a very low surface roughness required for most semiconductor-based processes, such as the damascene or dual-damascene process to create metal interconnects. A chemical removal process, vapor or liquid, can also be used to remove material from the backside of the substrate 400. A laser process can also be used to remove material from the backside of the substrate 400. A combination of several different processes can also be used to remove the material from the backside of the substrate 400 and expose the dielectric material 410i and 412i. For instance, a chemical wet etch process can be used to remove the bulk of the material from the backside of the substrate 400, followed by mechanical processes, such as a rough lap, fine lap and CMP, to flatten and planarize the substrate 400, exposing the dielectric material 410i and 412i and obtaining the desired surface roughness. If a double-sided lapping process is used to create a low surface roughness finish, then this process can also be used to remove any dielectric surface contamination from the dielectric filling process step. Therefore, creating two clean, high-quality smooth surfaces for subsequent RDLs with DIVs and TMVs interposers for 2.5/3D advanced packaging.

[0095] FIGS. 11 and 12 illustrate an alternative process of forming the TMVs, DIPs, and DIVs, according to another example embodiment of the present inventive concept. The process of forming the TMVs, DIPs, and DIVs according to this example embodiment includes turning over the metal substrate 400, which includes the dielectric material 410i, 413i, and 412i filled in the laser ablated regions 410, topside DIP cavities 413, and pocket(s) 412, as illustrated in FIG. 9, and then aligning the laser to ablate new regions 410 and pocket(s) 412 directly above the originally ablated regions 410 and pocket(s) 412 with the dielectric material 410i and 412i filled therein, respectively. Backside ablated regions 410, 412, can be aligned with topside filled dielectric regions 410i, 412i using through-wafer alignment marks previously ablated into the wafer during the topside ablation process. DIP cavity regions on the backside 413b of the metal substrate 400 can also be formed. Newly ablated regions 410 and pocket(s) 412 can be formed down into the metal substrate 400 to a point where the newly ablated regions 410 and pocket(s) 412 meet the dielectric material 410i and 412i previously formed through the front surface of the metal substrate 400. At this point, a continuous electrical pin 402 is formed. The backside ablated regions 410, 412, and 413b are then filled with dielectric material to form TMV dielectric 410i, DIVs 412i, and DIPs 413bi. An advantage of this process of ablating partially through the front surface of the substrate 400 to form the beginning of a metal pin 402, filling with dielectric, and then ablating partially through the back surface of the substrate 400 to complete the metal pin 402 is that in-substrate structures, such as TMVs and DIVs, can be formed in metal substrates twice as thick as would be possible using the drilling, filling, and backside grinding method. Forming the through vias using the two-side aligned etch and fill process does not require a thick backside grind to expose the dielectric filled material like in the drill, fill, and grind process. The double-sided drill and fill process also allows for DIPs on both sides of the wafer, which opens up a large amount of different ISSs that can be formed in the metal wafers.

[0096] The ISSs include, but are not limited to, TMVs, DIVs, ISPs, DIPs, STCs, ISWs, ISAs, SIMs, TSPs, TSCs, and SIPs.

[0097] TMVs facilitate power, ground, and signal to pass between electronic components inside the package and outside the package. The TMVs become coaxial if the metal substrate is grounded, which is often the case, and this provides lower crosstalk, lower loss, and a lower number of return vias relative to other through substrate vias, like TSVs and TGVs. The TMVs can also be fabricated in such a way as to form differential through metal vias. In this configuration, there are two dielectrically isolated signal pins, each surrounded by the same grounded metal substrate.

[0098] DIPs can be used to provide additional dielectric thickness to support patterned interconnects disposed above or below the dielectric. For example, as discussed in the background section, redistribution layers (RDLs) are a vital part of advanced packages and thick dielectric layers are often desired to support interconnects with high current carrying capability, controlled characteristic impedance, or low loss. However, there are technical and cost challenges associated with the deposition of thick dielectrics when employing conventional semiconductor fabrication processes. Alternatively, the DIP process produces an electrically isolated region between the metal substrate and patterned interconnect above, allowing for integration of impedance controlled, low loss RF interconnects without thick laminates or vacuum deposited oxides. Daisy chain or other connections can also be fabricated by connecting TMVs with DIPs that have a metal interconnect patterned atop them (FIG. 15).

[0099] DIVs can be used to produce a glass-like substrate in a local region of the metal substrate to eliminate capacitive and inductive coupling between the metal substrate and electrically conductive components, like die bumps and pads, disposed on either side of the metal substrate. DIVs can also be used for optical vias and waveguides to support photonic integration.

[0100] ISPs provide bulk metal for low impedance, high integrity power and ground routing to and from any point within the metal substrate. ISPs are valuable for improving the performance of the power delivery network (PDN) of an advanced package. They can also be used in combination with other ISSs, or more commonly, a patterned interconnect disposed on either side of the metal substrate, to form an SIP, like a decoupling capacitor.

[0101] ISWs can be used to route signal, power, or ground within the substrate to support, for example, high current density or impedance-controlled interconnects that would otherwise be difficult to manufacture using conventional RDL processes.

[0102] STCs can be used to provide thermal management, for example, by directing heat from a chip into a specific direction or by blocking heat from reaching a specific component.

[0103] ISAs can be used to form an antenna-in-package (AIP). For example, RF components such as transceivers, power amplifiers (PA), low-noise amplifiers (LNA), switches, filters, power management integrated circuits (PMIC), etc., can be mounted to RDLs patterned on one side of the metal substrate and cause a signal to radiate through the metal substrate using ISAs.

[0104] SIPs, by using the metal core for at least a portion of the component, can be used to as built in capacitors, resistors, inductors, or other passive components to support signal routing, power delivery, and other electrical functions.

[0105] Lastly, SIMs, TSPs, and TSCs can be used to support microfluidics and connectors.

[0106] Referring to FIGS. 11 and 12, once the newly ablated cavities 410 and pocket(s) 412 are formed into the back surface of the substrate 400 to meet the corresponding previously formed topside dielectric material 410i and 412i additional dielectric isolation material 410i, 413bi, and 412i can be filled in the laser ablated regions 410, backside DIP cavity 413b, and 412 according to any of the processes mentioned above with respect to FIG. 9. With this process as illustrated in FIGS. 11 and 12 a high degree of vertical depth of TMVs and DIVs is obtained, which leads to thicker, and thus more rigid substrates.

Example Products Of The Present Inventive Concept

[0107] FIG. 13 illustrates a microscope planar view of a laser drilled circular via 410 into a metal substrate 400. The circular blind vias 410 was drilled 175 m down into a 250 m thick Molybdenum substrate 400 by ablating 75 continuous circles. Notice that by ablating a circular profile 410 a center pillar 402 is left in the center of the via hole 410. This center pillar 402 will serve as the center pin in the final processed TMV. The outside diameter of the laser drilled via 410 is 70 m, the center metal conductive pillar 402 is 25 m, and the width of the laser drilled via 410 or kerf loss is 22.5 m. One issue with the laser used to cut the via hole 410 in the metal substrate 400 is that the pulse length is about 1.5 nanoseconds. This long pulse length does not fully evaporate the metal, therefore leaving debris 410db around the outside perimeter of the laser cut hole 410.

[0108] FIG. 14 illustrates a top microscope planar view of a laser drilled rectangular pocket 412 in a Molybdenum substrate 400. The pocket 412 was 1.0 mm0.5 mm and was drilled 125 m down into the substrate 400 surface. To reduce or eliminate debris 412db around the laser cut region 412 the metal substrate 400 surface was pre-coated with a polymer film. A ProtectoLED coating was spun on the surface of the metal substrate 400. The ProtectoLED film is a water-soluble polymer film that is the Ultimate Surface Protection Coating for Laser Processing. The clear ProtectoLED liquid was spun on the metal substrate 400 at 1,000 rpms for 30 minutes and then followed by a hot plate bake at 95 C. for 5 minutes. FIG. 14 illustrates that even before the ProtectoLED film is removed the laser debris 412db is dramatically reduce. To remove the laser debris 412db the substrate 400, with the ProtectoLED film, is placed upside down in a DI water bath and ultrasound is used to help the debris 412db float loose from the surface of the metal substrate 400.

[0109] FIG. 15 illustrates a top view of a laser confocal microscope image of two TMVs connected with a DIP laser etched into the metal wafer. The TMV pins 402 were formed by laser drilling cylindrical cavities 410 down into the metal surface 400. A laser drilled DIP cavity 413 connects the two TMVs. After these three ISSs are fully formed a metal can be deposited across the DIP to connect the two TMV pins 402 forming a delay line or a daisy chain through the metal wafer 400.

[0110] Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.