Input impedance boosting apparatus robust against parasitic components

Abstract

Disclosed is an input impedance boosting apparatus. More particularly, an input impedance boosting apparatus including an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and including a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and including a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal is provided.

Claims

1. An input impedance boosting apparatus, comprising: an analog-to-digital converter; an input capacitor connected to an input terminal of the analog-to-digital converter and a ground line and comprising a first shielding metal formed thereunder; a feedback capacitor connected onto a positive feedback loop of the analog-to-digital converter and comprising a second shielding metal formed thereunder; and an impedance booster connected to both ends of the feedback capacitor and configured to boost an input impedance based on a first parasitic component formed between the input capacitor and the first shielding metal and a second parasitic component formed between the feedback capacitor and the second shielding metal.

2. The input impedance boosting apparatus according to claim 1, wherein the impedance booster boosts the input impedance in a manner of copying the first parasitic component and the second parasitic component and adding the copied first and second parasitic components to the positive feedback loop.

3. The input impedance boosting apparatus according to claim 1, wherein the impedance booster comprises a first metal connected to a first terminal of the feedback capacitor; and a third shielding metal formed under the first metal and connected to a second terminal of the feedback capacitor.

4. The input impedance boosting apparatus according to claim 1, wherein the first shielding metal and the second shielding metal are respectively connected to a ground line.

5. The input impedance boosting apparatus according to claim 1, further comprising a chopper switch connected to an input terminal of the analog-to-digital converter.

6. The input impedance boosting apparatus according to claim 4, wherein the impedance booster further comprises a dummy switch connected to both ends of the feedback capacitor.

7. The input impedance boosting apparatus according to claim 6, wherein the impedance booster boosts the input impedance in a manner of copying a third parasitic component formed by the chopper switch through the dummy switch and of adding the copied third parasitic component to the positive feedback loop.

8. The input impedance boosting apparatus according to claim 6, wherein the dummy switch is formed to have a size equal to the chopper switch.

9. The input impedance boosting apparatus according to claim 1, wherein the feedback capacitor and the input capacitor are Metal-Oxide-Metal (MOM) capacitors.

10. The input impedance boosting apparatus according to claim 1, wherein the analog-to-digital converter is a continuous-time delta-sigma analog-to-digital converter comprising a linear integrator provided with a linear Gm cell and a quantizer provided with a body-driven VCO and a Frequency to Digital Converter (FDC).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

(2) FIG. 1 is a diagram for explaining an input impedance boosting apparatus according to an embodiment;

(3) FIGS. 2A to 2C are diagrams for more specifically explaining an input impedance boosting apparatus according to an embodiment;

(4) FIG. 3 is a diagram for more specifically explaining a linear integrator according to an embodiment;

(5) FIG. 4 is a diagram for more specifically explaining a body-driven VCO according to an embodiment; and

(6) FIGS. 5A and 5B are diagrams for explaining the performance simulation results of an input impedance boosting apparatus according to an embodiment.

DETAILED DESCRIPTION OF THE INVENTION

(7) The embodiments will be described in detail herein with reference to the drawings.

(8) However, it should be understood that the present disclosure is not limited to the embodiments according to the concept of the present disclosure, but includes changes, equivalents, or alternatives falling within the spirit and scope of the present disclosure.

(9) In the following description of the present disclosure, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present disclosure unclear.

(10) The terms used in the specification are defined in consideration of functions used in the present disclosure, and can be changed according to the intent or conventionally used methods of clients, operators, and users. Accordingly, definitions of the terms should be understood on the basis of the entire description of the present specification.

(11) In description of the drawings, like reference numerals may be used for similar elements

(12) The singular expressions in the present specification may encompass plural expressions unless clearly specified otherwise in context.

(13) In this specification, expressions such as A or B and at least one of A and/or B may include all possible combinations of the items listed together.

(14) Expressions such as first and second may be used to qualify the elements irrespective of order or importance, and are used to distinguish one element from another and do not limit the elements.

(15) It will be understood that when an element (e.g., first) is referred to as being connected to or coupled to another element (e.g., second), it may be directly connected or coupled to the other element or an intervening element (e.g., third) may be present.

(16) As used herein, configured to may be used interchangeably with, for example, suitable for, ability to, changed to, made to, capable of, or designed to in terms of hardware or software.

(17) In some situations, the expression device configured to may mean that the device may do with other devices or components.

(18) For example, in the sentence processor configured to perform A, B, and C, the processor may refer to a general-purpose processor (e.g., CPU or application processor) capable of performing corresponding operation by running a dedicated processor (e.g., embedded processor) for performing the corresponding operation, or one or more software programs stored in a memory device.

(19) In addition, the expression or means inclusive or rather than exclusive or.

(20) That is, unless otherwise mentioned or clearly inferred from context, the expression x uses a or b means any one of natural inclusive permutations.

(21) In the above-described specific embodiments, elements included in the disclosure are expressed singular or plural in accordance with the specific embodiments shown.

(22) It should be understood, however, that the singular or plural representations are to be chosen as appropriate to the situation presented for the purpose of description and that the above-described embodiments are not limited to the singular or plural constituent elements. The constituent elements expressed in plural may be composed of a single number, and constituent elements expressed in singular form may be composed of a plurality of elements.

(23) In addition, the present disclosure has been described with reference to exemplary embodiments, but it should be understood that various modifications may be made without departing from the scope of the present disclosure.

(24) Therefore, the scope of the present disclosure should not be limited by the embodiments, but should be determined by the following claims and equivalents to the following claims.

(25) FIG. 1 is a diagram for explaining an input impedance boosting apparatus according to an embodiment.

(26) Referring to FIG. 1, an input impedance boosting apparatus 100 according to an embodiment may reduce the effect of a parasitic capacitance component without additional calibration or trimming.

(27) In addition, the input impedance boosting apparatus 100 may boost an input impedance while minimizing power consumption and an increase in cost according to a circuit area.

(28) In addition, the input impedance boosting apparatus 100 may achieve an improved impedance boosting performance compared to an existing technology of using a trimming process.

(29) For this, the input impedance boosting apparatus 100 may include an Analog-to-Digital Converter (ADC), an input capacitor C.sub.IN, a feedback capacitor C.sub.IN and an impedance booster.

(30) For example, the ADC may be an analog-to-digital converter having a gain value of 2 or 2 or a Continuous-Time Delta-Sigma Modulator (CTDSM).

(31) Specifically, the input capacitor C.sub.IN according to an embodiment may be connected to an input terminal and ground line of the ADC, and a first shielding metal 110 may be formed on a lower part of the input capacitor C.sub.IN.

(32) In addition, the feedback capacitor C.sub.IN may be connected onto a positive feedback loop of a delta-sigma modulator, and a second shielding metal 120 may be formed on a lower part of the feedback capacitor C.sub.IN.

(33) For example, the first shielding metal 110 and the second shielding metal 120 may be respectively connected to a ground line and may be spaced apart from each other by a gap having a preset size under the corresponding capacitor.

(34) In addition, the input capacitor C.sub.IN and the feedback capacitor C.sub.IN may be metal-oxide-metal (MOM) capacitors.

(35) An impedance booster according to an embodiment may be connected to the feedback capacitor C.sub.IN and may boost the input impedance based on a first parasitic component 110-1 formed between the input capacitor C.sub.IN and the first shielding metal 110 and a second parasitic component 120-1 formed between the feedback capacitor C.sub.IN and the second shielding metal 120.

(36) According to an aspect, impedance boosters 130 and 140 may boost the input impedance in a manner of copying the first parasitic component 110-1 and the second parasitic component 120-1 and adding the same to the positive feedback loop.

(37) According to an aspect, the impedance boosters 130 and 140 may include a first metal 140 connected to a first terminal of the feedback capacitor C.sub.IN; and a third shielding metal 130 formed under the first metal 140 and connected to a second terminal of the feedback capacitor C.sub.IN.

(38) For example, the third shielding metal 130 may be formed under the first metal 140 to be spaced apart from the first metal 140 by a preset-sized gap.

(39) The input impedance boosting apparatus 100 may further include a chopper switch connected to the input terminal of the ADC. In other words, the chopper switch may be provided between the input terminal of the ADC and a node to which the input voltage V.sub.IN is applied.

(40) According to an aspect, the impedance booster may further include a dummy switch connected to both ends of the feedback capacitor C.sub.IN.

(41) Specifically, the impedance booster may boost the input impedance in a manner of copying a third parasitic component formed by the chopper switch through the dummy switch and adding the same to a positive feedback loop. For example, the dummy switch may be formed to have the same size as the chopper switch.

(42) Meanwhile, the ADC may be a continuous-time delta-sigma analog-to-digital converter including a linear integrator provided with a linear Gm cell and a quantizer provided with a body-driven VCO and a Frequency to Digital Converter (FDC).

(43) Specifically, the linear integrator may generate a first output signal corresponding to the input voltage V.sub.IN based on the operation of the linear Gm cell that receives the preset input voltage V.sub.IN.

(44) In addition, the quantizer may generate a second output signal corresponding to the first output signal based on the operation of the body-driven VCO that receives the first output signal and may generate a digital output code D.sub.OUT corresponding to the second output signal based on the operation of FDC that receives the second output signal.

(45) More specifically, the ADC is a 1.sup.st order CTDSM composed of the linear integrator 110 having low-noise characteristics and high linearity characteristics and a quantizer based on the body-driven VCO and may achieve low quantization noise characteristics within a signal bandwidth due to the inherent noise characteristics of the VCO-based quantizer while having high stability characteristics as characteristics of the 1st order loop.

(46) That is, the ADC may maximize the main performances, such as noise performance, linearity and a bandwidth, of the entire system by improving noise-power efficiency and linearity of the integrator and the VCO-based quantizer.

(47) According to an aspect, the ADC may further include a 4-tap FIR filter provided on a delta-sigma feedback loop that connects the input terminal of the linear integrator and the output terminal of the quantizer.

(48) For example, the delta-sigma feedback loop may be a positive feedback loop.

(49) Specifically, the input impedance of the ADC is determined by a chopping frequency f.sub.CH at an input capacitor C.sub.IN provided between the input terminal of the linear integrator 210 and a ground line and a node connected to the input terminal of the linear integrator 210 and, in the case of existing devices, a chopping frequency is equal to fs or used as fs/2, where fs is a sampling frequency, to prevent aliasing of quantization noise due to chopping.

(50) However, in this case, there is a problem of having a low input impedance of 1 M or less due to a high sampling frequency. To solve this problem, the ADC may generate notches in quantization noise by connecting a 4-tap FIR filter onto a feedback loop.

(51) More specifically, the ADC filters the quantization noise of a frequency band in which aliasing occurs through the 4-tap FIR filter to prevent the aliasing of quantization noise caused by chopping.

(52) In addition, the ADC uses a notch frequency of fs/8 generated through the 4-tap FIR filter as a chopping frequency, thereby increasing the input impedance by 4 times compared to an existing device.

(53) FIGS. 2A to 2C are diagrams for more specifically explaining an input impedance boosting apparatus according to an embodiment.

(54) Referring to FIGS. 2A to 2C, Reference numeral 210 illustrates a parasitic capacitance component to be considered in an input impedance boosting apparatus, and Reference numerals 220 and 230 more specifically illustrate the input impedance boosting apparatus according to an embodiment.

(55) According to Reference numeral 210, the input impedance boosting apparatus according to an embodiment uses a method of copying (imitating) a parasitic capacitance component without trimming and of adding the copied parasitic capacitance component to a positive feedback loop to minimize the effect of the parasitic capacitance component. For this, the input impedance boosting apparatus may consider a parasitic capacitor component C.sub.P_CH generated in the chopper switch and a parasitic capacitor component C.sub.P_M-GND generated in the input capacitor C.sub.IN and the feedback capacitor C.sub.IN, as main parasitic capacitances.

(56) Specifically, an input impedance boosting apparatus may implement infinite impedance when a system gain is 2 and the feedback capacitor C.sub.IN satisfies the condition of Equation 2 below:

(57) $\begin{array}{cc}{C}_{\mathrm{IN}}^{}=C_{\mathrm{IN}}+\underset{\mathrm{Parasiic}\mathrm{Replication}}{C_{\mathrm{P\_CH}}+C_{\mathrm{P\_M}-\mathrm{GND}}}& \left[\mathrm{Equation}2\right]\end{array}$

(58) According to Reference numerals 220 and 230, the input impedance boosting apparatus according to an embodiment may use a parasitic replication technique to copy the above-described parasitic capacitance component through Reference numeral 210.

(59) To copy a parasitic capacitance by a Metal-Oxide-Metal (MOM)-type capacitor (C.sub.IN/C.sub.IN), the input impedance boosting apparatus may include a shielding metal formed under the MOM capacitor. In this case, the parasitic capacitance component C.sub.P_M-GND is defined by an overlap area between the shielding metal and a metal layer of the MOM capacitor and may be easily copied.

(60) In addition, the input impedance boosting apparatus may copy the parasitic capacitance component C.sub.P_CH by using a dummy switch having the same size as the chopper switch and may minimize the effect of the parasitic capacitor and achieve 70 times higher impedance compared to the conventional cases by using the above-described manner.

(61) Specifically, the input impedance boosting apparatus may include a chopper switch, an ADC connected to the chopper switch, an input capacitor C.sub.IN on which a first shielding metal 221 is formed, and a feedback capacitor positioned on C.sub.IN a positive feedback loop and including a second shielding metal 222 formed thereunder.

(62) In addition, the input impedance boosting apparatus may further include an impedance booster for boosting input impedance based on a first parasitic component 221-1 connected to both ends of the feedback capacitor C.sub.IN and formed between the input capacitor C.sub.IN and the first shielding metal 221 and a second parasitic component 222-1 formed between the feedback capacitor C.sub.IN and the second shielding metal 222. For this, the impedance booster may include a first metal connected to the first terminal of the feedback capacitor C.sub.IN and a third shielding metal 223 formed under the first metal and connected to the second terminal of the feedback capacitor C.sub.IN.

(63) According to an aspect, the impedance booster may boost the input impedance in a manner of copying the first parasitic component 221-1 and the second parasitic component 222-1 and adding the same to the positive feedback loop.

(64) More specifically, in the input impedance boosting apparatus, the parasitic capacitance components 221-1 and 222-1 may be controlled by respectively disposing the first shielding metal 221 and second shielding metal 222, connected to a ground line, under the input capacitor C.sub.IN and the feedback capacitor C.sub.IN as MOM capacitors.

(65) Here, each of the parasitic capacitance components 221-1 and 222-1, i.e., the parasitic capacitance components C.sub.P_GND1 and C.sub.P_M-GND2, may be an overlap capacitance generated by a metal layer of each of the MOM capacitors and a shielding metal of each thereof.

(66) That is, in the input impedance boosting apparatus, a metal ground parasitic capacitance component may be added around the feedback capacitor C.sub.IN to remove (offset) the parasitic effect caused by the parasitic capacitance components C.sub.P_GND1 and C.sub.P_M-GND2.

(67) In other words, the input impedance boosting apparatus may minimize influence of the parasitic capacitance components C.sub.P_GND1 and C.sub.P_M-GND2 by copying the parasitic capacitance components C.sub.P_GND1 and C.sub.P_M-GND2 (i.e., C.sub.P_GND=C.sub.P_GND1+C.sub.P_GND2) using an impedance booster including the first metal connected to the first terminal of the feedback capacitor C.sub.IN and the third shielding metal 223 formed under the first metal and connected to the second terminal of the feedback capacitor C.sub.IN and by reflecting the copied parasitic capacitance components to the positive feedback loop.

(68) Meanwhile, the impedance booster may further include a dummy switch connected to both ends of the feedback capacitor C.sub.IN and formed to have the same size as the chopper switch and may minimize the influence of the parasitic capacitance component (C.sub.P_CH) by copying (i.e., C.sub.P_CH) the third parasitic component (i.e., C.sub.P_CH=C.sub.GS+C.sub.J+C.sub.GD+C.sub.J) formed by the chopper switch through the dummy switch and by reflecting the copied third parasitic component to the positive feedback loop.

(69) FIG. 3 is a diagram for more specifically explaining a linear integrator according to an embodiment.

(70) Referring to FIG. 3, a linear integrator 300 according to an embodiment is a first entity to which the input of an analog-to-digital converter (ADC) according to an embodiment is applied and plays a major role in determining system noise and linearity, so it may be designed to have low noise and high linearity.

(71) The linear integrator 300 according to an embodiment may generate first output signals I.sub.OUTN, I.sub.OUTP corresponding to input voltages V.sub.INN, V.sub.INP based on the operation of a linear Gm cell 310 receiving preset input voltages V.sub.INN, V.sub.INP.

(72) The linear Gm cell 310 may include a plurality of operational amplifiers 311 and a plurality of resistors RD connected to an input terminal of each of the OPAMPs 311, and the plural resistors RD may be respectively connected to the OPAMPs 311 through one side end of each of the plural resistors RD and may be respectively connected to a power supply voltage VDD line through another side end of each of the plural resistors RD.

(73) In addition, the linear integrator 300 may further include a DC-current source 320 connected to an output terminal of the linear Gm cell 310.

(74) Meanwhile, in the linear integrator 300, each of the OPAMPs 311 may be designed as current-recycling OPAMP to improve noise power efficiency.

(75) The input voltage V.sub.INP may be received through gate terminals of transistors M2 and M4 among a plurality of transistors constituting the OPAMPs 311, and the input voltage V.sub.INN may be received through gate terminals of transistors M1 and M3 among the transistors. Here, the transistors M1 to M4 may operate as a transconductance amplifier based on the input voltages V.sub.INN and V.sub.INP.

(76) According to an aspect, the linear integrator 300 may generate a linearly changing current by copying the input voltages V.sub.INN, V.sub.INP to both ends of the plural resistors RD by a unit gain feedback in the linear Gm cell 310 and may generate a first output signal corresponding to a change in the generated current.

(77) Specifically, the linear integrator 300 may generate output currents I.sub.OUTN, I.sub.OUTP by copying the linear current change generated by the linear Gm cell 310 to an output terminal by the NMOS transistor, and, since the generated output currents I.sub.OUTN, I.sub.OUTP flow into a load capacitor of the linear integrator 300, linearity may be maintained. Here, the output currents I.sub.OUTN, I.sub.OUTP may be converted to a corresponding voltage (i.e., first output signal) by the load capacitor.

(78) FIG. 4 is a diagram for more specifically explaining a body-driven VCO according to an embodiment.

(79) Referring to FIG. 4, the quantizer included in the ADC may generate a second output signal corresponding to the first output signal based on the operation of the body-driven VCO 400 that receives the first output signal output from the linear integrator and may generate a digital output code D.sub.OUT corresponding to the second output signal based on the operation of FDC that receives the second output signal.

(80) Specifically, in the case of the conventional gate-driven VCO, a change in output frequency is caused by a change in delay of each inverter delay-cell, and this delay change is generated by a change in the current of the PMOS transistor.

(81) Here, the input voltage V.sub.C of the gate-driven VCO is applied to a gate terminal of the PMOS transistor, and the G.sub.m characteristic of the PMOS transistor greatly affects the linearity. That is, since the G.sub.m of a PMOS transistor has a nonlinear characteristic, a change in output frequency with respect to the input voltage of the gate-driven VCO has a nonlinear characteristic.

(82) On the other hand, in the case of the body-driven VCO 400, input voltages V.sub.C+, V.sub.C are applied to a body terminal of the inverter delay-cell, unlike the existing gate-driven VCO, whereby the change in the delay of the inverter delay-cell is caused by a change in a threshold voltage of each of the PMOS transistor and NMOS transistor constituting the inverter delay-cell due to a change in the body voltage.

(83) That is, a change in output frequency versus input voltage of the body-driven VCO 400 according to an embodiment is caused by the G.sub.mb characteristic of each transistor, and since G.sub.mb has linear characteristics compared to G.sub.m, the body-driven VCO according to an embodiment may secure linear characteristics than the existing gate-driven VCO.

(84) FIGS. 5A and 5B are diagrams for explaining the performance simulation results of an input impedance boosting apparatus according to an embodiment.

(85) Referring to FIGS. 5A and 5B, Reference numerals 510 and 520 illustrate input impedance (Z.sub.IN) measurement results of the input impedance boosting apparatus according to an embodiment.

(86) Specifically, in the input impedance boosting apparatus according to an embodiment, a first shielding metal and second shielding metal connected to a ground line are respectively disposed under an input capacitor and a feedback capacitor as MOM capacitors, a first metal is disposed to be connected to the first terminal of the feedback capacitor, and a third shielding metal is formed under the first metal and connected to the second terminal of the feedback capacitor C.sub.IN, so that a parasitic capacitance component due to the input capacitor and the feedback capacitor may be controlled.

(87) In addition, in the input impedance boosting apparatus according to an embodiment, a dummy switch is connected to the feedback capacitor and is formed to have the same size as the chopper switch, so that a parasitic capacitance component caused by the chopper switch may be controlled.

(88) According to Reference numerals 510 and 520, it was confirmed that the input impedance boosting apparatus according to an embodiment obtains a boosting effect 70 times or more when compared to the theoretical value (unboosted Z.sub.IN).

(89) In addition, as a result of measuring 10 multi-chips, it was confirmed that the input impedance boosting apparatus according to an embodiment achieved an input impedance of at least 421M@DC, 147M@1 kHz and only 7% of the area of the entire system was consumed to apply the parasitic replication technique according to one embodiment.

(90) In conclusion, by using the present disclosure, the effect of a parasitic capacitance component can be reduced without additional calibration or trimming.

(91) In addition, by using the present disclosure, an input impedance may be boosted while minimizing power consumption and an increase in cost according to a circuit area.

(92) In addition, by using the present disclosure, an improved impedance boosting performance, compared to existing techniques using a trimming process, can be achieved.

(93) According to an embodiment, the present disclosure can reduce the effect of a parasitic capacitance component without additional calibration or trimming.

(94) According to an embodiment, the present disclosure can boost an input impedance while minimizing power consumption and an increase in cost according to a circuit area.

(95) According to an embodiment, the present disclosure can achieve an improved impedance-boosting performance, compared to existing techniques using a trimming process.

(96) Although the present disclosure has been described with reference to limited embodiments and drawings, it should be understood by those skilled in the art that various changes and modifications may be made therein. For example, the described techniques may be performed in a different order than the described methods, and/or components of the described systems, structures, devices, circuits, etc., may be combined in a manner that is different from the described method, or appropriate results may be achieved even if replaced by other components or equivalents.

(97) Therefore, other embodiments, other examples, and equivalents to the claims are within the scope of the following claims.

DESCRIPTION OF SYMBOLS

(98) TABLE-US-00001 100: input impedance boosting apparatus ADC: analog-to-digital converter C.sub.IN: input capacitor CIN: feedback capacitor 110: first shielding metal 110-1: first parasitic component 120: second shielding metal 120-1: second parasitic component 130: third shielding metal 140: first metal