Hybrid Power Converters

Abstract

Hybrid power converters are presented. The power converters can receive an input voltage at an input node and generate an output voltage at an output node. The power converters can have an inductor coupled between an inductor node and the output node. The power converters can have a first flying capacitor coupled between a first capacitor node and a second capacitor node. The power converters can have a second flying capacitor coupled between a third capacitor node and the inductor node. A first switching element may be coupled between the input node and the first capacitor node, and a fifth switching element may be coupled between the first capacitor node and the third capacitor node. Additionally, a sixth switching element may be coupled between the second capacitor node and the inductor node.

Claims

1) A power converter configured to receive an input voltage at an input node of the power converter and to generate an output voltage at an output node of the power converter, the power converter comprising: an inductor coupled between an inductor node and the output node, a first flying capacitor coupled between a first capacitor node and a second capacitor node, a second flying capacitor coupled between a third capacitor node and the inductor node, a first switching element coupled between the input node and the first capacitor node, and a fifth switching element coupled between the first capacitor node and the third capacitor node.

2) The power converter according to claim 1, wherein the power converter is configured to charge the second flying capacitor by establishing a current path from the input node, via the first switching element, via the fifth switching element, and via the second flying capacitor to a reference potential.

3) The power converter according to claim 1, wherein the power converter is configured to discharge the first flying capacitor and the second flying capacitor by turning off the fifth switching element and by establishing a current path from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

4) The power converter according to claim 1, further comprising a second switching element coupled between the first capacitor node and a reference potential.

5) The power converter according to claim 1, further comprising a third switching element coupled between the second capacitor node and a reference potential.

6) The power converter according to claim 1, further comprising a fourth switching element coupled between the second capacitor node and the third capacitor node.

7) The power converter according to claim 1, further comprising a sixth switching element coupled between the inductor node and a reference potential.

8) The power converter according to claim 1, further comprising a sixth switching element coupled between the inductor node and the second capacitor node.

9) The power converter according to claim 1, wherein the power converter is configured to establish, during a first phase of operation, a first current path from the input node, via the first switching element, and via the first flying capacitor to a reference potential.

10) The power converter according to claim 9, wherein the power converter is configured to establish, during the first phase of operation, a second current path from the input node, via the first switching element, via the fifth switching element, and via the second flying capacitor to the reference potential.

11) The power converter according to claim 9, wherein the power converter is configured to establish, during the first phase of operation, a third current path from the reference potential via the inductor to the output node of the power converter.

12) The power converter according to claim 1, wherein the power converter is configured to establish, during a second phase of operation, a first current path from the input node, via the first switching element, and via the first flying capacitor to a reference potential.

13) The power converter according to claim 12, wherein the power converter is configured to establish, during the second phase of operation, a second current path from the reference potential, via the second flying capacitor, and via the inductor to the output node of the power converter.

14) The power converter according to claim 1, wherein the power converter is configured to establish, during a third phase of operation, a current path from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

15) A power converter configured to receive an input voltage at an input node of the power converter and to generate an output voltage at an output node of the power converter, the power converter comprising: an inductor coupled between an inductor node and the output node, a first flying capacitor coupled between a first capacitor node and a second capacitor node, a second flying capacitor coupled between a third capacitor node and the inductor node, a first switching element coupled between the input node and the first capacitor node, and a sixth switching element coupled between the second capacitor node and the inductor node.

16) The power converter according to claim 15, wherein the power converter is configured to charge the second flying capacitor by establishing a current path from the input node, via the second flying capacitor, and via the sixth switching element to a reference potential.

17) The power converter according to claim 15, wherein the power converter is configured to discharge the first flying capacitor and the second flying capacitor by turning off the sixth switching element and by establishing a current path from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

18) The power converter according to claim 15, further comprising a second switching element coupled between the first capacitor node and a reference potential.

19) The power converter according to claim 15, further comprising a third switching element coupled between the second capacitor node and a reference potential.

20) The power converter according to claim 15, further comprising a fourth switching element coupled between the second capacitor node and the third capacitor node.

21) The power converter according to claim 15, further comprising a fifth switching element coupled between the third capacitor node and the input node of the power converter.

22) The power converter according to claim 15, further comprising a fifth switching element coupled between the third capacitor node and the first capacitor node.

23) The power converter according to claim 15, wherein the power converter is configured to establish, during a first phase of operation, a first current path from the input node, via the first switching element, and via the first flying capacitor to a reference potential.

24) The power converter according to claim 23, wherein the power converter is configured to establish, during the first phase of operation, a second current path from the input node, via the second flying capacitor, and via the sixth switching element to the reference potential.

25) The power converter according to claim 23, wherein the power converter is configured to establish, during the first phase of operation, a third current path from the reference potential, via the sixth switching element, and via the inductor to the output node of the power converter.

26) The power converter according to claim 15, wherein the power converter is configured to establish, during a second phase of operation, a first current path from the input node via the first flying capacitor to a reference potential.

27) The power converter according to claim 26, wherein the power converter is configured to establish, during the second phase of operation, a second current path from the reference potential, via the second flying capacitor, and via the inductor to the output node of the power converter.

28) The power converter according to claim 15, wherein the power converter is configured to establish, during a third phase of operation, a current path from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

29) A method of operating a power converter, the power converter comprising an inductor coupled between an inductor node and an output node of the power converter, a first flying capacitor coupled between a first capacitor node and a second capacitor node, and a second flying capacitor coupled between a third capacitor node and the inductor node, the method comprising: charging the second flying capacitor by establishing a charging current via a switching element, wherein said switching element is coupled between the first capacitor node and the third capacitor node, and discharging the second flying capacitor by establishing a discharging current when said switching element is turned off.

30) The method of claim 29, wherein establishing the charging current further comprises establishing the charging current from the input node, via another switching element, via the switching element, and via the second flying capacitor to the reference potential.

31) The method of claim 29, wherein establishing the discharging current further comprises establishing the discharging current from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

32) A method of operating a power converter, the power converter comprising an inductor coupled between an inductor node and an output node of the power converter, a first flying capacitor coupled between a first capacitor node and a second capacitor node, and a second flying capacitor coupled between a third capacitor node and the inductor node, the method comprising: charging the second flying capacitor by establishing a charging current via a switching element, wherein said switching element is coupled between the second capacitor node and the inductor node, and discharging the second flying capacitor by establishing a discharging current when said switching element is turned off.

33) The method of claim 32, wherein establishing the charging current further comprises establishing the charging current from the input node, via the second flying capacitor, via the switching element, and via another switching element to the reference potential.

34) The method of claim 32, wherein establishing the discharging current further comprises establishing the discharging current from a reference potential, via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings in which like reference numerals refer to similar or identical elements, and in which

[0031] FIG. 1 shows an exemplary inverting buck converter;

[0032] FIG. 2 shows a buck magnetizing phase for the inverting buck converter of FIG. 1;

[0033] FIG. 3 shows a buck demagnetizing phase for the inverting buck converter of FIG. 1;

[0034] FIG. 4 shows voltage ratings for the FET devices for the inverting buck converter of FIG. 1;

[0035] FIG. 5 an exemplary dual-stage converter based on the converter in FIG. 1 enabling V.sub.OUT=−2V.sub.IN (ideally);

[0036] FIG. 6 shows voltage ratings of the FET devices of the converter from FIG. 5;

[0037] FIG. 7 shows a buck magnetizing phase for the converter of FIG. 5;

[0038] FIG. 8 shows a buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase for the converter of FIG. 5;

[0039] FIG. 9 shows a boost demagnetizing phase/buck-boost demagnetizing phase for the converter of FIG. 5;

[0040] FIG. 10 shows a timing diagram of the converter of FIG. 5 when operating in boost mode;

[0041] FIG. 11 shows an exemplary hybrid inverting buck-boost topology;

[0042] FIG. 12 shows a buck magnetizing phase of the converter of FIG. 11;

[0043] FIG. 13 shows a buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase for the converter of FIG. 11;

[0044] FIG. 14 shows a boost demagnetizing phase/buck-boost demagnetizing phase for the converter of FIG. 11;

[0045] FIG. 15 shows an exemplary hybrid inverting buck-boost variant with low voltage rating for switch S5;

[0046] FIG. 16 shows an exemplary hybrid inverting buck-boost variant with low voltage rating for switch S6;

[0047] FIG. 17 shows a buck magnetizing phase of the converter of FIG. 15;

[0048] FIG. 18 shows a buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase for the converter of FIG. 15;

[0049] FIG. 19 shows a boost demagnetizing phase/buck-boost demagnetizing phase for the converter of FIG. 15;

[0050] FIG. 20 shows a buck magnetizing phase of the converter of FIG. 16;

[0051] FIG. 21 shows buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase for the converter of FIG. 16;

[0052] FIG. 22 shows a boost demagnetizing phase/buck-boost demagnetizing phase for the converter of FIG. 16; and

[0053] FIG. 23 shows voltage ratings of the FET devices of the hybrid converter of FIG. 11 and its variants of FIG. 15 and FIG. 16.

DESCRIPTION

[0054] The inverting-buck topology shown in FIG. 1 is used to generate a negative output voltage V.sub.OUT down to −V.sub.IN (theoretically). In mobile applications, the input voltage V.sub.IN is typically generated by a single cell Li-Ion battery.

[0055] FIGS. 2 and 3 show exemplary switching phases of the converter of FIG. 1. The converter cycles through phases of FIG. 2 and FIG. 3 It is equivalent to a conventional buck DC-DC converter: the voltage swing at the LX node is filtered by a second order low pass filter (inductor L and output capacitor C.sub.OUT) and the output voltage V.sub.OUT is taken from the non-grounded terminal of the output capacitor C.sub.OUT.

[0056] The operation of the inverting buck converter consists of: [0057] magnetization phase shown in FIG. 2. The switches S1 and S3 are closed, thus the voltage of nodes VCX and VLX goes to V.sub.IN and PGND, respectively. The flying capacitor C.sub.FLY is charged to V.sub.IN (theoretically), while the inductor is magnetized with V.sub.OUT/L current slope. [0058] The switch S2 is open, thus it experiences a drain-source voltage V.sub.DS=V.sub.IN. [0059] demagnetization phase shown in FIG. 3. The only involved switch is S2: once this FET is turned on, the voltage of node VLX goes below PGND (i.e. to −V.sub.IN). The flying capacitor C.sub.FLY is discharged to the output node, while the inductor is demagnetized with —(V.sub.IN+V.sub.OUT)/L current slope. The switches S1, S3 are open, thus they experience a drain-source voltage V.sub.DS=V.sub.IN in absolute value.

[0060] The relationship between V.sub.IN and V.sub.OUT is expressed by V.sub.OUT/V.sub.IN=−(1−D), wherein D denotes a duty cycle with D∈[0,1]. The voltage rating (i.e. the maximum V.sub.DS voltage V.sub.DS_max) for the FET devices is summarized in the table illustrated in FIG. 4.

[0061] The converting cell shown in FIG. 1 can be replicated in order to achieve a lower output voltage V.sub.OUT. FIG. 5 shows how a theoretical V.sub.OUT=−2V.sub.IN can be achieved by putting in series two of the basic cells that create the converter shown in FIG. 1.

[0062] The converter represented in FIG. 5 cycles through phases of FIGS. 7, 8, and 9. It is equivalent to a conventional buck DC-DC converter: the voltage swing at the LX node (PGND, −VIN or −2VIN) is filtered by a second order low pass filter (inductor L and output capacitor COUT). The output voltage VOUT is taken from the non-grounded terminal of the output capacitor COUT as done for converter in FIG. 1.

[0063] The converter of FIG. 5 operates in the following switching phases: [0064] The buck operation cycles through magnetization phase shown in FIG. 7 and buck demagnetization phase in FIG. 8. [0065] During the magnetization phase, both flying capacitors are recharged to V.sub.IN through switches S1, S3 and S5, S6. The switch S6 connects the VLX node to PGND. The inductor is magnetized with V.sub.OUT/L current slope. During the demagnetization phase, the flying capacitor C.sub.FLY1 is parked, i.e. connected between the input voltage V.sub.IN and PGND through switches S1 and S3. When parked, the capacitor voltage may be kept constant at V.sub.IN. The second flying capacitor C.sub.FLY2 is connected between PGND—using switches S3 and S4—and the VLX node. In this configuration, the voltage goes negative at VLX node. The inductor is demagnetized with (−V.sub.IN−V.sub.OUT)/L current slope. [0066] A first possible boost operation cycles through magnetization phase shown in FIG. 8 and demagnetization phase in FIG. 9. During the magnetization phase, the flying capacitor C.sub.FLY1 is parked, i.e. connected between V.sub.IN and PGND through switches S1 and S3. The second flying capacitor C.sub.FLY2 is connected between PGND—using switches S3 and S4—and the VLX node. In this configuration, the voltage goes negative at VLX node. The inductor is magnetized with (−V.sub.IN−V.sub.OUT)/L current slope. During the boost demagnetization phase C.sub.FLY1 and C.sub.FLY2 are connected in series through switch S4. The node VCX1 is connected to PGND through switch S2, therefore the node VLX goes to −2V.sub.IN. [0067] We should observe that switches S5, S6 are both experiencing V.sub.DS=2V.sub.IN voltage in this phase. The inductor is demagnetized with (−2V.sub.IN−V.sub.OUT)/L current slope. The relationship between V.sub.IN and V.sub.OUT for this boost mode is expressed by V.sub.OUT/V.sub.IN=−(2−D), with D∈[0,1]. In addition, we should also note that the first possible boost operation described above cannot be sustained for indefinite time as the flying capacitor C.sub.FLY2 has to be recharged (through a buck magnetization phase). [0068] A time-independent boost operation cycles through phases of FIG. 7—flying capacitors recharge—and FIG. 9—VLX node at −2V.sub.IN. This configuration increases the voltage ripple across the coil with respect to the boost mode described before. [0069] The relationship between V.sub.IN and V.sub.OUT for the time-independent boost mode is expressed by: V.sub.OUT/V.sub.IN=−2(1−D), with D∈[0,1]. [0070] The buck-boost operation cycles through phases of FIG. 7, FIG. 8, and FIG. 9. This operation may involve all switches.

[0071] The voltage rating (maximum V.sub.DS voltage V.sub.DS_max) for the FET devices of the converter in FIG. 5 is summarized in the table in FIG. 6. A higher voltage rating translates into a higher R.sub.sp for the device and, in turn, into a larger silicon area for a given target on-resistance R.sub.ON of a FET device.

[0072] The converter of FIG. 5 has a fundamental output voltage V.sub.OUT limitation during its boost operation—assuming the time-independent boost mode which cycles between phase in FIG. 7 and FIG. 9. The timing diagram of the converter during boost operation is shown in FIG. 10. The limitation is a consequence of the charge conservation on both flying capacitors C.sub.FA: the charge removed from the capacitors during the boost demagnetizing phase (see FIG. 9) is added during the boost magnetizing phase (see FIG. 7). Therefore, the current I.sub.FLY flowing in C.sub.FLY1 during the demagnetizing phase can be expressed as (by applying charge conservation principle): I.sub.OUT/I.sub.CFLY1=D/(1−D), with D∈[0,1]. The latter equation indicates that in order to keep I.sub.CFLY1<I.sub.OUT, the duty cycle D should be limited to 0.5. For values of D>0.5, the current I.sub.cy experiences a steep increase. Similar considerations apply to the second flying capacitor CFLY2.

[0073] A further hybrid inverting converter is shown in FIG. 11. In this topology, the switch S5 connects the node VCX2 (also denoted as the third capacitor node) to the input node VIN through the switch S1. At this, switch S5 is arranged in between node VCX1 (also denoted as the first capacitor node) and node VCX2 (i.e. the third capacitor node). Moreover, switch S6 connects the VLX node (also denoted as the inductor node) to PGND through the switch S3. At this, switch S6 is arranged in between node VLX (i.e. the inductor node) and node VCY (also denoted as the second capacitor node). These connections allow low voltage rating FETs for both S5 and S6 as they are in parallel to one flying capacitor when turned-off during the converter operation. In other words, in FIG. 11, the VLX terminal and VCY terminal may be shorted during a buck magnetization phase, and the VCX1 terminal and VCX2 terminal may be shorted during a buck magnetization phase.

[0074] FIG. 12, FIG. 13, and FIG. 14 show the switching phases of the hybrid inverting converter of FIG. 11. The operation of this topology is the similar to the operation of the converter in FIG. 5. However, it uses lower voltage rated devices for switches S5 and S6: [0075] The buck operation cycles through phases of FIG. 12 and FIG. 13. It is equivalent to a conventional inverting buck involving only the second flying capacitor CFLY2. Switches S1, S5, S3, S6 are closed so that both flying capacitors CFLY are connected between VIN and PGND during the flying capacitor recharge. [0076] A boost operation cycles through phases of FIG. 13 and FIG. 14. As described before, this operation cannot be sustained for indefinite time as the flying capacitor CFLY2 has to be recharged (e.g. through the buck magnetization phase illustrated in FIG. 12). A time-independent boost mode operation cycles through phases of FIG. 12 and FIG. 14. During boost operating mode, none of the instantiated switches is exposed to a drain-source voltage V.sub.DS>C.sub.IN. [0077] The buck-boost operation cycles through phases of FIG. 12, FIG. 13, and FIG. 14 and may involve all switches.

[0078] Two variants can be derived from the topology of FIG. 11: On the one hand, FIG. 15 shows a hybrid buck-boost variant with low voltage rating for switch S5. This switch operates in parallel to the first flying capacitor C.sub.FLY1, therefore a reduced voltage rate is enabled. On the other hand, FIG. 16 shows a hybrid buck-boost variant with low voltage rating for switch S6. This switch operates in parallel to the second flying capacitor C.sub.FLY2, therefore a reduced voltage rate is enabled.

[0079] The above-described hybrid buck-boost variants exploit the operating phases described before for the architecture of FIG. 11. FIG. 17 to FIG. 22 depict the corresponding switching phases. Specifically, FIG. 17 shows a buck magnetizing phase (also denoted as first phase of operation) of the converter of FIG. 15. FIG. 18 shows a buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase (also denoted as second phase of operation) for the converter of FIG. 15. FIG. 19 shows a boost demagnetizing phase/buck-boost demagnetizing phase (also denoted as third phase of operation) for the converter of FIG. 15. FIG. 20 shows a buck magnetizing phase (also denoted as first phase of operation) of the converter of FIG. 16. FIG. 21 shows buck demagnetizing phase/boost magnetizing phase/buck-boost bypass phase (also denoted as second phase of operation) for the converter of FIG. 16. FIG. 22 shows a boost demagnetizing phase/buck-boost demagnetizing phase (also denoted as third phase of operation) for the converter of FIG. 16.

[0080] The voltage ratings for the devices of these hybrid converter topologies are reported in the table in FIG. 23. In particular, FIG. 23 compares the voltage rating for the topology of FIG. 11 (new hybrid), the topology of FIG. 15 (variant LV S5), and the topology of FIG. 16 (variant LV S6). Because of the reduced V.sub.DS_max for the switches, devices with lower R.sub.SP can be used to lower silicon area while achieving higher V.sub.OUT for a given I.sub.OUT and V.sub.IN or lower V.sub.IN for a given V.sub.OUT and I.sub.OUT.

[0081] The hybrid buck-boost architectures of FIG. 11 and its variants of FIG. 15 and FIG. 16 have the same trade-off explained for the architecture of FIG. 5 between V.sub.OUT_max and I.sub.OUT because of the charge conservation on both flying capacitors C.sub.FLY. However, the use of devices rated for lower V.sub.DS voltage allows to reduce the IR drop developed on switches S5 and S6 while occupying less area on silicon. The presented hybrid topology and its variant can also be used either at input or at output pin of a DC-DC converter in order to double the input voltage or the output voltage, respectively.

[0082] In conclusion, for the same target impedance of the power FETs, the topologies of this invention occupy lower area while achieving higher V.sub.OUT for a given load current. Alternatively, lower V.sub.IN voltages could be achieved for the same V.sub.OUT voltages and load current I.sub.OUT.

[0083] An additional advantage of the proposed invention with respect to traditional inverting buck-boost architectures is the fast response and low noise output voltage. The presented topologies require a coil connected between LX node and the output node, like a buck converter. It allows delivering current to the output during both coil magnetizing and demagnetizing phases, i.e. no Right Half-Plane Zero (RHPZ) impacts the frequency response of the presented architectures.

[0084] Moreover, the LC filter at the output of the converter dramatically reduces the high frequency noise that would otherwise be generated by discontinues current delivery to the output.

[0085] It should be noted that the description and drawings merely illustrate the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements that, although not explicitly described or shown herein, embody the principles of the invention and are included within its spirit and scope. Furthermore, all examples and embodiment outlined in the present document are principally intended expressly to be only for explanatory purposes to help the reader in understanding the principles of the proposed methods and systems. Furthermore, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.