FOUNDRY-COMPATIBLE PROCESS FOR INTEGRATED MICRO-SPEAKER AND MICROPHONE

Abstract

A MEMS audio device includes a first substrate having a first surface, a cavity, and a first vent hole formed through the first substrate, a device layer disposed upon the first substrate comprising a semiconductor material sandwiched between a first and second oxides, wherein a portion of the semiconductor material is substantially free of oxide, wherein the first oxide is disposed against the first surface, and wherein the device layer comprises first contacts, a substrate disposed upon the device layer, including a first vent hole formed through the second substrate, and second electrical contacts coupled to the first electrical contacts, wherein the portion of the semiconductor material forms a diaphragm for the MEMS audio device and wherein the diaphragm is configured to move within the first cavity.

Claims

1. A method for forming a Micro-Electric Mechanical System (MEMS) audio device comprising: receiving a first wafer comprising a first substrate characterized by a first surface, wherein a first cavity is formed within the first substrate; disposing a device layer upon the first wafer, wherein the device layer comprises a semiconductor material having a first side and a second side, wherein the semiconductor material comprises a first semiconductor material portion, wherein a first material layer is formed upon the first side, wherein a second material layer is formed upon the second side, wherein a first portion of the first material layer is disposed above the first semiconductor material portion, wherein a first portion of the second material layer is disposed below the first semiconductor material portion, and wherein the first material layer is disposed against the first surface; forming a first plurality of contacts through the second material layer to at least the semiconductor material; receiving a second substrate wafer, wherein a plurality of metal layers are disposed within the second substrate, wherein a first plurality of vent holes are formed through the second substrate, and wherein a second plurality of contacts are formed on a first surface of the second substrate; coupling the first plurality of contacts to the second plurality of contacts; forming a second plurality of vent holes through the first substrate, wherein a first vent hole from the second plurality of vent holes is coupled to the first cavity; etching at least the first portion of the first material layer and the first portion of the second material layer from around the first semiconductor material portion; and wherein the first portion of the semiconductor material forms a diaphragm for the MEMS audio device configured to move within the first cavity.

2. The method of claim 1 wherein the second substrate wafer comprises a CMOS device wafer having a plurality of active devices.

3. The method of claim 1 wherein the MEMS audio device is selected from a group consisting of: a speaker and a microphone.

4. The method of claim 1 wherein the first portion of the semiconductor material forms a diaphragm for a speaker configured to move within the first cavity; wherein a second cavity is formed within the first substrate of the first wafer; wherein the semiconductor material comprises a second semiconductor material portion; wherein a second portion of the first material layer is disposed above the second semiconductor material portion; wherein a second portion of the second material layer is disposed below the second semiconductor material portion, and wherein the first material layer is disposed against the first surface; wherein a second vent hole from the second plurality of vent holes is coupled to the second cavity; wherein the method further comprising: etching at least the second portion of the first material layer and the second portion of the second material layer from around the second semiconductor material portion; and wherein the second portion of the semiconductor material forms a diaphragm for a microphone configured to move within the second cavity.

5. The method of claim 1 wherein the forming the first plurality of electrical contacts comprises: etching through at least a first portion of the second material layer to define a plurality of contact regions; disposing a conductive semiconductor material layer above the second material layer and into the plurality of contact regions; and etching at least a first portion of the conductive semiconductor material layer to define the first plurality of electrical contacts comprising conductive semiconductor material.

6. The method of claim 5 wherein the etching at least the first portion of the conductive semiconductor material layer further comprises: etching at least a second portion of the conductive semiconductor material layer to define a conductive structure disposed above a second portion of the second material layer and above the diaphragm; wherein the conductive structure comprises conductive semiconductor material; and wherein the conducive structure forms a backplane of a microphone.

7. The method of claim 1 wherein the etching at least the first portion of the first material layer and the first portion of the second material layer from around the first semiconductor material portion comprises: providing vapor hydrofluoric acid into the first cavity.

8. The method of claim 1 further comprising: performing a deep reactive ion etching (DRIE) process to the second substrate to form the first plurality of vent holes.

9. The method of claim 5 wherein a distance between the diaphragm and an electrode of the MEMS audio device comprises a thickness of the conductive semiconductor layer.

10. The method of claim 5, where the semiconductor material comprises a polysilicon layer deposited in an epitaxial reactor or with Low Pressure Chemical Vapor Deposition (LPCVD).

11. A Micro-Electric Mechanical System (MEMS) audio device comprising: a first wafer comprising a first substrate characterized by a first surface and comprising a first cavity within the first substrate, wherein the first substrate comprises at least a first vent hole formed through the first substrate and coupled to the first cavity; a device layer disposed upon the first wafer, wherein the device layer comprises a semiconductor material having a first side and a second side, wherein a first material layer is formed upon a portion of the first side, wherein a second material layer is formed upon a portion the second side, wherein the semiconductor material comprises a first semiconductor material portion substantially free of the first material layer and the second material layer, wherein the first material layer is disposed against the first surface of the first wafer, and wherein the device layer comprises a first plurality of electrical contacts; a second substrate wafer disposed upon the device layer, wherein the second substrate comprises at least a first vent hole formed through the second substrate and coupled to the first cavity, and wherein the second substrate wafer comprises a second plurality of electrical contacts coupled to the first plurality of electrical contacts; and wherein the first portion of the semiconductor material forms a diaphragm for the MEMS audio device and wherein the first portion of the semiconductor material is configured to move within the first cavity.

12. The device of claim 11 wherein the MEMS audio device is selected from a group consisting of: a speaker and a microphone.

13. The device of claim 11 wherein the second substrate wafer comprises a CMOS wafer having a plurality of active devices.

14. The device of claim 11 wherein the first wafer further comprises a second cavity within the first substrate, wherein the second substrate comprises a second vent-hole formed through the first substrate and coupled to the second cavity; wherein the semiconductor material comprises a second semiconductor material portion substantially free of the first material layer and the second material layer; wherein the second substrate comprises at least a second vent hold formed through the second substrate and coupled to the second cavity; wherein the second portion of the semiconductor material forms a diaphragm for another MEMS audio device; and wherein the second portion of the semiconductor material is configured to move within the second cavity.

15. The device of claim 14 further comprising: a first electrode associated with the diaphragm for the MEMS audio device, wherein a first distance is associated with a distance between the diaphragm for the MEMS audio device and the first electrode; a second sense electrode associated with the diaphragm for the other MEMS audio device, wherein a second distance is associated with a distance between the diaphragm for the other MEMS device and the second electrode; and wherein the first distance is larger than the second distance.

16. The device of claim 15 wherein the first distance is within a range of 4 to 40 microns; and wherein the second distance is within a range of 0.1 to 5 micron.

17. The device of claim 11 wherein the semiconductor material comprises a second semiconductor material portion; and wherein the first plurality of electrical comprises a second semiconductor material portion.

18. The device of claim 17 wherein the semiconductor material comprises a third semiconductor material portion disposed below a portion of the diaphragm; and wherein the third semiconductor material portion forms a backplane of the MEMS audio device.

19. The device of claim 11 further comprising a CMOS device coupled to the second substrate, wherein the CMOS device comprises an audio function selected from a group consisting of: an amplifier, an audio driver, an encoder, a decoder, a signal processor, a digital signal processor.

20. A method for forming a Micro-Electric Mechanical System (MEMS) audio device comprising: receiving a first wafer comprising a first substrate characterized by a first surface, wherein a first cavity is formed within the first substrate; disposing a first side of a device layer upon the first wafer, wherein the device layer comprises a material, and wherein a first portion of the material is disposed adjacent to the first cavity having a first side and a second side; forming a first plurality of electrical contacts to at least the material; receiving a wafer having a second substrate, wherein a plurality of active devices are disposed within the second substrate; disposing a second side of the device layer upon the wafer, wherein at least an electrical contact from the first plurality of electrical contacts is coupled to an active device from the plurality of active devices; and wherein the first portion of the material forms a diaphragm for the MEMS audio device that is configured to move within the first cavity.

21. The method of claim 20 wherein the method further comprises: etching a first vent hole through the first substrate proximate to the first cavity; and etching a second vent hole through the second substrate proximate to the diaphragm.

22. The method of claim 20 wherein the device layer comprises a material disposed between layers of a sacrificial material; wherein a portion of the layer of sacrificial material is disposed upon the first portion of the material; and wherein the method further comprises: etching the portion of the layer of sacrificial material from the first portion of the material.

23. The method of claim 20 wherein the MEMS audio device is selected from a group consisting of: a MEMS speaker, a MEMS microphone.

24. The method of claim 20 wherein the material is selected from a group consisting of: a silicon material, polysilicon, and graphene.

25. A method of fabricating a Micro-Electric Mechanical System (MEMS) speaker device using a foundry compatible process, the method comprising: providing a semiconductor substrate comprising a plurality of CMOS cells, a first surface and a second surface opposing the second surface, the CMOS cells comprising a drive circuit, and the semiconductor substrate configured with one or more electrodes formed on the first surface of the semiconductor substrate and the one or more electrodes being configured with the drive circuit for supplying a voltage potential to the one or more electrodes; and bonding the first surface of the semiconductor substrate to a MEMS semiconductor substrate device, the MEMS semiconductor substrate device comprising a MEMS speaker device configured from a diaphragm device coupled to a frame configured within the semiconductor substrate such the one or more electrodes from the semiconductor substrate are operably coupled to the diaphragm device to generate an audio signal upon actuating of the diaphragm device using the voltage potential generated from the drive circuit.

Description

BRIEF DESCRIPTION OF FIGURES

[0025] In order to more fully understand the present invention, reference is made to the accompanying drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently described embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings in which:

[0026] FIG. 1 is a simplified diagram of some embodiments;

[0027] FIGS. 2A-I illustrates results of process steps according to some embodiments of the present invention;

[0028] FIG. 3 shows cross section of a packaged embodiment; and

[0029] FIGS. 4A-B illustrate a device configuration according to some embodiments.

DETAILED DESCRIPTION

[0030] According to various embodiments, techniques directed to fabrication of an integrated micro-speaker and microphone using Micro Electro Mechanical Systems MEMS are provided. In particular, some embodiments of the present invention disclose a Foundry compatible process for fabricating a MEMS speaker device and/or a MEMS microphone device. The terminology micro-speaker and speaker has been interchangeably used with both implying a device that can generate sound wave. Although the invention has been described in terms of specific examples, it will be recognized that the invention has a much broader range of applicability.

[0031] FIG. 1 is a simplified diagram showing a set of wafers that are used in the fabrication of the process described in some embodiments. A device 100 typically includes a MEMS handle wafer 102, a device wafer 104 (with material (e.g. oxide) layers 108 and 110) and a CMOS wafer 106. In some embodiments, material layers 108 and/or 110 may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, or other material that may be etched (e.g. vapor etched), as disclosed below. In some embodiments, wafers 102, 104 and 106 are silicon-based wafers/media. In other embodiments, wafer 104 may be semiconductor, polysilicon, carbide, graphite, or the like. For sake of convenience, reference to oxide layers 108 and 110 and semiconductor material wafer 102, 106, and 108, are used, below.

[0032] In some embodiments, MEMS wafer 102 and device wafer 104 may be processed asynchronously from the processing of CMOS wafer 106. In particular, as is illustrated in FIGS. 2A-G, MEMS wafer 102 and device wafer 104 may be processed, combined, and further processed. The combination is then bonded with CMOS wafer 106, and then further processed.

[0033] FIGS. 2A-E illustrate results of various foundry-compatible processing steps of embodiments of the present invention. FIG. 2A illustrates a MEMS handle wafer 200, with cavities 202 and 204 that are intended for housing a micro speaker and a microphone. In various embodiments, cavities 202 and 204 are etched from MEMS wafer 200 using a single Deep Reactive Ion Etching (DRIE) process which may result in cavities 202 and 204 being approximately the same depth. In some embodiments, the planar dimension of the cavity and the depth of a cavity for a microphone may be different than for a speaker. As an example, the cavity depth for the microphone may be few microns to few tens of microns which may be shallower than the cavity depth for a speaker. The area for the cavity etch is defined using a photolithography process using a mask associated with this step. In some embodiments, if the cavity depths for micro-speaker and the microphone are to be different, then two separate masks and two separate DRIE processes may be needed to accomplish this step.

[0034] In some embodiments, a series of grooves, bumps, ridges or other type of geometric structure may be etched or otherwise formed on the sidewalls and/or bottoms of cavities 202 (e.g. 205 and 207) and/or 204. These geometric structures may be used to inhibit stiction of a movable diaphragm (discussed below), disposed within cavities 202 and/or 204, against the sidewalls (e.g. 205) or bottoms (e.g. 207) of respective cavities 200 and/or 204.

[0035] FIG. 2B illustrates a result of subsequent processes. In these processes, a device wafer (e.g. device wafer 104 having oxide layers 108 and 110), is bonded to wafer 200. In some cases, a fusion bonding process may be used. In this example, oxide layer 108 appears as oxide layer 206, and a portion of device layer 104 appears as layer 208.

[0036] After the wafer bonding, oxide layer 108 and device layer 104 are grinded down to obtain the desired thickness for a diaphragm layer 208. This process step can be accomplished. for example, using Chemical Mechanical Planarization (CMP), polishing, or the like. In various embodiments, portions of diaphragm layer 208 are used as a diaphragm for a micro-speaker, a microphone, or the like. In various embodiments, an initial thickness of the device wafer 104 may be a few hundred microns, and a thickness of diaphragm layer 208 can range from fractions of micrometers to a few micrometers. Alternatively, the device diaphragm can be deposited with the desired thickness as polysilicon using Low Pressure Chemical Vapor Deposition (LPCVD), or the like, rather than being thinned from an existing thick layer of silicon.

[0037] In various embodiments, photo lithographical steps may then be performed upon diaphragm layer 208 to define, the speaker diaphragm 210, the microphone diaphragm 212, and other mechanical elements (e.g. springs that couple diaphragms 208 and 210 to wafer 200, and the like). Subsequently, a silicon dioxide layer 214 may be deposited, to passivate the top and the side walls of the etched device layer 208, including structures 210 and 212, and the like, to protect them from the subsequent etching steps via LPCVD, Plasma Enhanced Chemical Vapor Deposition (PECVD), or the like.

[0038] FIG. 2C illustrates a result of subsequent processes. In various embodiments, a photo resist layer (not shown) may be deposited on layer 214 and an oxide etching process can be performed to form notches 216. As will be illustrated below, notches 216 may be used to create polysilicon bumps or the like. The polysilicon bumps will provide a reduced gap between the microphone diaphragm 212 and a sensing surface (shown below) to provide higher sensitivity for the microphone. In some embodiments, structures such as mechanical stoppers or bumps, can be created using notches 216 or the like to limit the out of plane motion of the microphone diaphragm. Portions of unpatterned regions on layer 214 will be used to define an air gap, as will be illustrated below. In other embodiments, other processes may be used.

[0039] In additional embodiments, the photoresist layers or additional photoresist layers (not shown) may also be deposited on layer 214 and etching processes can be performed to define various contact regions, e.g. 218, 220, 222, etc. These contact regions allow electrical contact between subsequent layers and the mechanical device layers illustrated. In some embodiments, oxide reactive ion etching (RIE) may be used in contact regions such as 220, and oxide RIE and silicon RIE may be used in contact regions 218 and 222, or the like.

[0040] FIG. 2D illustrates a result of subsequent process steps. In various embodiments, a silicon material layer 224 is then deposited on top of the device wafer of FIG. 2C, and can fill contact regions 218, 220, 222, etc. In some instances, silicon material layer 224 may be conductive polysilicon or other conductive material. Material layer 224 may be formed in a number of ways, such as deposited in a high temperature epitaxial reactor (epi-poly) or deposited at lower temperature with the process of Low Pressure Chemical Vapor Deposition (LPCVD), or the like. In various embodiments, the thickness 228 of the silicon layer 224 can vary from hundreds of nanometers to a few tens of micro-meters. As will be understood from subsequent steps, the thickness 228 may be related to a designed vertical cavity gap needed for the micro speaker and microphone. This vertical cavity gap is directed to the out of plane motion (e.g. up and down) of diaphragms 208 and 210. In various embodiments, a CMP step may optionally then be applied to polish the surface of the sacrificial silicon 224 and to achieve the desired thickness 228.

[0041] In various embodiments, a conductive material layer 226, such as Germanium or similar material is then sputtered on top of silicon material layer 224. In some examples, Germanium is used for enabling bonding such as Eutectic bonding using, for example, Aluminum-Germanium (AlGe) bond, as will be seen in subsequent steps. In other embodiments, other types of bonding are contemplated, such as fusion bonding, and the like.

[0042] FIG. 2E illustrates a result of subsequent process steps. In various embodiments, conductive material layer 226 may be patterned by any conventional process, e.g. photoresist, plasma, etc., to form a number of Eutectic bonding sites, e.g. 230, 232, etc. Additionally a photoresist layer (not shown) may be deposited upon the top surface of this wafer, and various etching techniques may be performed to etch material layer 224 as shown. In some cases processing steps including RIE, DRIE, or the like may be performed to pattern material layer 224. In some embodiments, these etching processes removes portions of sacrificial silicon layer 224 from an area where a cavity 234 is created. This cavity 234 gives speaker diaphragm 210 space to move vertically. As is illustrated, the height 236 of cavity 234 above diaphragm 210 is approximately the thickness 228 of the silicon material layer 224 that was etched away to create the cavity. Additionally, the etching process removes portions of silicon layer 224 from an area where a backplate 238 is formed. In some embodiments, backplate 238 is used as the sensing clement for microphone diaphragm 212. As is illustrated, the height 240 between backplate 238 and diaphragm 212 is approximately the thickness of oxide layer 214.

[0043] FIG. 2F illustrates a CMOS wafer after conventional processing steps. In this example, CMOS wafer 242 is illustrated including active devices 244 and one or more metal layers 246. Active devices 244 (e.g. transistors, etc.) and metal layers 246 may include circuitry for MEMS handle wafer 200 including microphone and/or micro speaker driving circuitry, reading circuitry, processing circuitry, an amplifier circuitry, an encoder circuitry, a decoder circuitry, a signal processor circuitry, a digital signal processor circuitry, and the like. In some embodiments, the top surface and oxide of the processed CMOS wafer 242 is passivated with Nitride material layer 248 (e.g. SixNy). Layer 248 is typically used to generally protect active devices 244 and metal layers 246, as well to protect these devices from subsequent Vapor Hydrogen Fluoride (VHF) etches described below.

[0044] FIG. 2G illustrates a result of subsequent processing steps. In various embodiments, a backside 250 of the CMOS wafer 242, a surface opposite to the metal layers, may be polished with CMP and/or grinded down to until a desired thickness 252 of CMOS wafer 242 is achieved. Additionally, in some embodiments, vent holes 254 and 256 are etched with RIE, DRIE, or the like in CMOS wafer 242. Locations for vent holes 254 and 256 are typically located in the areas identified on wafer 200 for the speaker (e.g. diaphragm 210) and microphone (e.g. diaphragm 212) as shown in FIG. 2E. In some embodiments, vent holes 254 and 256 may be etched from the top or backside 250 of CMOS wafer 242.

[0045] In various embodiments, pads 258, 260, 262 and the like are exposed through material layer 248. These contact pads (e.g. 258, 260) are locations where CMOS wafer 242 may be electrically coupled to MEMS wafer 200, and contact pads (e.g. 262) may be locations where CMOS wafer 242 will support have wire bonds. In various embodiments, contact pads may be aluminum or other contact material. In the case of aluminum contact pads, the aluminum material may form a eutectic bonds with germanium material (e.g. 226) of device wafer 200.

[0046] FIG. 2H illustrates a wafer bonding process. In various embodiments, device wafer 200 (e.g. the wafer stack of combined device wafer 102 and handle wafer 104) is turned upside down and disposed on CMOS wafer 242. As can be seen in this embodiment, cavity 202 and micro speaker diaphragm 210 may be vertically disposed above vent hole 254, cavity 204, microphone diaphragm 212, and backplate 238 may be vertically disposed above vent hole 256. In some embodiments, vent holes need not be centered above the respective cavities. In other embodiments, multiple micro speakers, multiple microphones, or the like may be disposed within a combined wafer 264.

[0047] As can be seen in this embodiment, germanium bonding site 230 will be disposed upon aluminum contact pad 258, bonding site 232 will be disposed upon contact pad 260, and the like. In some examples, to form a eutectic bond between these respective bonding sites and contact pads, wafers 200 and 242 are typically pressed against each other and heated to approximately 400 degrees C., although different conditions may be used in other examples.

[0048] FIG. 2I illustrates a result of subsequent processing steps. In various embodiments, multiple openings (e.g. holes 266 and 268) or channels (e.g. 270) may be etched through MEMS wafer 200 using an RIE, DRIE process, or the like. In this example, vent hole 266 is typically disposed above cavity 202 and micro speaker diaphragm 210; and vent hole 268 is typically disposed above cavity 204, microphone diaphragm 212 and backplate 238. These vent holes respectively allows soundwaves to pass outwards 272 from the micro speaker diaphragm 210 to the external environment and allows soundwaves to pass inwards 274 from the external environment to the microphone diaphragm 212. Additionally, the multiple holes and channels enable Vapor Hydro Fluoric (VHF) material to enter between MEMS wafer 200 and CMOS wafer 242.

[0049] In various embodiments, combined wafer 264 may then be processed with a Vapor Hydro Fluoric (VHF) etch. As mentioned above, the multiple openings (e.g. 266, 268, 270) are configured to allow VHF to be channeled between MEMS wafer 200 and CMOS wafer 242. In operation, the VHF is used to etch away portions of oxide layers 206 and 214. In particular, portions of oxide layers 206 and 214 surrounding micro speaker diaphragm 210 and associated spring elements are etched away. Further, portions of oxide layer 206 above and surrounding microphone diaphragm 212 and associated spring elements are etched away, and portions of oxide layer 214 between microphone diaphragm 212 and backplate 238 and associated spring elements are etched away. As a result of the above processes, micro speaker diaphragm 210 is suspended and can be directed to move within cavity 202 to generate sound pressure, and microphone diaphragm 212 is suspended and can move relative to backplate 238 to sense sound pressure. As can be seen in FIG. 2I, a distance between diaphragm 212 and backplate (electrode) 238 is height 240, approximately the same thickness as layer 214, before it is etched away, as shown. Further, a distance between diaphragm 210 and backplate (electrode) 278 is height 280. In some embodiments, height 240 may be within a range of 0.1 to 5 microns, 0.3 to 3 microns, 0.5 to 1 microns, or the like; height 280 may be within a range of 4 to 20 microns, 5 to 10 microns, 3 to 7 microns, or the like.

[0050] FIG. 3 illustrates an embodiment of a completed device. In this example, beginning with the embodiment illustrated in FIG. 2I, a MEMS tab portion 276 is removed to expose CMOS bond pads, e.g. contact pad 262. In some embodiments, this can be done by dicing tape or a mechanical fixture that is attached to tabs portion 276 and then removed. In various embodiments, multiple completed devices are thus formed on a wafer.

[0051] At this stage in the process, product-level wafer testing and sorting of devices can be performed by applying signals and receiving data from external test systems via the exposed CMOS bond pads. Next, the wafer is then mounted on a dicing tape, or the like and diced using stealth dicing, or the like. Singulated device dies, e.g. die 302 are then available for assembly as shown in FIG. 3.

[0052] In various embodiments, die 302 is then coupled via an interposer material 304 (e.g. epoxy, resin) to a printed circuit board (e.g. PCB) 306. In various embodiments, a metal housing 306 may be coupled to PCB 306 to provide electrical contacts and isolation of combined wafer 302, and the like. As shown, metal housing 312 typically includes one or more opening 314 where sound pressure from micro speaker 316 can exit metal housing 312 and where sound pressure from external sources can reach microphone 318. In some cases, opening 314 may include a mesh-like material 316 that reduces humidity, dust, dirt or other contaminants from entering metal housing 312.

[0053] In various embodiments, PCB 306 may include a number of metallic contacts or terminals, e.g. 308. In various embodiments, the metallic contacts may be electrically coupled to circuitry within CMOS portion 320 and/or to portions of MEMS portion 322 of combined wafer 302. In one example, wire bonds, e.g. 310 are coupled to contact pads, e.g. 262, and the like.

[0054] In some embodiments, micro speaker 316 may be driven by three different signals: speaker_top, speaker_dia, and speaker_bottom, which may be provided from external sources or internally provided. In this example, CMOS portion 320 provides speaker_top 324 and speaker_dia 326 to MEMS portion 322. As shown, speaker_top 324 is coupled to the top portion 330 of microspeaker 316 cavity. Further, speaker_dia 326 may be coupled to the diaphragm 327 of microspeaker via the above-mention spring/suspension structures. Additionally, speaker_bottom 332 may be coupled to the bottom portion (e.g. backplate 335) of microspeaker cavity 316. In exemplary operation, the audio signals on speaker_top and speaker_bottom are out of phase (opposite phase) and speaker_dia, may be held constant. As an example, speaker_top may vary in time: 20V, 40V, 0V, 20V, while speaker_bottom may vary in time: 20V, 0V, 40V, 20V, and speaker_dia may be held at 20V. In other embodiments, the bias voltages and amplitudes of speaker_top, speaker_bot, and speaker_dia may vary. In one example, the differential signals of speaker_top and speaker_bot causes speaker diaphragm 327 to move out-of plane (e.g. upwards and downwards within microspeaker 316 cavity), thus producing sound.

[0055] In some embodiments, microphone 318 may be driven/sensed by three different signals: mic_top, mic_dia, and mic_bottom, which may be driven/sensed from external sources or internal sources. In this example, CMOS portion 320 provides mic_top 328, mic_dia 330, and mic_bottom 332 to MEMS portion 322. As shown, mic_top 328 is coupled to the top portion 334 of microphone 318 cavity. Further, mic_dia 330 may be coupled to the diaphragm 329 of microphone 318 via the above-mentioned spring/suspension structures. Additionally, mic_bottom 332 may be coupled to the backplate 336. In operation, a DC bias voltage may be applied to mic_bottom and/or mic_dia, and when microphone diaphragm 329 moves out-of-plane movement (e.g. upwards and downwards) in response to a received sound, a change of capacitance across mic_dia 330 and mic_bottom 332 is sensed.

[0056] FIGS. 4A-B illustrate a DRIE process according to various embodiments. As is known, DRIE processes typically generate high impact ions to etch vent holes 254 and 256, as was illustrated in FIG. 2G. Typical drawbacks to using include that the high energy ions can potentially damage other active devices on a fabricated CMOS wafer, such as CMOS wafer 242. Accordingly, a configuration illustrated in FIGS. 4A-B are shown that attempts to limit the impact of the DRIE ions on active devices in the neighboring areas.

[0057] FIG. 4A illustrates a top view 400 of various embodiments. Specifically, FIG. 4A illustrates a structure, e.g. hole 402 etched through a CMOS wafer 404 using a DRIE, RIE, or the like. Also shown are metallic structures 406 that are positioned around where DRIE etching of hole 402 is to be performed, including vias 408. The locations on device where vent holes or other channels are to be etched are known ahead of time, accordingly, during a chip layout, conductive or metallic structures 406, i.e. toroidal rings, may be formed in multiple layers in the device. In various cases, some or all of these conductive structures may be coupled together and may be coupled together by one or more vias 408, to ground, or the like. In the case of buried doped wells within a CMOS wafer, a conductive or metallic structure may separately be tied to ground, or the like.

[0058] FIG. 4B illustrates a perspective section view of FIG. 4A. In this figure, a vent hole area 402 may be created with a DRIE process. In this embodiment, a structure 410 is formed in a Metal 3 layer, a structure 412 is formed in a Metal 2 layer, and a structure 414 is formed in a Metal 1 layer, and the like. In some embodiments, structures may have a similar shape, e.g. toroidal, and in other embodiments, the shapes may be different. As illustrated in this example, multiple vias, e.g. 416 and 418 may be used to electrically couple structures 410, 412 and 414. In other embodiments, a single via may be used, and structures 410, 412 and 414 may be coupled to the single via. In operation, these structures help absorb excess ions generated during the DRIE process and thus preventing the ions from damaging active devices on the CMOS wafer 404. In some examples, the electrically grounded structures formed within the one or more metal layers serve as moats or sinks for the excessive ions that are used to etch through the device. These moats ground the ions so that the ions do not harm or change the characteristics of MOS devices on the CMOS wafer.

[0059] Further embodiments can be envisioned to one of ordinary skill in the art after reading this disclosure. In some embodiments, the wafer identified as CMOS wafer 242 may simply be a wafer with metallic interconnects similar to CMOS wafer 242 shown above, but lack active devices, e.g. transistors, and the like. Bonding of contacts between MEMS handle wafer 200 and wafer 242 may still be performed in some cases. In various embodiments MEMS handle wafer 200 may not be flipped relative to CMOS wafer 242 and stacked upon CMOS wafer 242, as illustrated in FIG. 2H. In some embodiments, MEMS handle wafer 200 and CMOS wafer 242 may be placed or mounted proximate to each other upon a common substrate, e.g. PCB 306, under a common metal housing, e.g. 312 in FIG. 3. Contacts, e.g. 324, 326, 328, 330, 332, and the like shown between MEMS portion 322 and CMOS portion 320 in FIG. 3, may then be facilitated via wire bonding, or the like, similar to wire bond 310.

[0060] In other embodiments, multiple MEMS speakers or MEMS microphones may be formed upon a common MEMS handle wafer 200, using the processes disclosed above. In some embodiments, one MEMS speaker may be optimized for one band of audio output (e.g. midrange), one MEMS speaker may be optimized for another band of audio output (e.g. bass), and the like; and one MEMS microphone may be optimized for one band of audio input (e.g. high frequency), one MEMS microphone may be optimized for another band of audio input (e.g. bass), and the like. In some cases, frequency band directed/cross-over functionality may be implemented by active and/or passive devices formed within CMOS wafer 242, within MEMS handle wafer 200, or via external devices, e.g. discrete passive capacitors, inductors, resistors, and the like disposed upon PCB 306, for example. Additionally, in still other embodiments, one or more MEMS microphones and one or more MEMS speakers may be formed monolithically as was illustrated in the figures above.

[0061] In other embodiments, structures 410, 412, 414, etc. may have different shapes from each other. Further, they may be approximately circles, approximately square, approximately rectangular, approximately polygons (e.g. hexagons), or the like. In some embodiments, structures 410, 412, 414, etc. may not be closed structures, but may be concave structures, e.g. having a C-type shape, a comb shape, etc., where vent hole area 402 may be within the concave area, partially within the concave area, or the like. As an example a structure for a Metal 1 layer may be C-shaped, with an opening to the right, a Metal 2 layer may be a spiral shape with an opening to the left, a Metal 3 layer may be approximately square and have an approximately square hole therein, and the like.

[0062] The block diagrams of the architecture and flow charts are grouped for ease of understanding. However, it should be understood that combinations of blocks, additions of new blocks, re-arrangement of blocks, and the like are contemplated in alternative embodiments of the present invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the invention as set forth in the claims.