PHASE-CHANGE MEMORY MATERIAL, PREPARATION METHOD THEREOF, PHASE-CHANGE MEMORY CHIP, AND DEVICE

Abstract

This application relates to the field of data storage technologies, and specifically, to a phase-change memory material, a preparation method thereof, a phase-change memory chip, and a device. The phase-change memory material includes a material shown by Ti.sub.aSb.sub.bTe.sub.cD.sub.d, where a represents an atom percent of Ti, b represents an atom percent of Sb, c represents an atom percent of Te, d represents an atom percent of an element D, and a+b+c+d=1; 3%a45%, and 0.5(b:c)3; and D is a doping element, and 0d15%. The phase-change memory material has low operation power consumption and a low operation delay.

Claims

1. A phase-change memory material, wherein the phase-change memory material comprises a material shown by a formula (1):
Ti.sub.aSb.sub.bTe.sub.cD.sub.d(1), wherein a represents an atom percent of Ti, b represents an atom percent of Sb, c represents an atom percent of Te, d represents an atom percent of an element D, and a+b+c+d=1; 3%a45%, and 0.5(b:c)3; and D is a doping element, and 0d15%.

2. The phase-change memory material according to claim 1, wherein a value range of the atom percent a of Ti is 20%a35%.

3. The phase-change memory material according to claim 1, wherein a ratio of the atom percent b of Sb to the atom percent c of Te is 2:3.

4. The phase-change memory material according to claim 1, wherein the atom percent d of the doping element D is 3%d8%.

5. The phase-change memory material according to claim 1, wherein the doping element comprises one or a combination of at least two of a first non-metallic element, a first metallic element, and a telluride of the first metallic element, wherein the first non-metallic element is one or a combination of at least two of C, O, N, and Si; and the first metallic element is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn.

6. A phase-change memory chip, comprising a plurality of memory cells, wherein the plurality of memory cells form a memory cell array, and each memory cell comprises: a phase-change layer, a first electrode located on one side of the phase-change layer, and a second electrode located on another side of the phase-change layer, wherein the phase-change layer is made of the phase-change memory material, wherein the phase-change memory material comprises a material shown by a formula (1):
Ti.sub.aSb.sub.bTe.sub.cD.sub.d(1), wherein a represents an atom percent of Ti, b represents an atom percent of Sb, c represents an atom percent of Te, d represents an atom percent of an element D, and a+b+c+d=1; 3%a45%, and 0.5(b:c)3; and D is a doping element, and 0d15%.

7. The phase-change memory chip according to claim 6, wherein a value range of the atom percent a of Ti is 20%a35%.

8. The phase-change memory chip according to claim 6, wherein a ratio of the atom percent b of Sb to the atom percent c of Te is 2:3.

9. The phase-change memory chip according to claim 6, wherein the atom percent d of the doping element D is 3%d8%.

10. The phase-change memory chip according to claim 6, wherein the doping element comprises one or a combination of at least two of a first non-metallic element, a first metallic element, and a telluride of the first metallic element, wherein the first non-metallic element is one or a combination of at least two of C, O, N, and Si; and the first metallic element is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn.

11. The phase-change memory chip according to claim 6, wherein each memory cell further comprises a buffer layer in contact with the phase-change layer, wherein the buffer layer is made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal; and the third metal is one or a combination of at least two of W, Ta, and Ti, and the fourth metal is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn.

12. The phase-change memory chip according to claim 6, wherein each memory cell further comprises at least one phase-change layer and at least one chalcogenide layer, wherein both the at least one phase-change layer and the at least one chalcogenide layer are located between the first electrode and the second electrode, and the at least one phase-change layer and the at least one chalcogenide layer are stacked alternately.

13. The phase-change memory chip according to claim 12, wherein a lattice coefficient of the chalcogenide layer is less than a lattice coefficient of SbTe.

14. A storage device, wherein the storage device comprises a controller and the phase-change memory chip, wherein the phase-change memory chip comprises a plurality of memory cells, wherein the plurality of memory cells form a memory cell array, and each memory cell comprises: a phase-change layer, a first electrode located on one side of the phase-change layer, and a second electrode located on another side of the phase-change layer, wherein the phase-change layer is made of the phase-change memory material, wherein the phase-change memory material comprises a material shown by a formula (1):
Ti.sub.aSb.sub.bTe.sub.cD.sub.d(1), wherein a represents an atom percent of Ti, b represents an atom percent of Sb, c represents an atom percent of Te, d represents an atom percent of an element D, and a+b+c+d=1; 3%a45%, and 0.5(b:c)3; and D is a doping element, and 0d15%.

15. The storage device according to claim 14, wherein a value range of the atom percent a of Ti is 20%a35%.

16. The storage device according to claim 14, wherein a ratio of the atom percent b of Sb to the atom percent c of Te is 2:3.

17. The storage device according to claim 14, wherein the atom percent d of the doping element D is 3%d8%.

18. The storage device according to claim 14, wherein the doping element comprises one or a combination of at least two of a first non-metallic element, a first metallic element, and a telluride of the first metallic element, wherein the first non-metallic element is one or a combination of at least two of C, O, N, and Si; and the first metallic element is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn.

19. The storage device according to claim 14, wherein each memory cell further comprises a buffer layer in contact with the phase-change layer, wherein the buffer layer is made of one of carbon, a third metal, a nitride of the third metal, and a telluride of a fourth metal; and the third metal is one or a combination of at least two of W, Ta, and Ti, and the fourth metal is one or a combination of at least two of Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, and Sn.

20. The storage device according to claim 14, wherein each memory cell further comprises at least one phase-change layer and at least one chalcogenide layer, wherein both the at least one phase-change layer and the at least one chalcogenide layer are located between the first electrode and the second electrode, and the at least one phase-change layer and the at least one chalcogenide layer are stacked alternately.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0042] FIG. 1A is a diagram of a structure of a phase-change memory cell according to an embodiment of this application;

[0043] FIG. 1B is a diagram of a structure of another phase-change memory cell according to an embodiment of this application;

[0044] FIG. 2 is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0045] FIG. 3A is a diagram of a low resistance state of a germanium-antimony-tellurium system phase-change memory material;

[0046] FIG. 3B is a diagram of a high resistance state of a germanium-antimony-tellurium system phase-change memory material;

[0047] FIG. 4A is a diagram of a low resistance state of a phase-change memory material according to an embodiment of this application;

[0048] FIG. 4B is a diagram of a high resistance state of a phase-change memory material according to an embodiment of this application;

[0049] FIG. 5A is a display diagram of a grain size of a phase-change memory material according to an embodiment of this application;

[0050] FIG. 5B is a display diagram of a grain size of a phase-change memory material according to an embodiment of this application;

[0051] FIG. 6 is a display diagram of a resistance-temperature curve of a phase-change memory material according to an embodiment of this application;

[0052] FIG. 7A is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0053] FIG. 7B is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0054] FIG. 7C is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0055] FIG. 7D is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0056] FIG. 7E is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0057] FIG. 8A is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0058] FIG. 8B is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0059] FIG. 8C is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0060] FIG. 8D is a diagram of a structure of a phase-change memory cell array according to an embodiment of this application;

[0061] FIG. 9 is a diagram of a structure of a storage device according to an embodiment of this application; and

[0062] FIG. 10 is a diagram of a structure of an electronic device according to an embodiment of this application.

DESCRIPTION OF EMBODIMENTS

[0063] The following describes technical solutions in embodiments of this application with reference to the accompanying drawings. It is clear that the described embodiments are merely a part of but not all of embodiments of this application.

[0064] In the descriptions of this specification, specific features, structures, materials, or characteristics may be combined in a proper manner in any one or more embodiments or examples.

[0065] It may be understood that in the descriptions of embodiments of this application, a word such as example, for example, or exemplary is used to represent giving an example, an illustration, or a description. Any embodiment or design scheme described as an example, for example, or exemplary in embodiments of this application should not be explained as being more preferred or having more advantages than another embodiment or design scheme. Exactly, use of the word such as example, for example, or exemplary is intended to present a related concept in a specific manner.

[0066] A term and/or in the descriptions of embodiments of this application describes only an association relationship between associated objects and indicates that there may be three relationships. For example, A and/or B may indicate the following three cases: Only A exists, only B exists, and both A and B exist. In addition, unless otherwise stated, a term a plurality of means two or more than two. For example, a plurality of systems mean two or more systems, and a plurality of terminals mean two or more terminals.

[0067] A phase-change memory chip is a chip that stores data by using a conductivity difference shown by a phase-change memory material during conversion of the phase-change memory material between a crystalline state and an amorphous state. Specifically, in the crystalline state, atoms in the phase-change memory material are arranged in order, so that the phase-change memory material has a long-distance atomic energy level and high free electron density, and therefore, the phase-change memory material has low resistivity. Therefore, the crystalline state may be referred to as a low resistance state. In the amorphous state, the atoms in the phase-change memory material are arranged in a disorderly manner, so that the phase-change memory material has a short-distance atomic energy level and low free electron density, and therefore, the phase-change memory material has high resistivity. Therefore, the amorphous state may be referred to as a high resistance state. It may be set that a phase-change memory material in the low resistance state corresponds to one of 0 and 1, and a phase-change memory material in the high resistance state corresponds to the other of 0 and 1.

[0068] When a specific pulse voltage is applied to the phase-change memory material, the phase-change memory material may be converted between the high resistance state and the low resistance state. Specifically, a high and narrow electrical pulse (which may be referred to as a reset pulse) may be applied to the phase-change memory chip, so that the phase-change memory material is converted from the low resistance state to the high resistance state. A low and wide electrical pulse (which may be referred to as a set pulse) may be applied to the phase-change memory chip, so that the phase-change memory material is converted from the high resistance state to the low resistance state. Therefore, a write operation on the phase-change memory material can be implemented.

[0069] In addition, the high resistance state and the low resistance state of the phase-change memory material respectively correspond to different bit values. In this way, a low read voltage (a voltage that cannot cause the phase-change memory material to be converted between the high resistance state and the low resistance state) may be applied to the phase-change memory material, to read a resistance value of the phase-change memory material, and implement a read operation.

[0070] FIG. 1A shows an implementation of a phase-change memory cell 110 and a corresponding selector 120. The phase-change memory cell is a memory cell that is in a phase-change memory chip and that is configured to store one bit value (0 or 1). As shown in FIG. 1A, the phase-change memory cell 110 may include an electrode 111, an electrode 112, and a phase-change layer 113 located between the electrode 111 and the electrode 112. The phase-change layer 113 is made of a phase-change memory material. A voltage or a current is applied to the phase-change layer 113 through the electrode 111 and the electrode 112, to implement a write operation or a read operation.

[0071] During writing, a current or a voltage is applied to a word line 130, so that the word line 130 is at a high potential, and the transistor 120 is conducted. Then, a current or a voltage is applied to a bit line 140, so that the phase-change layer of the phase-change memory cell is converted between a high resistance state and a low resistance state, to perform the write operation. During reading, a column selection circuit adds a small preset potential to the bit line 140 (where the preset potential does not change a resistance state of the phase-change memory cell). As described above, the word line 130 is at the high potential. This affects a potential on the bit line 140, where a magnitude of influence is related to a magnitude of a resistance of the phase-change memory cell. The influence of the word line 130 on the potential on the bit line 140 is equivalent to that the phase-change memory cell outputs a signal, and an influence result (a potential on the bit line 140 after being affected by the word line 130) is equivalent to the output signal. The influence result is compared with a reference potential, to determine a resistance state of the phase-change memory cell, and determine, based on the resistance state, data stored in the phase-change memory cell. The column selection circuit is described below, and details are not described herein.

[0072] FIG. 1B shows another implementation of a phase-change memory cell 110. The phase-change memory cell 110 may include an electrode 111, a phase-change layer 113, an electrode 112, a selection layer 116 (which may also be referred to as a selection tube 116), and an electrode 117 that are sequentially adjacent to each other. The phase-change layer 113 may include a phase-change memory material. A voltage or a current may be applied to the phase-change layer 113 between the electrode 111 and the electrode 112, to implement a write operation or a read operation.

[0073] Specifically, the electrode 112 may be connected to a word line 130 through the selection layer 116 and the electrode 117. When a voltage difference between two ends of the selection layer 116 exceeds a threshold switching voltage Vth of the selection layer 116, the selection layer 116 is conducted, and voltages at the two ends of the selection layer 116 decrease, so that more voltages are applied to two ends of the phase-change layer 113. Therefore, the write operation or the read operation can be implemented.

[0074] In some embodiments, a material of the selection layer 116 is a threshold switching device (ovonic threshold switching, OTS) material including Ge, Se, and As. The OTS material forming the selection layer 116 may be doped with at least one of Si, N, and S. In some embodiments, the material of the selection layer 116 is a GeAsSe alloy. In some embodiments, the material of the selection layer 116 is a GeAsSe alloy doped with at least one of Si, N, C, As, Se, and the like.

[0075] In addition, materials of the phase-change layer 113, the electrode 111, the electrode 112, the electrode 116, and the electrode 117 are described below. In the following descriptions, when no particular distinction is made, the electrode 111, the electrode 112, the electrode 116, and the electrode 117 may be referred to as electrodes for short. FIG. 2 shows a phase-change memory chip, including a phase-change memory cell array and a peripheral circuit. The phase-change memory cell array includes a plurality of phase-change memory cells arranged in a crosswise manner, to form a high-density memory array. A phase-change memory cell 110 may be one phase-change memory cell in the phase-change memory cell array. The phase-change memory cell 110 may use the structure shown in FIG. 1A, or may use the structure shown in FIG. 1B. In addition, when the phase-change memory cell in the phase-change memory cell array is specifically of the structure shown in FIG. 1A, the phase-change memory cell array further includes a selection transistor (not shown in FIG. 2) of the phase-change memory cell. For the phase-change memory cell, when a bit line and a word line are selected at the same time, and a selector is in a conducted state, the phase-change memory cell is in a selected state; otherwise, the phase-change memory cell is in an unselected state. A processor (not shown) may select a word line 130 through a row selection circuit, select a bit line 140 through a column selection circuit, and control a selection transistor 120 to be conducted, to select the phase-change memory cell 110. A read/write (R/W) circuit may receive a command of the processor, control the row selection circuit and the column selection circuit based on the command, and apply a voltage to the phase-change memory cell 110 through the word line 130 and the bit line 140, to perform a read operation or a write operation. A drive circuit VS1 may apply, under control of the row selection circuit, a voltage to the phase-change memory cell 110 through the word line 130, and a drive circuit VS2 may apply, under control of the column selection circuit, a voltage to the phase-change memory cell 110 through the bit line 140.

[0076] The foregoing examples describe structures of the phase-change memory chip and the phase-change memory cell provided in embodiments of this application. The following describes the phase-change memory material.

[0077] Performance in phase-change power consumption (to be specific, energy consumption required for conversion between a high resistance state and a low resistance state), a fatigue life, a phase-change speed (time required for the conversion between the high resistance state and the low resistance state), a thermal stability, and the like of the phase-change memory material has important influence on an operation delay, a life, and reliability of the phase-change memory chip. A conventional germanium-antimony-tellurium (GeSbTe, GST) system phase-change memory material has good thermal stability and a good fatigue life. However, as shown in FIG. 3A and FIG. 3B, the conversion between the high resistance state and the low resistance state involves breaking and recombination of a GeTe bond, which delays a phase-change process (to be specific, a speed of the conversion between the high resistance state and the low resistance state is slow). As a result, the operation delay is high (100 ns level). This cannot fully meet a requirement for a low delay of a storage-class memory (storage-class memory, SCM). Therefore, even if the phase-change memory material is used in the storage-class memory, a delay of the storage-class memory is high.

[0078] An embodiment of this application provides a Ti doped SbTe phase-change memory material. Ti doping improves thermal stability of an SbTe phase-change system, reduces phase-change power consumption, and improves a fatigue life. In addition, existence of a TiTe nucleation center can accelerate crystallization, and therefore, reduce an operation delay. A chemical general formula of the Ti doped SbTe phase-change memory material is: Ti.sub.aSb.sub.bTe.sub.cD.sub.d. a represents an atom percent of a chemical element titanium Ti. To be specific, a represents a proportion of the chemical element titanium Ti in a total quantity of all atoms in the phase-change memory material. b represents an atom percent of a chemical element antimony Sb. To be specific, b represents a proportion of the chemical element antimony Sb in the total quantity of all atoms in the phase-change memory material. c represents an atom percent of a chemical element tellurium Te. To be specific, c represents a proportion of the chemical element tellurium Te in the total quantity of all atoms in the phase-change memory material. d represents an atom percent of a doping element D. To be specific, d represents a proportion of the doping element D in the total quantity of all atoms in the phase-change memory material. In short, a+b+c+d=1.

[0079] In the phase-change memory material provided in this embodiment of this application, 3%a45%. To be specific, the proportion of Ti in the total quantity of all atoms in the phase-change memory material is greater than or equal to 3% and is less than or equal to 45%. In addition, 0.5(b:c)3. To be specific, in the phase-change memory material, a ratio of an atom quantity of Sb to an atom quantity of Te is greater than or equal to 0.5 and less than or equal to 3.0d15%. To be specific, the proportion of the doping element D in the total quantity of all atoms in the phase-change memory material is less than or equal to 15%. In other words, the phase-change memory material may not include the doping element, or may include the doping element, and the atom percentage of the doping element does not exceed 15%.

[0080] The phase-change memory material provided in this embodiment of this application is a new SbTe-based phase-change memory material. When SbTe is crystallized, that is, in a crystalline state, the phase-change memory material is in the low resistance state; or when SbTe is amorphous, that is, in an amorphous state, the phase-change memory material is in the high resistance state. Different resistance states of the phase-change memory material may represent different information, to implement information storage. In addition, the information can be read by measuring the resistance state of the phase-change memory material.

[0081] Refer to FIG. 4A and FIG. 4B. In a phase-change memory material provided in an embodiment of this application, Ti and Te form a TiTe nucleation center, and TiTe has stronger bonding strength than SbTe. When SbTe is converted from a crystalline state (that is, a low resistance state) to an amorphous state (that is, a high resistance state), the TiTe nucleation center can maintain a stable structure. Therefore, the TiTe nucleation center exists in both the low resistance state and the high resistance state of the phase-change memory material. When the phase-change memory material is converted from the high resistance state (that is, the amorphous state) to the low resistance state (that is, the crystalline state), the TiTe nucleation center, as a nucleation center for recrystallization, can increase a crystallization speed of SbTe, so that an operation delay is reduced. Crystallization is a process in which an atomic structure in a material is changed from disorder to orderly arrangement, that is, a process of converting the amorphous state to the crystalline state.

[0082] In addition, a lattice mismatch degree between lattices of TiTe and SbTe is 12%, and Ti is introduced into the phase-change memory material provided in this embodiment of this application. This may cause lattice distortion or a lattice defect of TiSbTe, so that the phase-change memory material is converted from the crystalline state to the amorphous state more easily, and therefore, power consumption required for conversion from the crystalline state to the amorphous state can be reduced.

[0083] In addition, based on an experimental test, Ti included in the phase-change memory material provided in this embodiment of this application can reduce a grain size, and therefore, improve a fatigue life.

[0084] In addition, based on the experimental test, Ti included in the phase-change memory material provided in this embodiment of this application can improve thermal stability of the phase-change memory material in the low resistance state and the high resistance state.

[0085] In some embodiments, a value range of an atom percent a of Ti may be 5%a40%, 10%a38%, 15%a30%, 20%a35%, or the like. Details are not listed one by one herein. When the value range of the atom percent a of Ti is 20%a35%, the phase-change memory material has better performance in the operation delay, the power consumption, the thermal stability, the fatigue life, and the like.

[0086] In an example, a may be specifically 5%. In an example, a may be specifically 8%. In an example, a may be specifically 10%. In an example, a may be specifically 13%. In an example, a may be specifically 15%. In an example, a may be specifically 18%. In an example, a may be specifically 20%. In an example, a may be specifically 25%. In an example, a may be specifically 28%. In an example, a may be specifically 30%. In an example, a may be specifically 32%. In an example, a may be specifically 35%. In an example, a may be specifically 37%. In an example, a may be specifically 40%. In an example, a may be specifically 45%.

[0087] In some embodiments, a ratio of an atom percent b of Sb to an atom percent c of Te, that is, (b:c), may be 0.5(b:c)1, 0.5(b:c)2, 1(b:c)3, 2(b:c)3, or the like. Details are not listed one by one herein.

[0088] In an example, (b:c) may be specifically 0.5, (2:3), 1, 2, 3, or the like. Details are not listed one by one herein. When (b:c) is (2:3), the phase-change memory material has better performance in the operation delay, the power consumption, thermal stability, the fatigue life, and the like.

[0089] In some embodiments, the value range of the atom percent a of Ti is 20%a35%, and the ratio of the atom percent b of Sb to the atom percent c of Te is (2:3). In this case, the phase-change memory material has a lower operation delay, lower power consumption, higher thermal stability, and a higher fatigue life.

[0090] In some embodiments, a doping element D may be specifically one or a combination of at least two of non-metallic elements such as C, O, N, and Si. In some embodiments, the doping element D may be specifically one or a combination of at least two of metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, the doping element D may be specifically one or a combination of at least two of tellurides of the metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn. In some embodiments, the doping element D may be specifically one or a combination of at least two of the non-metallic elements such as C, O, N, and Si, the metallic elements such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Ga, and Sn, and the tellurides of the metallic elements.

[0091] The doping element D is added into the phase-change memory material, so that a thermal stability and the fatigue life of the phase-change memory material can be improved, and a crystallization speed (to be specific, a speed of conversion from the high resistance state to the low resistance state) of the phase-change memory material can be further increased. Therefore, the operation delay is reduced.

[0092] In some embodiments, an atom percent d of the doping element D may be 0%d10%, 0%d8%, 3%d10%, or 3%d8%. When 3%d8%, the phase-change memory material has a lower operation delay and a higher fatigue life.

[0093] In an example, the atom percent d of the doping element D is 0, that is, the phase-change memory material does not include the doping element D. In an example, d is 1%. In an example, d is 3%. In an example, d is 5%. In an example, d is 8%. In an example, d is 10%. In an example, d is 15%.

[0094] The foregoing examples describe compositions of the phase-change memory material. The following uses examples to describe preparation solutions of the phase-change memory material.

[0095] In embodiments of this application, the phase-change memory material may be deposited on a base material according to an element ratio shown by Ti.sub.aSb.sub.bTe.sub.cD.sub.d in a material deposition manner such as chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), or atomic layer deposition (atomic layer deposition, ALD). The base material may be an electrode, may be an electrode, may be a buffer layer to be described below, may be a chalcogenide layer to be described below, or may be another specific base material. Details are not described herein.

[0096] In some embodiments, the phase-change memory material is prepared on the base material by using a Ti single elemental target material and an SbTe alloy target material. In a sputtering process, different deposition rates may be obtained by controlling power of different target materials, to obtain a phase-change memory material with a corresponding composition distribution ratio.

[0097] In some embodiments, the phase-change memory material may be specifically prepared on the base material by sputtering a single-target material in a sputtering manner (for example, a magnetron sputtering method) in the physical vapor deposition. Specifically, when a doping element D is not included, or a doping element D1 is not N and/or O, sputtering may be performed using a Ti single elemental target material, an Sb single elemental target material, a Te single elemental target material, and a doping element D (when a phase-change material includes the doping element D) single elemental target material, to prepare the phase-change memory material on the base material. When the doping element D1 is N, sputtering may be performed using a titanium nitride alloy target material, an Sb single elemental target material, and a Te single elemental target material, to prepare the phase-change memory material on the base material. When the doping element D1 is O, sputtering may be performed using a titanium oxide alloy target material, an Sb single elemental target material, and a Te single elemental target material, to prepare the phase-change memory material on the base material. In the sputtering process, different deposition rates may be obtained by controlling the power of the different target materials, to obtain the phase-change memory material with the corresponding composition distribution ratio.

[0098] In some embodiments, a Ti.sub.aSb.sub.bTe.sub.cD.sub.d alloy may be prepared (for example, smelted) first. Then, the sputtering is performed using the Ti.sub.aSb.sub.b Te Da alloy, to prepare the phase-change memory material on the base material.

[0099] The following describes a preparation process of the phase-change memory material in specific embodiments.

Embodiment 1

[0100] A phase-change memory material whose element composition is Ti.sub.8Sb.sub.36.8Te.sub.55.2 is prepared. Details are as follows.

[0101] A Ti single elemental target material and an SbTe alloy target material each having an atom percentage purity of not less than 99.99% are placed at different target material locations in a sputtering cavity. A ratio of atoms of Sb to atoms of Te in the SbTe alloy is 2:3. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti single elemental target material and the SbTe alloy target material to generate sputtering glow. Sputtering power applied to the Ti single elemental target material is 10 W, and sputtering power applied to the SbTe alloy target material is 7 W. An argon flow is 35 sccm in a sputtering process. In this way, the phase-change memory material whose element composition is Ti.sub.8Sb.sub.36.8Te.sub.55.2 can be prepared on the base material.

Embodiment 2

[0102] A phase-change memory material whose element composition is Ti.sub.22Sb.sub.31.2Te.sub.46.8 is prepared. Details are as follows.

[0103] A Ti single elemental target material and an SbTe alloy target material each having an atom percentage purity of not less than 99.99% are placed at different target material locations in a sputtering cavity. A ratio of atoms of Sb to atoms of Te in the SbTe alloy is 2:3. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti single elemental target material and the SbTe alloy target material to generate sputtering glow. Sputtering power applied to the Ti single elemental target material is 30 W, and sputtering power applied to the SbTe alloy target material is 7 W. An argon flow is 35 sccm in a sputtering process. In this way, the phase-change memory material whose element composition is Ti.sub.22Sb.sub.31.2Te.sub.46.8 can be prepared on the base material.

Embodiment 3

[0104] A phase-change memory material whose element composition is Ti.sub.28Sb.sub.28.8Te.sub.43.2 is prepared. Details are as follows.

[0105] A Ti single elemental target material and an SbTe alloy target material each having an atom percentage purity of not less than 99.99% are placed at different target material locations in a sputtering cavity. A ratio of atoms of Sb to atoms of Te in the SbTe alloy is 2:3. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti single elemental target material and the SbTe alloy target material to generate sputtering glow. Sputtering power applied to the Ti single elemental target material is 40 W, and sputtering power applied to the SbTe alloy target material is 7 W. An argon flow is 35 sccm in a sputtering process. In this way, the phase-change memory material whose element composition is Ti.sub.22Sb.sub.31.2Te.sub.46.8 can be prepared on the base material.

Embodiment 4

[0106] A phase-change memory material whose element composition is Ti.sub.3Sb.sub.38.8Te.sub.58.2 is prepared. For a specific preparation process, refer to the descriptions in Embodiment 1. Details are not described herein again.

Embodiment 5

[0107] A phase-change memory material whose element composition is Ti.sub.45Sb.sub.18.8Te.sub.36.2 is prepared. For a specific preparation process, refer to the descriptions in Embodiment 1. Details are not described herein again.

Embodiment 6

[0108] A phase-change memory material whose element composition is Ti.sub.40Sb.sub.23.8Te.sub.36.2 is prepared. For a specific preparation process, refer to the descriptions in Embodiment 1. Details are not described herein again.

Embodiment 7

[0109] A phase-change memory material whose element composition is Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 is prepared. An alloy whose element composition is Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 is smelted. The Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 alloy is placed at a target material location in a sputtering cavity. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 alloy to generate sputtering glow. Therefore, the Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 alloy is sputtered onto the base material, to prepare the Ti.sub.21Sb.sub.29.6Te.sub.44.4C.sub.5 phase-change memory material.

Embodiment 8

[0110] A phase-change memory material whose element composition is Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 is prepared. An alloy whose element composition is Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 is smelted. The Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 alloy is placed at a target material location in a sputtering cavity. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 alloy to generate sputtering glow. Therefore, the Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 alloy is sputtered onto the base material, to prepare the Ti.sub.25.7Sb.sub.27.7Te.sub.41.6C.sub.5 phase-change memory material.

Embodiment 9

[0111] A phase-change memory material whose element composition is Ti.sub.17Sb.sub.31.2Te.sub.46.8O.sub.5 is prepared. An alloy whose element composition is Ti.sub.17Sb.sub.31.2Te.sub.46.8O.sub.5 is smelted. The Ti.sub.17Sb.sub.31.2Te.sub.46.8O.sub.5 alloy is placed at a target material location in a sputtering cavity. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti.sub.17Sb.sub.31.2Te.sub.46.8O.sub.5 alloy to generate sputtering glow. Therefore, the Ti.sub.17Sb.sub.31.2Te.sub.46.8O.sub.5 alloy is sputtered onto the base material, to prepare the Ti.sub.17Sb.sub.31.2 Te.sub.46.8O.sub.5 phase-change memory material.

Embodiment 10

[0112] A phase-change memory material whose element composition is Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.8 is prepared. An alloy whose element composition is Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.5 is smelted. The Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.5 alloy is placed at a target material location in a sputtering cavity. A base material is placed on a sample table in the sputtering cavity. Sputtering power is applied to the Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.5 alloy to generate sputtering glow. Therefore, the Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.5 alloy is sputtered onto the base material, to prepare the Ti.sub.14Sb.sub.31.2Te.sub.46.8Si.sub.5 phase-change memory material.

[0113] The foregoing examples describe the preparation solutions of the phase-change memory material provided in embodiments of this application. The following describes data related to a fatigue life and thermal stability of a phase-change memory material provided in embodiments of this application.

[0114] The phase-change memory material prepared in Embodiment 1 and the phase-change memory material prepared in Embodiment 2 are separately observed using a transmission electron microscope, and results are respectively shown in FIG. 5A and FIG. 5B. It can be seen that, when an atom percentage of Ti in the phase-change memory material is 8%, some grain sizes are tens of nanometers. When the atom percentage of Ti in the phase-change memory material increases to 28%, the grain size can be reduced to less than 10 nm. It indicates that Ti can reduce the grain size in the phase-change memory material, so that grain size distribution is more uniform (which may be understood that a smaller grain size indicates a smaller grain size distribution range, and the grain size distribution is more uniform). Therefore, a short fatigue life of the phase-change memory material caused by uneven grain sizes can be reduced or avoided. That is, when the atom percentage of Ti in the phase-change memory material is high (for example, 28%), the fatigue life of the phase-change memory material is high.

[0115] Resistances of the phase-change material prepared in Embodiment 1 are measured at different temperatures. Results are shown by a curve 601a and a curve 601b in FIG. 6. The curve 601a is a temperature rise curve, and the curve 601b is a temperature fall curve.

[0116] Resistances of the phase-change material prepared in Embodiment 2 are measured at different temperatures. Results are shown by a curve 602a and a curve 602b in FIG. 6. The curve 602a is a temperature rise curve, and the curve 602b is a temperature fall curve.

[0117] Resistances of the phase-change material prepared in Embodiment 3 are measured at different temperatures. Results are shown by a curve 603a and a curve 603b in FIG. 6. The curve 603a is a temperature rise curve, and the curve 603b is a temperature fall curve.

[0118] The temperature fall curve indicates a change of the resistance in a temperature falling process. The temperature rise curve indicates a change of the resistance in a temperature rising process. As shown in FIG. 6, in the temperature rising process of the phase-change memory material prepared in embodiments of this application, resistance decreasing indicates that the phase-change memory material is crystallizing. In the temperature falling process of the phase-change memory material, the basically unchanged resistance of the phase-change memory material indicates that crystallization is completed.

[0119] In addition, it can be seen from FIG. 6 that, as Ti concentration increases, an initial resistance of the phase-change memory material decreases, and a crystallization temperature increases. An abscissa of a location at which the resistance decreases fastest is the crystallization temperature. Specifically, a crystallization temperature of the phase-change material prepared in Embodiment 1 is about 210 C., a crystallization temperature of the phase-change material prepared in Embodiment 2 is about 240 C., and a crystallization temperature of the phase-change material prepared in Embodiment 3 is about 260 C. In addition, the initial resistance is a resistance corresponding to a minimum temperature on each curve in FIG. 6.

[0120] It can be learned from FIG. 6 that, in embodiments of this application, Ti is added to the phase-change memory material, so that the crystallization temperature of the phase-change memory material is increased. That is, the thermal stability of the phase-change memory material is improved.

[0121] The foregoing describes element compositions, preparation methods, and performance of the phase-change memory material provided in embodiments of this application. The following describes a phase-change memory chip formed by the phase-change memory material provided in embodiments of this application.

[0122] The phase-change memory chip provided in this embodiment of this application may include a phase-change memory cell memory array and a peripheral circuit. For details, refer to the foregoing descriptions of the embodiment shown in FIG. 2. Details are not described herein again.

[0123] The phase-change memory cell array may include a plurality of phase-change memory cells. In some embodiments, a structure of the phase-change memory cell may be implemented with reference to the structure shown in FIG. 1A. In some embodiments, a structure of the phase-change memory cell may be implemented with reference to the structure shown in FIG. 1B. Refer to FIG. 1A or FIG. 1B again. The phase-change layer 113 in the phase-change memory cell 110 may be the phase-change memory material provided in embodiments of this application. A material of an electrode may be a metallic material, a non-metallic material, a metallic nitride, or the like. More specifically, the material of an electrode 1 may be one or a combination of at least two of tungsten (W), carbon (C), tantalum Ta, titanium nitride (TiN), tantalum nitride (TaN), and the like. The material of the electrode is not specifically limited in this embodiment of this application.

[0124] In Embodiment a, the phase-change memory cell 110 may further include a buffer layer 114. The buffer layer 114 is in contact with the phase-change layer 113, and is also located between an electrode 111 and an electrode 112. In an illustrative example, a material of the buffer layer 114 may be a non-metal such as carbon (C). In an illustrative example, a material of the buffer layer 114 may be a non-metal such as carbon (C). In an illustrative example, a material of the buffer layer 114 may be a metal such as W, Ta, or Ti. In an illustrative example, a material of the buffer layer 114 may be a metallic nitride such as TiN or TaN. In an illustrative example, a material of the buffer layer 114 may be a telluride of a metal such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn.

[0125] The buffer layer 114 in contact with the phase-change layer 113 is introduced into the phase-change memory cell 110, so that performance of the phase-change layer 113 can be further improved. Specifically, when the material of the buffer layer 114 is the non-metal such as carbon (C), the buffer layer 114 can improve a heat insulation effect of the phase-change layer 113, reduce operation power consumption of the phase-change memory cell, avoid element diffusion in the phase-change layer 113, and improve an adhesion effect between the phase-change layer and the electrode. When the material of the buffer layer 114 is the telluride of the metal such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, the buffer layer 114 may be used as a crystallization template of the phase-change memory material, so that a speed of conversion of the phase-change memory material from an amorphous state to a crystalline state can be accelerated. Therefore, an operation delay of the phase-change memory operation cell 110 can be reduced, heating efficiency of the phase-change memory cell 110 can be improved, and operation power consumption of the phase-change memory cell 110 can be reduced. When the material of the buffer layer 114 is the metal such as W or Ta, the buffer layer 114 can avoid element diffusion in the phase-change memory material, and can also improve an adhesion effect between the phase-change layer and the electrode. When the material of the buffer layer 114 is the metallic nitride, the buffer layer 114 can improve the adhesion effect between the phase-change layer and the electrode, improve heating efficiency of the phase-change memory material, reduce resistance drift, repair a void at an interface of the phase-change memory material, improve the adhesion effect between the phase-change layer and the electrode, and so on.

[0126] The foregoing describes the material and a function of the buffer layer 114. The following uses an example to describe a location relationship between the buffer layer 114 and the phase-change layer 113.

[0127] In an illustrative example of Embodiment a, with reference to FIG. 7A, the buffer layer 114 is in contact with the phase-change layer 113, and the buffer layer 114 is located between the phase-change layer 113 and the electrode 111.

[0128] In another illustrative example of Embodiment a, with reference to FIG. 7B, the buffer layer 114 is in contact with the phase-change layer 113, and the buffer layer 114 is located between the phase-change layer 113 and the electrode 112.

[0129] In another illustrative example of Embodiment a, with reference to FIG. 7C, the phase-change memory cell 110 includes two buffer layers 114, and each buffer layer 114 is in contact with the phase-change layer 113. One buffer layer 114 is located between the phase-change layer 113 and the electrode 111, and the other buffer layer 114 is located between the phase-change layer 113 and the electrode 112. Materials of the two buffer layers 114 may be the same or may be different. For example, the materials of the two buffer layers 114 are both the non-metal such as carbon (C), the metal such as W or Ta, the metallic nitride such as TiN or TaN, or the telluride of the metal such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn. For example, a material of one of the two buffer layers 114 is the non-metal such as carbon (C), and a material of the other buffer layer 114 is the non-metal such as carbon (C); a material of one buffer layer 114 is the metallic nitride such as TiN or TaN, and a material of the other buffer layer 114 is the telluride of the metal such as Zr, Cr, Al, Sc, Y, Ta, Hf, Er, In, Ge, Bi, Ti, Ga, or Sn, or the like. Details are not listed one by one herein. The materials of the two buffer layers 114 are different, so that the phase-change memory cell 110 can have advantages corresponding to the two materials.

[0130] In another illustrative example of Embodiment a, with reference to FIG. 7D, the phase-change layer 113 has a groove, and the buffer layer 114 is located in the groove of the phase-change layer 113 and is in contact with the phase-change layer 113. That is, the phase-change layer 113 surrounds the buffer layer 114.

[0131] In another illustrative example of Embodiment a, with reference to FIG. 7E, the buffer layer 114 has a groove, and the phase-change layer 113 is located in the groove of the buffer layer 114 and is in contact with the buffer layer 114. That is, the buffer layer 114 surrounds the phase-change layer 113.

[0132] The foregoing uses the structures shown in FIG. 7A to FIG. 7E as examples to describe the location relationship between the phase-change layer 113 and the buffer layer 114, but the examples are not exhaustive. In another embodiment, the phase-change layer 113 and the buffer layer 114 may alternatively have another location relationship. Details are not listed one by one herein.

[0133] In Embodiment b, the phase-change memory cell 110 may further include at least one chalcogenide layer 115 and at least one phase-change layer 113. The at least one phase-change layer 113 and the at least one chalcogenide layer 115 are stacked alternately, and are both located between the electrode 111 and the electrode 112.

[0134] In an illustrative example of Embodiment b, a material of the chalcogenide layer 115 may be a metal sulfide, for example, GeS.sub.x.

[0135] In another illustrative example of Embodiment b, a material of the chalcogenide layer 115 may be a metal Te compound, for example, TiTe.sub.2, Hf.sub.xTe.sub.y or Zr.sub.xTe.sub.y.

[0136] In another illustrative example of Embodiment b, a material of the chalcogenide layer 115 may alternatively be a phase-change memory material, for example, one or a combination of at least two of Sb.sub.xTe.sub.y, Ge.sub.xSb.sub.yTe.sub.z, Ge.sub.xTe.sub.y, Bi.sub.xTe.sub.y, and Inx Te.sub.y. In the foregoing chemical formulas, subscripts x, y, and z respectively represent proportions of corresponding atoms.

[0137] The phase-change layer 113 and the chalcogenide layer 115 are stacked alternately. It is not difficult to understand that there is an interface between one phase-change layer 113 and one adjacent chalcogenide layer 115. In this way, alternate stacking of the phase-change layer 113 and the chalcogenide layer 115 can introduce more interfaces for the phase-change memory material, and the interface can reduce thermal conduction. Therefore, the operation power consumption of the phase-change memory cell 110 is reduced, and a fatigue life of the phase-change memory cell 110 is improved. In addition, a chalcogenide has good thermal insulation performance. This can reduce the operation power consumption of the phase-change memory cell 110 and improve the fatigue life of the phase-change memory cell 110. In addition, when the material of the chalcogenide layer 115 is TiTe.sub.2 or the like, a lattice coefficient of the chalcogenide layer 115 is less than a lattice coefficient of the phase-change memory material provided in embodiments of this application, so that the element diffusion in the phase-change layer 113 can be avoided, and a fatigue life of the phase-change layer 113 is improved, in other words, the fatigue life of the phase-change memory cell 110 is improved.

[0138] In another illustrative example of Embodiment b, with reference to FIG. 8A, in a direction from the electrode 111 to the electrode 112, the at least one chalcogenide layer 115 and the at least one phase-change layer 113 are stacked alternately or arranged periodically, and n periodic repeated stacking may be formed starting from the phase-change layer 113 and ending at the chalcogenide layer 115. n is an integer greater than or equal to 1.

[0139] In another illustrative example of Embodiment b, with reference to FIG. 8B, in a direction from the electrode 111 to the electrode 112, the at least one chalcogenide layer 115 and the at least one phase-change layer 113 are stacked alternately or arranged periodically, and n periodic repeated stacking may be formed starting from the chalcogenide layer 115 and ending at the phase-change layer 113. n is an integer greater than or equal to 1. n is an integer greater than or equal to 1.

[0140] In another illustrative example of Embodiment b, with reference to FIG. 8C, in a direction from the electrode 111 to the electrode 112, the at least one chalcogenide layer 115 and the at least one phase-change layer 113 are stacked alternately or arranged periodically. This may start from the phase-change layer 113 and end at the phase-change layer 113. Between a phase-change layer 113 at a start location and a phase-change layer 113 at an end location, there are n periodically and repeatedly stacked chalcogenide layers 115 and phase-change layers 113. In addition, in the phase-change memory cell 110, at least one chalcogenide layer 115 is between the two phase-change layers 113, and at least one phase-change layer is between two chalcogenide layers 115. n is an integer greater than or equal to 1. n is an integer greater than or equal to 1.

[0141] In another illustrative example of Embodiment b, with reference to FIG. 8D, in a direction from the electrode 111 to the electrode 112, the at least one chalcogenide layer 115 and the at least one phase-change layer 113 are stacked alternately or arranged periodically. This may start from the chalcogenide layer 115 and end at the chalcogenide layer 115. Between a chalcogenide layer 115 at a start location and a chalcogenide layer 115 at an end location, there are n periodically and repeatedly stacked phase-change layers 113 and chalcogenide layers 115. In addition, in the phase-change memory cell 11, at least one chalcogenide layer 115 is between two phase-change layers 113, and at least one phase-change layer is between the two chalcogenide layers 115. n is an integer greater than or equal to 1. n is an integer greater than or equal to 1.

[0142] The foregoing uses the structures shown in FIG. 8A to FIG. 8D as examples to describe a location relationship between the phase-change layer 113 and the chalcogenide 115, but the examples are not exhaustive. In another embodiment, the phase-change layer 113 and the chalcogenide layer 115 may alternatively have another location relationship. Details are not listed one by one herein.

[0143] Refer to FIG. 9. An embodiment of this application provides a storage device 900, including a phase-change memory chip 910 and a controller 920. The phase-change memory chip 910 may be configured to store data, and the controller 920 may be configured to write data into the phase-change memory chip 910 or read data from the phase-change memory chip 910. The phase-change memory chip 910 may include a plurality of phase-change memory cells 110, and the plurality of phase-change memory cells 110 form a memory cell array in the storage device 900.

[0144] In some embodiments, the phase-change memory chip 910 may be implemented with reference to the foregoing descriptions of the embodiment shown in FIG. 2. The controller 920 may be a device having a data processing capability, and is configured to control a peripheral circuit of the phase-change memory chip 910, to write data into the phase-change memory chip 910 or read data from the phase-change memory chip 910.

[0145] Refer to FIG. 10. An embodiment of this application provides an electronic device 1000. The electronic device 1000 may include a processor 1010 and a storage device 900. The storage device 900 may be configured to store data, for example, may store an application and a configuration file of the electronic device 1000. The storage device 900 may provide data storage space for the processor 1010, so that the processor 1010 can write data into the data storage space. Data stored in the storage device 900 may be read or invoked by the processor 1010. The processor 1010 is configured to write data into the storage device 900 or read data from the storage device 900. Specifically, the processor 1010 may write data into a phase-change memory chip 910 or read data from a phase-change memory chip 910 through a controller 920. For example, the processor 1010 may invoke data in the storage device 900, to implement a corresponding function of the electronic device 1000.

[0146] In some embodiments, the storage device 900 may be used as a memory (memory) of the electronic device 1000. In some embodiments, the storage device 900 may be used as an external memory of the electronic device 1000. In some embodiments, the processor 1010 may be a neural-network processing unit (neural-network processing unit, NPU). In some embodiments, the storage device 900 may alternatively be another form of apparatus that has a data storage capability and that is in the electronic device 1000. An implementation of the storage device 900 is not specifically limited in this application.

[0147] In some embodiments, the processor 1010 may be a central processing unit (central processing unit, CPU). In some embodiments, the processor 1010 may be a graphics processing unit (graphics processing unit, GPU). In some embodiments, the processor 1010 may be an application-specific integrated circuit (application-specific integrated circuit, ASIC). In some embodiments, the processor 1010 may be a neural-network processing unit (neural-network processing unit, NPU). In some embodiments, the processor 1010 may alternatively be another form of apparatus that has a data processing capability and that is in the electronic device 100. An implementation of the processor 1010 is not specifically limited in this application.

[0148] In some embodiments, the electronic device 1000 may be a server, a mobile terminal (for example, a mobile phone, a tablet computer, or a notebook computer), a vehicle-mounted terminal, or the like. An implementation of an electronic device in which the processor 1010 and the storage device 900 are located is not specifically limited in this embodiment of this application.

[0149] It may be understood that the foregoing embodiments are merely intended for describing the technical solutions of this application, but not for limiting this application. Although this application is described in detail with reference to the foregoing embodiments, a person of ordinary skill in the art should understand that modifications to the technical solutions recorded in the foregoing embodiments or equivalent replacements to some technical features thereof may still be made; and these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions in embodiments of this application.

[0150] The foregoing descriptions are merely specific implementations of this application, but are not intended to limit the scope of the protection of this application. Any variation or replacement readily figured out by a person skilled in the art within the technical scope disclosed in the present invention shall fall within the scope of the protection of this application. Therefore, the scope of the protection of this application shall be subject to the scope of the protection of the claims.