SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF

Abstract

A semiconductor memory device includes a substrate having a conductor region thereon, an interlayer dielectric layer on the substrate, and a conductive via electrically connected to the conductor region. The conductive via has a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer. The upper portion has a rounded top surface. A storage structure conformally covers the rounded top surface.

Claims

1. A semiconductor memory device, comprising: a substrate comprising a conductor region thereon; an interlayer dielectric layer on the substrate; a conductive via electrically connected to the conductor region, wherein the conductive via comprises a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has a rounded top surface; and a storage structure conformally covering the rounded top surface.

2. The semiconductor memory device according to claim 1, wherein a thickness of the lower portion is greater than that of the upper portion.

3. The semiconductor memory device according to claim 1, wherein the interlayer dielectric layer is a tetraethoxysilane (TEOS)-based silicon oxide layer.

4. The semiconductor memory device according to claim 1 further comprising: an etch stop layer between the interlayer dielectric layer and the substrate.

5. The semiconductor memory device according to claim 1, wherein the storage structure comprises a magnetic tunnel junction stack.

6. The semiconductor memory device according to claim 1, wherein the conductive via comprises a tungsten layer.

7. The semiconductor memory device according to claim 6, wherein the conductive via comprises a barrier layer between the tungsten layer and the interlayer dielectric layer.

8. A semiconductor memory device, comprising: a substrate comprising a conductor region thereon; an interlayer dielectric layer on the substrate; a conductive via electrically connected to the conductor region, wherein the conductive via comprises a lower portion embedded in the interlayer dielectric layer and an upper portion protruding from a top surface of the interlayer dielectric layer, wherein the upper portion has a flat top surface and a round edge surface extending between the flat top surface and a sidewall surface of the upper portion; and a storage structure conformally covering the rounded top surface.

9. The semiconductor memory device according to claim 8, wherein a thickness of the lower portion is greater than that of the upper portion.

10. The semiconductor memory device according to claim 8, wherein the interlayer dielectric layer is a tetraethoxysilane (TEOS)-based silicon oxide layer.

11. The semiconductor memory device according to claim 8 further comprising: an etch stop layer between the interlayer dielectric layer and the substrate.

12. The semiconductor memory device according to claim 8, wherein the storage structure comprises a magnetic tunnel junction stack.

13. The semiconductor memory device according to claim 8, wherein the conductive via comprises a tungsten layer.

14. The semiconductor memory device according to claim 13, wherein the conductive via comprises a barrier layer between the tungsten layer and the interlayer dielectric layer.

15. A method of forming a semiconductor memory device, comprising: providing a substrate comprising a conductor region thereon; forming an interlayer dielectric layer on the substrate; forming a conductive via in the interlayer dielectric layer, wherein the conductive via is electrically connected to the conductor region; subjecting the interlayer dielectric layer to a first etching process, thereby forming an upper portion of the conductive via protruding from a top surface of the interlayer dielectric layer and a lower portion of the conductive via embedded in the interlayer dielectric layer; subjecting the upper portion of the conductive via to a second etching process to trim the upper portion; and forming a storage structure conformally covering the upper portion of the conductive via.

16. The method according to claim 15, wherein a thickness of the lower portion is greater than that of the upper portion.

17. The method according to claim 15, wherein the interlayer dielectric layer is a tetraethoxysilane (TEOS)-based silicon oxide layer.

18. The method according to claim 15 further comprising: forming an etch stop layer between the interlayer dielectric layer and the substrate.

19. The method according to claim 15, wherein the upper portion has a rounded top surface, after subjecting the upper portion of the conductive via to the second etching process.

20. The method according to claim 15, wherein the upper portion has a flat top surface and a rounded edge surface extending between the flat top surface and a sidewall surface of the upper portion, after subjecting the upper portion of the conductive via to the second etching process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 to FIG. 5 are schematic diagrams illustrating a method of forming a semiconductor memory device according to an embodiment of the present invention.

[0028] FIG. 6 to FIG. 10 are schematic diagrams illustrating a method of forming a semiconductor memory device according to another embodiment of the present invention.

DETAILED DESCRIPTION

[0029] In the following detailed description of the disclosure, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention.

[0030] Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description is not to be considered as limiting, but the embodiments included herein are defined by the scope of the accompanying claims.

[0031] FIG. 1 to FIG. 5 are schematic diagrams illustrating a method of forming a semiconductor memory device 1 according to an embodiment of the present invention. As shown in FIG. 1, first, a substrate 100, such as a silicon substrate, is provided, on which a conductor region 110 is provided. For example, the conductor region 110 may be a copper metal layer disposed in a dielectric layer 120, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer 120 may be a low dielectric constant material layer, for example, the dielectric constant may be less than 2.5, but is not limited thereto. An inter-layer dielectric layer 140 is formed on the substrate 100. According to an embodiment of the present invention, the interlayer dielectric layer 140 may be a tetraethylorthosilicate (TEOS)-based silicon oxide layer.

[0032] According to the embodiment of the present invention, an etch stop layer 130 may be formed between the interlayer dielectric layer 140 and the substrate 100, for example, a nitrogen-doped silicon carbide layer, but it is not limited thereto.

[0033] According to the embodiment of the present invention, then, a conductive via 20 is formed in the interlayer dielectric layer 140. According to the embodiment of the present invention, the conductive via 20 is electrically connected to the conductor region 110. At this point, the top surface S1 of the conductive via 20 and the top surface S2 of the interlayer dielectric layer 140 are coplanar. According to the embodiment of the present invention, the conductive via 20 may include a tungsten metal layer 201. In addition, the conductive via 20 may have a barrier layer 202 between the tungsten metal layer 201 and the interlayer dielectric layer 140, such as titanium nitride, but is not limited thereto.

[0034] The method of forming the conductive via 20 may include a lithography process, an etching process, a chemical vapor deposition (CVD) process, a chemical mechanical polishing (CMP) process, and the like.

[0035] As shown in FIG. 2, a first etching process, such as a dry etching process, is then performed on the interlayer dielectric layer 140 to remove a part of the interlayer dielectric layer 140, so that an upper portion 20U of the conductive via 20 protrudes from the top surface S3 of the interlayer dielectric layer 140 and the lower portion 20L of the conductive via 20 is still embedded in the interlayer dielectric layer 140.

[0036] As shown in FIG. 3, next, a second etching process, such as a dry etching process, is performed on the upper portion 20U of the conductive via 20 to trim the upper portion 20U. According to the embodiment of the present invention, after the second etching process is performed on the upper portion 20U of the conductive via 20, the upper portion 20U has a rounded top surface S4. According to an embodiment of the present invention, the thickness of the lower portion 20L of the conductive via 20 may be greater than the thickness of the upper portion 20U.

[0037] As shown in FIG. 4, next, a lower electrode layer 301, a magnetic tunnel junction stack 302, and an upper electrode layer 303 are sequentially deposited on the top surface S3 of the interlayer dielectric layer 140 and the upper portion 20U of the conductive via 20. The lower electrode layer 301, the magnetic tunnel junction stack 302 and the upper electrode layer 303 constitute a stack structure 300. According to an embodiment of the present invention, the lower electrode layer 301 may be, for example, tantalum nitride, and the upper electrode layer 303 may be, for example, titanium nitride, but is not limited thereto. According to the embodiment of the present invention, the magnetic tunnel junction stack 302 may include a reference layer, a channel layer, and a free layer, but is not limited thereto. The reference layer and the free layer may include a magnetic material, and the channel layer may include an insulating material, but it is not limited thereto.

[0038] As shown in FIG. 5, next, a photolithography process is performed to form a photoresist pattern PR on the conductive via 20. An etching process, for example, an anisotropic dry etching process, is then performed to etch the stacked structure 300 not covered by the photoresist pattern PR, thereby forming the storage structure 30 that covers the upper portion 20U of the conductive via 20 in a conformal manner. The subsequent steps may include deposition of a low dielectric constant material layer and a subsequent metallization process, which is a well-known technique and will not be described in detail.

[0039] FIG. 6 to FIG. 10 are schematic diagrams illustrating a method of forming a semiconductor memory device 2 according to another embodiment of the present invention. As shown in FIG. 6, likewise, a substrate 100 is provided, for example, a silicon substrate, on which a conductor region 110 is formed. For example, the conductor region 110 may be a copper metal layer disposed in a dielectric layer 120, but is not limited thereto. According to an embodiment of the present invention, the dielectric layer 120 may be a low dielectric constant material layer, for example, the dielectric constant may be less than 2.5, but is not limited thereto. An inter-dielectric layer 140 is formed on the substrate 100. According to an embodiment of the present invention, the interlayer dielectric layer 140 may be a TEOS-based silicon oxide layer.

[0040] According to the embodiment of the present invention, an etch stop layer 130 may be formed between the interlayer dielectric layer 140 and the substrate 100, for example, a nitrogen-doped silicon carbide layer, but it is not limited thereto.

[0041] According to the embodiment of the present invention, then, a conductive via 20 is formed in the interlayer dielectric layer 140. According to the embodiment of the present invention, the conductive via 20 is electrically connected to the conductor region 110. At this point, the top surface S1 of the conductive via 20 and the top surface S2 of the interlayer dielectric layer 140 are coplanar. According to the embodiment of the present invention, the conductive via 20 may include a tungsten metal layer 201. In addition, the conductive via 20 may have a barrier layer 202 between the tungsten metal layer 201 and the interlayer dielectric layer 140, such as titanium nitride, but is not limited thereto.

[0042] As shown in FIG. 7, then, a first etching process is performed on the interlayer dielectric layer 140, such as a dry etching process, to remove a part of the interlayer dielectric layer 140, so that an upper portion 20U of the conductive via 20 protrudes from the top surface S3 of the interlayer dielectric layer 140 and the lower portion 20L of the conductive via 20 is still embedded in the interlayer dielectric layer 140.

[0043] As shown in FIG. 8, next, a second etching process, such as a dry etching process, is performed on the upper portion 20U of the conductive via 20 to trim the upper portion 20U. According to the embodiment of the present invention, after the second etching process is performed on the upper portion 20U of the conductive via 20, the upper portion 20U has a flat top surface S5 and a round edge surface S6 between a sidewall surface S7 and the flat top surface S5. According to an embodiment of the present invention, the thickness of the lower portion 20L of the conductive via 20 may be greater than the thickness of the upper portion 20U.

[0044] As shown in FIG. 9, next, a lower electrode layer 301, a magnetic tunnel junction stack 302, and an upper electrode layer 303 are sequentially deposited on the top surface S3 of the interlayer dielectric layer 140 and the upper portion 20U of the conductive via 20. The lower electrode layer 301, the magnetic tunnel junction stack 302 and the upper electrode layer 303 constitute a stack structure 300. According to an embodiment of the present invention, the lower electrode layer 301 may be, for example, tantalum nitride, and the upper electrode layer 303 may be, for example, titanium nitride, but is not limited thereto. According to the embodiment of the present invention, the magnetic tunnel junction stack 302 may include a reference layer, a channel layer, and a free layer, but is not limited thereto. The reference layer and the free layer may include a magnetic material, and the channel layer may include an insulating material, but it is not limited thereto.

[0045] As shown in FIG. 10, next, a lithography process is performed to form a photoresist pattern PR on the conductive via 20, and then an etching process, for example, an anisotropic dry etching process, is performed to etch the stacked structure 300 not covered by the photoresist pattern PR., thereby forming the storage structure 30 that covers the upper portion 20U of the conductive via 20 in a conformal manner. The subsequent steps may include deposition of a low dielectric constant material layer and a subsequent metallization process, which is a well-known technique and will not be described in detail.

[0046] The present invention trims the upper portion 20U of the conductive via 20 through the second etching, so that the upper portion 20U has a rounded top surface S4 (FIG. 3) or a flat top surface S5 and a round edge surface S6 between the flat top surface S5 and the sidewall surfaces S7 of the upper portion 20U (FIG. 8), and the subsequently formed storage structure 30 conformally covers the upper portion 20U of the conductive via 20. By providing such configuration, an overlap area between the magnetic tunnel junction stack 302 and the conductive via 20 can be increased, thereby increasing the tunneling magnetoresistance (TMR).

[0047] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.