ETCH STOP LAYER FOR INJECTING CARRIERS INTO DRIFT LAYER FOR A VERTICAL POWER DEVICE

Abstract

A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n− type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

Claims

1. A method for forming a vertical power device comprising: providing a silicon substrate wafer having a top surface and a bottom surface; forming a p− type etch stop layer over or in the top surface of the wafer, the etch stop layer having an etch rate lower than the etch rate of the wafer underlying the etch stop layer, the etch stop layer being conductive; epitaxially growing a drift layer overlying the etch stop layer; forming one or more doped regions in or over the drift layer; etching the wafer to remove the wafer while retaining the etch stop layer such that the etch stop layer has an exposed surface, the etch stop layer automatically reducing the etch rate; and forming a metal electrode on the exposed surface of the etch stop layer, whereby, when the device is turned on and conducting a vertical current, the current flows through the metal electrode and the etch stop layer.

2. The method of claim 1 wherein the wafer is one of n-type, undoped, or a p-type having a p− type dopant concentration less than 1×10E18 cm.sup.−3.

3. The method of claim 1 wherein forming the etch stop layer comprises epitaxially growing a layer having a p− type dopant concentration greater than 1×10E19 cm.sup.−3.

4. The method of claim 1 wherein forming the etch stop layer comprises implanting boron ions into the top surface of the wafer.

5. The method of claim 1 wherein forming the etch stop layer comprises forming a layer of p-type SiGe over the top surface of the wafer.

6. The method of claim 1 wherein etching the wafer comprises performing a chemical etch of the wafer.

7. The method of claim 6 wherein the chemical etch comprises applying a KOH solution or a TMAH solution to an exposed surface of the wafer until the etch stop layer is exposed.

8. The method of claim 1 wherein etching the wafer comprises performing a plasma etch of the wafer until the etch stop layer is exposed.

9. The method of claim 1 further comprising grinding down the wafer to a certain thickness, followed by the step of etching.

10. The method of claim 1 further comprising epitaxially growing an n− type buffer layer over the etch stop layer, followed by the step of epitaxially growing the drift layer over the n− type buffer layer, wherein the drift layer is n− type.

11. The method of claim 1 wherein the drift layer is n− type, and the step of forming one or more doped regions in or over the drift layer comprises: forming a p− type well region in the drift layer; and forming one or more n− type regions in the p− type well region.

12. The method of claim 1 wherein the metal electrode is a bottom metal electrode, the method further comprising forming a top metal electrode overlying the one or more doped regions in or over the drift layer, such that current is conducted between the top metal electrode and the bottom metal electrode through the etch stop layer when the device is turned on.

13. The method of claim 1 further comprising forming trenches containing a conductor to form gates, such that biasing the gates turns the device on to conduct a current through the etch stop layer.

14. A vertical power device comprising: a p− type etch stop layer, which was formed over or in a top surface of a silicon wafer that has been removed, the etch stop layer having an etch rate lower than the etch rate of the wafer, the etch stop layer being conductive; an epitaxially grown drift layer overlying the etch stop layer; one or more doped regions in or over the drift layer; and a metal electrode on the exposed surface of the etch stop layer, whereby, when the device is turned on and conducting a vertical current, the current flows through the metal electrode and the etch stop layer.

15. The device of claim 14 wherein the wafer is one of n− type, undoped, or a p− type having a p− type dopant concentration less than 1×10E18 cm.sup.−3.

16. The device of claim 14 wherein the etch stop layer was epitaxially grown over the wafer and has a p-type dopant concentration greater than 1×10E19 cm.sup.−3.

17. The device of claim 14 wherein the etch stop layer was formed by implanting boron ions into the top surface of the wafer.

18. The device of claim 14 wherein the etch stop layer comprises a layer of p− type SiGe.

19. The device of claim 14 wherein the drift layer is n− type, and the one or more doped regions in or over the drift layer comprises: a p− type well region in the drift layer; and one or more n− type regions in the p− type well region.

20. The device of claim 14 further comprising trenches containing a conductor to form gates, such that biasing the gates turns the device on to conduct a current through the etch stop layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is a cross-sectional view of a portion of a prior art IGTO device of the Applicant's own design.

[0027] FIG. 2 is a cross-sectional view of a starting silicon substrate wafer, in accordance with one embodiment of the invention.

[0028] FIG. 3 is a graph of net dopant density vs. depth into the wafer of FIG. 2.

[0029] FIG. 4 illustrates the wafer having formed on its top surface a boron-doped layer by epitaxial growth, forming a p+ layer, which also serves as an etch stop layer.

[0030] FIG. 5 is a graph showing the net dopant density vs. depth into the structure of FIG. 4.

[0031] FIG. 6 illustrates another embodiment of the invention where the wafer of FIG. 2 has boron ions implanted in its top surface and ultimately driven in to form a top p+ layer, which also serves as an etch stop layer.

[0032] FIG. 7 is a graph showing the net dopant density vs. depth into the wafer of FIG. 6.

[0033] FIG. 8 illustrates a modification of the device of FIG. 1 where the wafer of FIG. 4 or FIG. 6 is used as the growth substrate for forming the overlying layers and regions.

[0034] FIG. 9 illustrates the device of FIG. 8 after the wafer portion below the etch stop layer has been removed by grinding and chemical or plasma etching, using the etch stop layer to automatically stop the etching process, followed by forming a bottom metal electrode over the p+ etch stop layer.

[0035] FIG. 10 is a flowchart of steps used in one embodiment of the invention.

[0036] Elements that are the same or equivalent are labeled with the same numbers.

DETAILED DESCRIPTION

[0037] FIG. 2 is a cross-sectional view of a starting silicon substrate wafer 40, in accordance with one embodiment of the invention. The wafer 40 may be n− type, p− type, or undoped, since it will eventually be completely removed. Such wafers may be on the order of a few hundred microns, and up to 1000 microns, in thickness. The wafer 40 is for epitaxial growth and mechanical support during the fabrication process for forming a vertical power device. After the wafer is removed, a bottom, low resistivity p+ type semiconductor layer injects carriers into an overlying n-type drift layer when the device is turned on. The invention results in the bottom semiconductor layer being very thin and very low resistivity for a lower voltage drop when conducting large currents.

[0038] FIG. 3 is a graph of net dopant density vs. depth into the wafer 40, showing that the dopant density is uniform throughout the wafer 40. An undoped wafer 40 may also be used. If the wafer 40 is p− type, it should have a dopant concentration less than 1×10E18 cm.sup.−3.

[0039] FIG. 4 illustrates the wafer 40 after it has formed on its top surface a boron-doped layer by epitaxial growth, forming a very low resistance p+ layer, which also serves as an etch stop layer 42. The dopant concentration of the etch stop layer 42 should be at least 1×10E19 cm.sup.−3. Boron gas is injected into a reactor while growing the silicon epitaxial layer. Alternatively, the etch stop layer 42 may be a boron-dope silicon germanium (SiGe) epitaxial layer. The etch stop layer 42 may be a few microns thick. Its thickness is not critical, but a thinner etch stop layer 42 will reduce the voltage drop when conducting high currents. The thickness of the etch stop layer 42 is very repeatable since epitaxial growth thickness is very controllable.

[0040] It is known that certain chemical etchants, such as KOH (potassium hydroxide) and TMAH (tetramethyl ammonium hydroxide), experience a large reduction in silicon etching rate when the p− type dopant density (if any) of silicon goes from less than 1×10E18 cm.sup.−3 to above 1×10E19 cm.sup.−3. The etch rate of silicon can be reduced 20-200 times at the etch stop layer 42. Accordingly, the dopant density in the wafer 40 must be n− type, undoped, or have a low p− type dopant density (less than 1×10E18 cm.sup.−3). The wafer may have at least its bottom exposed surface subjected to the KOH or TMAH solution, such as in a bath.

[0041] If the etch stop layer 42 is p+ type SiGe, the SiGe inherently etches slower than silicon, so the dopant concentration is not as important for the reduction in etch rate. A high p− type dopant concentration is still important for low resistivity and should be above 1×10E19 cm.sup.−3.

[0042] FIG. 5 is a graph showing the net dopant density vs. depth into the structure of FIG. 4, where the dopant density of the boron in the etch stop layer 42 at the top is greater than 1×10E19 cm.sup.−3 and the p− type dopant density in the wafer 40 is less than 1×10E18 cm .sup.−3 (or the wafer 40 is n− type or undoped).

[0043] FIG. 6 illustrates another embodiment of the invention where the wafer 40 of FIG. 2 has boron ions implanted in its top surface and ultimately driven in to form a top p+ layer, which also serves as an etch stop layer 44. After the dopants are driven in, the etch stop layer 44 has the same properties as the etch stop layer 42 in FIG. 4.

[0044] FIG. 7 is a graph showing the net dopant density vs. depth into the wafer 40 of FIG. 6. Since the thickness of the etch stop layer 44 depends on the depth of ion implantation and the drive-in step, the etch stop layer 44 may be thicker or thinner than the etch stop layer 42 formed using epitaxial growth. The thickness, however, is highly repeatable, resulting in the device parameters being the same from lot-to-lot.

[0045] FIG. 8 illustrates a modification of the device of FIG. 1 where the wafer 40 of FIG. 4 or FIG. 6, with the etch stop layer 42 or 44 on top, is used as the growth substrate for forming the overlying epitaxial layer and regions. The etch stop layer 42/44 has no effect on the remaining processes used to form the device structure. The n− drift layer 32 and n− buffer layer 35 are epitaxially grown over the etch stop layer 42/44. The device can be a vertical switch device, such as an IGTO, an IGBT, a thyristor, or other device, which may be gated or non-gated.

[0046] FIG. 9 illustrates the device of FIG. 8 after the wafer portion below the etch stop layer 42/44 has been removed by grinding, followed by chemical or plasma etching, using the etch stop layer 42/44 to automatically stop the etching process. Those skilled in the art know various chemical or plasma etching techniques where the etch rate is greatly reduced with highly p− doped silicon or an SiGe layer.

[0047] A metal electrode 48 is then formed over the etch stop layer 42/44 to complete the vertical power device.

[0048] FIG. 10 illustrates various steps used in the process to form a vertical power device with a thin, low resistivity p+ layer as its bottom semiconductor layer.

[0049] In step 50, a starting wafer is provided. If it is p-doped, the dopant density should be less than 1×10E18 cm.sup.−3.

[0050] In step 52, a low resistivity p+ etch stop layer 42/44 is formed on or in the top surface of the wafer.

[0051] In step 54, a thick epitaxial layer is formed over the etch stop layer 42/44 to form an n− type drift region for supporting high voltages in the off state of the vertical power device. The drift region may be greater than 10 microns thick.

[0052] In step 56, the other device layers and regions are formed, such as to form the IGTO device of FIG. 8.

[0053] In step 58, the wafer is ground down to a thickness where the tolerance ensures that the grinding has not reached the etch stop layer 42/44. Minimum post-grinding thicknesses are typically on the order of 0.05 mm (50 microns). So, the wafer will be at least 50 microns thick at this stage.

[0054] In step 60, a chemical or plasma etch is used to remove the remainder of the wafer up to the etch stop layer 42/44, which automatically limits the etching process.

[0055] In step 62, a bottom metal electrode is formed over the thin p+ etch stop layer 42/44 to complete the vertical power device. A top metal electrode may also be formed at this time or previously. The etch stop layer 42/44 will typically have a p− type dopant concentration greater than 1×10E19 cm.sup.−3 and will efficiently inject holes into the drift layer when the device is turned on. The voltage drop across the etch stop layer 42/44 is low due to its small thickness and its low resistivity. The thickness is highly repeatable from lot-to-lot. In one embodiment, the etch stop layer 42/44 is less than 20 microns, and preferably less than 5 microns. This is much thinner than a minimum, ground down p+ wafer thickness of, for example, 50 microns.

[0056] While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.