MIM CAPACITOR AND FABRICATING METHOD OF THE SAME

Abstract

A metal-insulator-metal capacitor includes a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top. The superlattice layer contacts the dielectric layer. A silicon dioxide layer has a negative voltage coefficient of capacitance.

Claims

1. A metal-insulator-metal (MIM) capacitor, comprising: a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance.

2. The MIM capacitor of claim 1, wherein the silicon dioxide layer is annealed and polarized silicon dioxide.

3. The MIM capacitor of claim 1, wherein the silicon dioxide layer is amorphous silicon dioxide.

4. The MIM capacitor of claim 1, wherein the superlattice layer comprises perovskite material layers not less than 5 layers.

5. The MIM capacitor of claim 1, wherein the superlattice layer comprises perovskite material layers not less than 5 layers, and a thickness of each of the perovskite material layers is between 10 nm and 60 nm.

6. The MIM capacitor of claim 1, wherein the superlattice layer comprises SrTiO.sub.x, BaTiO.sub.x, CaTiO.sub.x, CaMgO.sub.x or PbTiO.sub.x.

7. The MIM capacitor of claim 1, wherein the superlattice layer has a positive voltage coefficient of capacitance.

8. The MIM capacitor of claim 1, wherein the dielectric layer comprises AlN.sub.x or BN.sub.x.

9. The MIM capacitor of claim 1, wherein the top electrode comprises TIN, Al, Ta, Cu, Ti or Ta, and the bottom electrode comprises TIN, Al, Ta, Cu, Ti or Ta.

10. The MIM capacitor of claim 1, wherein the top electrode contacts the silicon dioxide layer, and the bottom electrode contacts the dielectric layer.

11. A fabricating method of a metal-insulator-metal (MIM) capacitor, comprising: forming a bottom electrode, a dielectric layer, a superlattice layer, a silicon dioxide layer and a top electrode stacked from bottom to top; wherein the superlattice layer contacts the dielectric layer and the silicon dioxide layer, and the silicon dioxide layer has a negative voltage coefficient of capacitance.

12. The fabricating method of an MIM capacitor of claim 11, wherein steps of fabricating the superlattice layer comprises using a deposition process, periodically and alternately stacking a perovskite material layer at an operation temperature between 350 degrees Celsius to 450 degrees Celsius.

13. The fabricating method of an MIM capacitor of claim 12, wherein the deposition process comprises an atomic layer deposition, a chemical vapor deposition or a physical vapor deposition.

14. The fabricating method of an MIM capacitor of claim 11, wherein steps of fabricating the silicon dioxide layer comprises: depositing the silicon dioxide layer; and performing an annealing process to the silicon dioxide layer at a temperature of 400 degrees Celsius.

15. The fabricating method of an MIM capacitor of claim 11, wherein the silicon dioxide layer is amorphous and polarized silicon dioxide.

16. The fabricating method of an MIM capacitor of claim 11, wherein the superlattice layer comprises perovskite material layers not less than 5 layers.

17. The fabricating method of an MIM capacitor of claim 11, wherein the superlattice layer comprises perovskite material layers not less than 5 layers, and a thickness of each of the perovskite material layers is between 10 nm and 60 nm.

18. The fabricating method of an MIM capacitor of claim 11, wherein the superlattice layer comprises SrTiO.sub.x, BaTiO.sub.x, CaTiO.sub.x, CaMgO.sub.x or PbTiO.sub.x.

19. The fabricating method of an MIM capacitor of claim 11, wherein the superlattice layer has a positive voltage coefficient of capacitance.

20. The fabricating method of an MIM capacitor of claim 11, wherein the dielectric layer comprises AlN.sub.x or BN.sub.x.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 depicts a substrate with an interlayer dielectric layer thereon;

[0008] FIG. 2 is a fabricating stage in continuous of FIG. 1;

[0009] FIG. 3 is a fabricating stage in continuous of FIG. 2;

[0010] FIG. 4 is a fabricating stage in continuous of FIG. 3;

[0011] FIG. 5 is a fabricating stage in continuous of FIG. 4;

[0012] FIG. 6 is a fabricating stage in continuous of FIG. 5; and

[0013] FIG. 7 is a fabricating stage in continuous of FIG. 6.

DETAILED DESCRIPTION

[0014] FIG. 1 to FIG. 7 depict a fabricating method of an MIM capacitor according to a preferred embodiment of the present invention.

[0015] As shown in FIG. 1, a substrate 10 is provided. At least one transistor (not shown) can be optionally formed on the substrate 10. Next, an interlayer dielectric layer 12 is formed to cover the substrate 10. Metal interconnections (not shown) can be optionally formed in the interlayer dielectric layer 12 to connect the aforementioned transistor.

[0016] As shown in FIG. 2, a bottom electrode 14 is formed to cover and contact the interlayer dielectric layer 12. The bottom electrode 14 can be formed by atomic layer deposition, a chemical vapor deposition, a physical vapor deposition or other deposition processes. Because the bottom electrode 14 is composed of columnar grain structures, the bottom electrode 14 has a concave-convex top surface. The bottom electrode 14 includes TIN, Al, Ta, Cu, Ti or Ta.

[0017] As shown in FIG. 3, a dielectric layer 16 is formed to cover and contact the bottom electrode 14. The dielectric layer 16 is preferably a nitrogen-containing material with a high energy band gap. For example, the dielectric layer 16 can be AlN.sub.x or BN.sub.x. The dielectric layer 16 can be formed by an atomic layer deposition, a chemical vapor deposition, a physical vapor deposition or other deposition processes. Because the bottom electrode 14 has the concave-convex top surface, the dielectric layer 16 can fill in concave positions of the concave-convex top surface. Furthermore, the dielectric layer 16 can provide a flat top surface on the bottom electrode 14. That is, the top surface of the dielectric layer 16 is flat. Therefore, material layers formed subsequently can be stacked on the flat top surface of the dielectric layer 16.

[0018] As shown in FIG. 4, a superlattice layer 18 is formed to contact the dielectric layer 16. In this embodiment, the superlattice layer 18 is formed by stacking periodically and alternately at least two types of perovskite material layers. In different embodiments, more than two types of perovskite material layers can also be used for stacking. The perovskite material layers can be formed by an atomic layer deposition, a chemical vapor deposition, a physical vapor deposition or other deposition processes at an operation temperature between 350 degrees Celsius to 450 degrees Celsius. The perovskite material layers include SrTiO.sub.x, BaTiO.sub.x, CaTiO.sub.x, CaMgO.sub.x or PbTiO.sub.x. The superlattice layer 18 includes perovskite material layers not less than five layers. The total number of perovskite material layers of the superlattice layer 18 is preferably between 5 and 20 layers. According to a preferred embodiment of the present invention, the superlattice layer 18 may be formed by periodically and alternately stacking strontium titanium oxide (SrTiO.sub.x) 18a/barium titanium oxide (BaTiO.sub.x) 18b. The superlattice layer 18 has a positive voltage coefficient of capacitance (VCC).

[0019] According to another preferred embodiment of the present invention, the superlattice layer 18 can also be formed by metal doped with titanium oxide. For example, the superlattice layer 18 can be formed by stacking periodically and alternately two different metals respectively doped with titanium oxide or stacking periodically and alternately the same metal doped with different concentrations of titanium oxide.

[0020] As shown in FIG. 5, a silicon dioxide layer 20 is formed to cover and contact the superlattice layer 18. It is noteworthy that the silicon dioxide layer 20 has a negative voltage coefficient of capacitance. The silicon dioxide layer 20 is annealed, polarized and amorphous silicon dioxide. According to a preferred embodiment of the present invention, the manufacturing method of the silicon dioxide layer 20 includes forming an amorphous silicon dioxide layer 20 by a physical vapor deposition, a chemical vapor deposition or an atomic layer deposition. Later, an annealing process operated at a temperature of 400 degrees Celsius is performed to the silicon dioxide layer 20 to transform the silicon dioxide layer 20 to become polarized and has a negative voltage coefficient of capacitance. Then, a top electrode 22 is formed to cover and contact the silicon dioxide layer 20. The top electrode 22 is formed by a physical vapor deposition, a chemical vapor deposition, an atomic layer deposition or other deposition processes. Because the top electrode 22 is composed of columnar grain structures, the top electrode 22 has a concave-convex top surface. The top electrode 22 includes TIN, Al, Ta, Cu, Ti or Ta.

[0021] As shown in FIG. 6, an etching process is performed to remove part of the top electrode 22, part of the silicon dioxide layer 20 and part of the superlattice layer 18 by using the dielectric layer 16 as an etching stop layer. At this time, part of the dielectric layer 16 is exposed. After that, an inter-metal dielectric layer 24 is formed to cover the top electrode 22, the silicon dioxide layer 20, the superlattice layer 18, the dielectric layer 16 and the bottom electrode 14.

[0022] As shown in FIG. 7, a top electrode contact plug 26 is formed to penetrate the inter-metal dielectric layer 24 to contact the top electrode 22. A bottom electrode contact plug 28 is formed to penetrate the inter-metal dielectric layer 24 and the dielectric layer 16 to contact the bottom electrode 14. Now an MIM capacitor 100 of the present invention 100 is completed.

[0023] According to another preferred embodiment of the present invention, An MIM capacitor is provided in the present invention. As shown in FIG. 7, an MIM capacitor 100 is disposed on a substrate 10. An interlayer dielectric layer 12 is disposed on the substrate 10, and the interlayer dielectric layer 12 is sandwiched between the MIM capacitor 100 and the substrate 10. The MIM capacitor 100 includes a bottom electrode 14, a dielectric layer 16, a superlattice layer 18, a silicon dioxide layer 20 and a top electrode 22 stacked from bottom to top. The superlattice layer 18 contacts the dielectric layer 16 and the silicon dioxide layer 20. The silicon dioxide layer 20 has a negative voltage coefficient of capacitance. A top electrode contact plug 26 contacts the top electrode 22, and a bottom electrode contact plug 28 contacts the bottom electrode 14. The top electrode contact plug 26 and the bottom electrode contact plug 28 are located at the same side of the top surface of the substrate 10.

[0024] The substrate 10 includes a silicon substrate, a germanium substrate, a gallium arsenide substrate, a silicon germanium substrate, an indium phosphide substrate, a gallium nitride substrate, a silicon carbide substrate or a silicon-on-insulator substrate. The top electrode 22 and the bottom electrode 14 independently include TIN, Al, Ta, Cu, Ti or Ta. The dielectric layer 16 is preferably a nitrogen-containing material with a high energy band gap. For example, the dielectric layer 16 can be AlN.sub.x or BN.sub.x. Therefore, the the dielectric layer 16 is good at preventing current leakage.

[0025] The superlattice layer 18 is formed by stacking periodically and alternately at least two types of perovskite material layers. The superlattice layer 18 includes not less than 5 layers. Advantageously, the total number of perovskite material layers of the superlattice layer 18 is preferably between 5 and 20 layers. Each of the perovskite material layers has a thickness between 10 nm and 60 nm. The total thickness of the superlattice layer 18 is between 100 nm and 2400 nm. The perovskite material layers include SrTiO.sub.x, BaTiO.sub.x, CaTiO.sub.x, CaMgO.sub.x or PbTiO.sub.x. The superlattice layer 18 preferably includes perovskite material layers with low crystallinity. The superlattice layer 18 may be formed by periodically and alternately stacking not less than 5 layers of strontium titanium oxide 18a/barium titanium oxide 18b. Moreover, the silicon dioxide layer 20 is annealed, polarized and amorphous silicon dioxide.

[0026] Because the perovskite material layer has a high dielectric constant, the present invention uses the perovskite material layer as a part of the capacitor dielectric layer. However, the energy band gap of the perovskite material layer is small, so current leakage occurs easily through the perovskite material layer. Furthermore, the voltage coefficient of capacitance of the perovskite material layer is positive, so charge/discharge performance of the perovskite material layer at low voltage and high voltage is nonlinear. Therefore, in the present invention, a nitrogen-containing material with a high energy band gap is disposed under the superlattice layer formed by the perovskite material layer to prevent current leakage of the perovskite material layer. In addition, a silicon dioxide layer with a negative voltage coefficient of capacitance is disposed above the superlattice layer formed by the perovskite material layer to balance the positive voltage coefficient of capacitance. In this way, the MIM capacitor of the present invention has the advantage of a high dielectric constant provided by the perovskite material layer, and the current leakage and nonlinear charge/discharge performance can be avoided.

[0027] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.