CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Abstract

A circuit board includes a main board, a thermistor layer, a plurality of n-type semiconductor units and a plurality of p-type semiconductor units. The main board includes a first external structure, a second external structure, and an internal structure disposed between the first external structure and the second external structure. The internal structure includes a first internal circuit layer, a second internal circuit layer, and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer. The thermistor layer is disposed on the insulating layer and the first internal circuit layer. The n-type semiconductor units and the p-type semiconductor units are electrically connected to the second internal circuit layer and the second external structure, in which the n-type semiconductor units and the p-type semiconductor units are alternately arranged in one direction.

Claims

1. A circuit board, comprising: a main board, comprising: a first external structure; a second external structure; and an internal structure disposed between the first external structure and the second external structure, wherein the internal structure, the first external structure, and the second external structure are stacked along a first direction, wherein the internal structure includes: a first internal circuit layer; a second internal circuit layer; and an insulating layer disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along the first direction; a first bonding layer disposed between the internal structure and the first external structure, wherein the first bonding layer connects to the internal structure and the first external structure; a second bonding layer disposed between the internal structure and the second external structure, wherein the second bonding layer connects to the internal structure and the second external structure; a thermistor layer embedded in the first bonding layer and disposed on the insulating layer and the first internal circuit layer; and a plurality of N-type semiconductor units and a plurality of P-type semiconductor units, wherein the N-type semiconductor units and the P-type semiconductor units are embedded in the second bonding layer and electrically connect to the second internal circuit layer and the second external structure, wherein the N-type semiconductor units and the P-type semiconductor units alternately arrange along a second direction perpendicular to the first direction, and an orthogonal projection of the N-type semiconductor units and the P-type semiconductor units on the insulating layer overlaps an orthogonal projection of the thermistor layer on the insulating layer.

2. The circuit board of claim 1, wherein the second internal circuit layer comprises a plurality of cold ends, and the second external structure comprises a plurality of hot ends, wherein an ith N-type semiconductor unit is adjacent to an ith P-type semiconductor unit, the ith N-type semiconductor unit and the ith P-type semiconductor unit connect to a same cold end, and the ith P-type semiconductor unit and a (i+1)th N-type semiconductor unit connect to a same hot end, where i is a positive integer.

3. The circuit board of claim 1, wherein the N-type semiconductor units and the P-type semiconductor units electrically connect to the second external structure.

4. The circuit board of claim 3, further comprising: a thermal conductive layer disposed on the second external structure, wherein the thermal conductive layer connects to the second external structure and the second bonding layer; and a dissipation reinforcing layer disposed on the thermal conductive layer.

5. The circuit board of claim 1, further comprising: a thermal conductive layer disposed on the thermistor layer; and an image sensor disposed on the thermal conductive layer.

6. The circuit board of claim 1, wherein a protruding portion of the internal structure protrudes from a sidewall of the first external structure and a sidewall of the second external structure, wherein the main board further comprising: a first cover layer covering the protruding portion of the internal structure; and a second cover layer covering the protruding portion of the internal structure; wherein the circuit board further comprising: an extending board, wherein the extending board electrically connects to the protruding portion of the internal structure.

7. The circuit board of claim 6, wherein the extending board comprises a data processor and a driving circuit.

8. The circuit board of claim 1, further comprising: a solder mask layer disposed on the first external structure and on the second external structure.

9. The circuit board of claim 1, further comprising: a protecting layer on the first external structure, wherein the protecting layer includes a nickel-gold layer.

10. A manufacturing method of a circuit board, comprising: providing an internal structure, wherein the internal structure comprising: a first internal circuit layer; a second internal circuit layer; and an insulating layer, disposed between the first internal circuit layer and the second internal circuit layer, wherein the insulating layer, the first internal circuit layer, and the second internal circuit layer are stacked along a first direction; forming a thermistor layer on the first internal circuit layer, wherein the thermistor layer connects to the insulating layer and the first internal circuit layer; forming a first peelable glue layer on the thermistor layer; forming a first bonding layer on the first internal circuit layer, wherein the first bonding layer encapsulates the first peelable glue layer and the thermistor layer; forming a second bonding layer on the second internal circuit layer, wherein the second bonding layer comprises a plurality of recesses, the recesses expose the second internal circuit layer, and an orthogonal projection of the recesses on the insulating layer overlaps an orthogonal projection of the thermistor layer on the insulating layer; filling a N-type semiconductor material and a P-type semiconductor material in the recesses to form a plurality of N-type semiconductor units and a plurality of P-type semiconductor units, wherein the N-type semiconductor units and the P-type semiconductor units alternately arrange along a second direction perpendicular to the first direction; forming a first external structure on the first bonding layer; forming a second external structure on the second bonding layer, such that the second external structure electrically connects to the N-type semiconductor units and the P-type semiconductor units; and removing the first peelable glue layer and a portion of the first bonding layer located above the first peelable glue layer, and exposing the thermistor layer.

11. The manufacturing method of the circuit board of claim 10, further comprising: forming a thermal conductive layer on the thermistor layer.

12. The manufacturing method of the circuit board of claim 10, further comprising: disposing an image sensor on the thermistor layer; forming a thermal conductive layer on the second external structure, wherein the thermal conductive layer connects to the second external structure and the second bonding layer; and forming a dissipation reinforcing layer on the thermal conductive layer.

13. The manufacturing method of the circuit board of claim 12, further comprising: after disposing the image sensor, forming bonding wires above the image sensor, such that the image sensor is electrically connected to the first external structure.

14. The manufacturing method of the circuit board of claim 10, further comprising: forming a first cover layer on the first internal circuit layer, wherein the first cover layer separates from the thermistor layer; forming a second cover layer on the second internal circuit layer, wherein the second cover layer separates from the recesses, and an orthogonal projection of the first cover layer on the insulating layer overlaps an orthogonal projection of the second cover layer on the insulating layer; forming a second peelable glue layer on the first cover layer, wherein in the operation of forming the first bonding layer, the first bonding layer further encapsulates the second peelable glue layer and the first cover layer; forming a third peelable glue layer on the second cover layer, wherein in the operation of forming the second bonding layer, the second bonding layer further encapsulates the third peelable glue layer and the second cover layer; removing the second peelable glue layer to expose the first cover layer; and removing the third peelable glue layer to expose the second cover layer.

15. The manufacturing method of the circuit board of claim 10, further comprising: after forming the first bonding layer and the second bonding layer, forming a plated-through hole.

16. The manufacturing method of the circuit board of claim 15, further comprising: after forming the plated-through hole, forming a solder mask layer in the plated-through hole and on the first external structure and the second external structure.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0023] FIG. 1 to FIG. 8 are cross-sectional views of a circuit board at various stages of a manufacturing process in accordance with at least one embodiment of the present invention.

DETAILED DESCRIPTION

[0024] In the following text, in order to clearly present the technical features of the present disclosure, the dimensions (such as lengths, widths, thicknesses and depths) of the components (such as insulating layers, circuit layers, and through-holes, etc.) in the drawings may be enlarged in a non-proportional manner, and the number of some components may be reduced. Therefore, the description and explanation of the following embodiments are not limited to the number of components in the drawings and the size and shape of the components, but should cover the deviations in sizes, shapes and both caused by actual manufacturing processes and/or tolerances. For example, a planar surface shown in the drawings may have rough and/or non-linear features, while acute angles shown in the drawings may be rounded. Therefore, the components shown in the drawings of the present disclosure are mainly for illustration, and are not intended to accurately depict the actual shapes of the components, nor are used to limit the scope of the patent application of the present disclosure.

[0025] Further, spatially relative terms, such as beneath, below, lower, above, upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. That is, when the device is oriented differently from the drawings (rotated 90 degrees or at other orientations), the spatially relative terms used in the present disclosure may also be interpreted accordingly.

[0026] It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term and/or includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, about, approximately, essentially, or substantially can be used according to optical properties, etching properties, mechanical properties, measurement properties, coating properties or other properties. Accepted deviation ranges or standard deviations are selected, instead of one standard deviation for all properties. It should be noted that a first direction D1 and a second direction D2 are labeled in the drawings to present the configuration relationship of the components in the drawings, and the first direction D1 and the second direction D2 are substantially perpendicular to each other.

[0028] FIG. 1 to FIG. 8 are cross-sectional views of a circuit board 800 at various stages of a manufacturing process in accordance with at least one embodiment of the present invention. Referring to FIG. 1, an internal structure 100 includes a first internal circuit layer 110, a second internal circuit layer 120, and an insulating layer 130 disposed between the first internal circuit layer 110 and the second internal circuit layer 120. The insulating layer 130, the first internal circuit layer 110, and the second internal circuit layer 120 are stacked along the first direction D1.

[0029] As shown in FIG. 1, the first internal circuit layer 110 includes electrodes 111 and 112, and the electrodes 111 and 112 are spaced apart from each other. The second internal circuit layer 120 includes a plurality of cold ends 121, 122, and 123, and the cold ends 121, 122, and 123 are spaced apart from each other. The electrodes 111 and 112 and the cold ends 121, 122, and 123 are respectively disposed on opposite sides of the insulating layer 130. It is understood that both of the electrodes 111 and 112 are metal pads (or metal layers) of the first internal circuit layer 110 at this stage, and all of the cold ends 121, 122, and 123 are metal pads of the second internal circuit layer 120 at this stage.

[0030] In some embodiments, a material of the insulating layer 130 may be an insulating material such as, polyimide (PI), glass fiber epoxy resin (FR4), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyethylene (PE), but is not limited thereto.

[0031] In the present embodiment, the first internal circuit layer 110 and the second internal circuit layer 120 are formed by first forming a dry film, and then exposed and developed. Therefore, the first internal circuit layer 110 and the second internal circuit layer 120 are formed by a subtractive process. However, in other embodiments, the first internal circuit layer 110 and the second internal circuit layer 120 may be formed by a semi-additive process or an additive process. In some embodiments, a material of the first internal circuit layer 110 and/or second internal circuit layer 120 may be a conductive material such as copper, gold, or silver, but is not limited thereto.

[0032] Referring to FIG. 2, a thermistor layer 210 is formed on the first internal circuit layer 110, in which the thermistor layer 210 connects to the electrodes 111 and 112 of the first internal circuit layer 110 and the insulating layer 130. In some embodiments, a material of the thermistor layer 210 may be a material of a negative temperature coefficient thermistor (NTC) or a material of a positive temperature coefficient thermistor (PTC).

[0033] As shown in FIG. 2, a first adhesive layer 220 and a first cover layer 230 are further disposed on the first internal circuit layer 110, in which the first cover layer 230 separates from the thermistor layer 210. A second adhesive layer 240 and a second cover layer 250 are further disposed on the second internal circuit layer 120. Since the first cover layer 230 and the second cover layer 250 are respectively disposed on opposite sides of the insulating layer 13, an orthogonal projection of the first cover layer 230 on the insulating layer 130 overlaps an orthogonal projection of the second cover layer 250 on the insulating layer 130. In the present embodiment, the first cover layer 230 and the second cover layer 250 are disposed by laminating processes.

[0034] Referring to FIG. 3, a first peelable glue layer 310 is formed on the thermistor layer 210, a second peelable glue layer 320 is formed on the first cover layer 230, and a third peelable glue layer 330 is formed on the second cover layer 250. In the present embodiment, the first peelable glue layer 310, the second peelable glue layer 320, and the third peelable glue layer 330 are disposed by laminating processes. In the present embodiment, a width of the first peelable glue layer 310 in the second direction D2 substantially equals to a width of the thermistor layer 210 in the second direction D2. In the present embodiment, a width of the second peelable glue layer 320 in the second direction D2 is smaller than a width of the first cover layer 230 in the second direction D2, and a width of the third peelable glue layer 330 in the second direction D2 is smaller than a width of the second cover layer 250 in the second direction D2.

[0035] Referring to FIG. 4, a first bonding layer 410 is formed on the first internal circuit layer 110, in which the first bonding layer 410 encapsulates the first peelable glue layer 310 and the thermistor layer 210. A second bonding layer 420 is formed on the second internal circuit layer 120, in which the second bonding layer 420 includes a plurality of recesses 422 arranged along the second direction D2, and the recesses 422 expose the cold ends 121, 122, and 123 of the second internal circuit layer 120. As shown in FIG. 4, since the recesses 422 are disposed on the cold ends 121, 122, and 123 of the second internal circuit layer 120, an orthogonal projection of the recesses 422 on the insulating layer 130 overlaps an orthogonal projection of the thermistor layer 210 on the insulating layer 130.

[0036] As shown in FIG. 4, the first bonding layer 410 further encapsulates the second peelable glue layer 320 and the first cover layer 230, and the second bonding layer 420 further encapsulates the third peelable glue layer 330 and the second cover layer 250. In the present embodiment, the first bonding layer 410 and the second bonding layer 420 are disposed by laminating and pressing. In the present embodiment, materials of the first bonding layer 410 and the second bonding layer 420 may be low flow prepreg or non-flow prepreg.

[0037] As shown in FIG. 4, a metal layer 440 is formed on the first bonding layer 410, and the metal layer 450 is formed on the second bonding layer 420. After the aforementioned first bonding layer 410, second bonding layer 420, metal layer 440, and metal layer 450 are formed, a plurality of through-holes 430 are formed. In the present embodiment, the through-holes 430 may be formed using a mechanical drilling method or a laser drilling method.

[0038] Referring to FIG. 5, a N-type semiconductor material and a P-type semiconductor material are filled into the recesses 422 (referring to FIG. 4) to formed a plurality of N-type semiconductor units 510a, 510b, and 510c and a plurality of P-type semiconductor units 520a, 520b, and 530c, in which an orthogonal projection of the P-type semiconductor units 520a, 520b, and 530c on the insulating layer 130 overlaps an orthogonal projection of the thermistor layer 210 on the insulating layer 130.

[0039] N-type semiconductor units 510a, 510b, and 510c and P-type semiconductor units 520a, 520b, and 530c alternately arrange along the second direction D2. Taking FIG. 5 as an example, a first N-type semiconductor unit 510a is adjacent to a first P-type semiconductor unit 520a, a second N-type semiconductor unit 510b is adjacent to a second P-type semiconductor unit 520b, and a third N-type semiconductor unit 510c is adjacent to a third P-type semiconductor unit 520c. Therefore, an ith N-type semiconductor unit (such as the first N-type semiconductor unit 510a) would be adjacent to an ith P-type semiconductor unit (such as the first P-type semiconductor unit 520a), where i is a positive integer.

[0040] In the present embodiment, the N-type semiconductor material is filled into portions of the recesses 422 by using a printing process, and then the N-type semiconductor material is baked to form N-type semiconductor units 510a, 510b, and 510c. After that, the P-type semiconductor material is filled into the remaining portions of the recesses 422 by using a printing process, and then the P-type semiconductor material is baked to form the P-type semiconductor units 520a, 520b, and 530c. N-type semiconductor is the semiconductor in which the electron density in the conduction band is greater than the hole density in the valence band, such that the N-type semiconductor material is formed by adding acceptor impurities (for example, doping arsenic or phosphorus) to the crystal structure of silicon. P-type semiconductor is the semiconductor in which the hole density in the conduction band greater than the electron density in the valence band, such that the P-type semiconductor material is formed by adding acceptor impurities (for example, boron doping) to the crystal structure of silicon. In some embodiments, the N-type semiconductor material and the P-type semiconductor material may be bismuth antimony telluride alloys, bismuth telluride, lead telluride, silicon germanium, or skutterudite. In the present example, the N-type semiconductor material may be Bi.sub.2Sb.sub.2.7Te.sub.0.3, and the P-type semiconductor material may be BiSbTe.

[0041] It is understood that one N-type semiconductor unit and the adjacent P-type semiconductor unit form a pair of thermocouples. FIG. 5 illustrates three pairs of thermocouples (i.e., a pair of the N-type semiconductor unit 510a and the P-type semiconductor unit 520a, a pair of the N-type semiconductor unit 510b and the P-type semiconductor unit 520b, and a pair of the N-type semiconductor unit 510c and the P-type semiconductor unit 520c). The N-type semiconductor unit 510a and the P-type semiconductor unit 520a are disposed on the cold end 121, the N-type semiconductor unit 510b and the P-type semiconductor unit 520b are disposed on the cold end 122, and the N-type semiconductor unit 510c and the P-type semiconductor unit 520c are disposed on the cold end 123. It should be noted that the number of thermocouples may be adjusted according to the actual cooling demand, and is not limited to the number shown in FIG. 5.

[0042] Referring to FIG. 6, a first external structure 610 is formed on the metal layer 440, and a second external structure 620 is formed on the metal layer 450, in which the second external structure 620 electrically connects to the N-type semiconductor units 510a, 510b, and 510c and the P-type semiconductor units 520a, 520b, and 530c. It is understood that the metal layer 440 is used as a seed layer, and the first external structure 610 is electroplated on the metal layer 440. Similarly, the metal layer 450 is used as a seed layer, and the second external structure 620 is electroplated on the metal layer 450.

[0043] It is noted that second external structure 620 includes hot ends 621 and 622. It is understood that both of the hot ends 621 and 622 are metal pads of the second external structure 620 at this stage. Specifically, the P-type semiconductor unit 520a and the N-type semiconductor unit 510b connect to the same hot end 621, the P-type semiconductor unit 520b and the N-type semiconductor unit 510c connect to the same hot end 622, and the hot end 621 and the hot end 622 are spaced apart from each other. In other words, the N-type semiconductor units 510a, 510b, and 510c and the P-type semiconductor units 520a, 520b, and 530c form a series structure between the cold ends 121, 122, and 123 and the hot ends 621 and 622.

[0044] As shown in FIG. 6, in the present embodiment, the first external structure 610, the second external structure 620, and the plated-through hole 630 may be formed by plating copper to form metallic copper layers.

[0045] Referring to FIG. 7, a solder mask (SM) layer 710 is formed in the plated-through hole 630 (referring to FIG. 6) and on the first external structure 610 and the second external structure 620. In the present example, the solder mask layer 710 is formed by a printing process and a baking process.

[0046] As shown in FIG. 7, after the solder mask layer 710 is formed, a surface treatment is performed on the exposed first external structure 610 to form the protective layer 720. In the present example, the protective layer 720 includes a nickel-gold layer. The protective layer 720 may electrically connect to the underlying first external structure 610 and second external structure 620.

[0047] As shown in FIG. 7, after the protective layer 720 is formed, the first peelable glue layer 310 and a portion of the first bonding layer 410 above the first peelable glue layer 310 are removed, and the thermistor layer 210 is exposed. The second peelable glue layer 320 and a portion of the first bonding layer 410 above the second peelable glue layer 320 are removed to expose the first cover layer 230. The third peelable glue layer 330 and a portion of the second bonding layer 420 above the third peelable glue layer are removed to expose the second cover layer 250.

[0048] In the present embodiment, the first peelable glue layer 310, the second peelable glue layer 320, and the third peelable glue layer 330 are removed by using a routing process. It is understood that the material of the peelable glue layer has certain viscosity, such that it hardly has residual glue on the underlying film layer when the peelable glue layer is removed.

[0049] As shown in FIG. 7, after the thermistor layer 210, the first cover layer 230, and the second cover layer 250 are exposed, a thermal conductive layer 730 is formed on the second external structure 620, in which the second external structure 620 covers portions of the solder mask layer 710. It is understood that the second external structure 620 has hot ends 621 and 622, so the thermal conductive layer 730 covers and connects to the hot ends 621 and 622 and the second bonding layer 420 adjacent to the hot ends 621 and 622.

[0050] In the present embodiment, a material of the thermal conductive layer 73 may be silicone. In the present embodiment, the thermal conductive layer 730 is formed by a laminating process.

[0051] In the embodiment of FIG. 7, after the thermal conductive layer 730 is formed, a dissipation reinforcing layer 740 is formed on the thermal conductive layer 730. In the present embodiment, the dissipation reinforcing layer 740 is formed by a laminating process.

[0052] Referring to FIG. 8, a thermal conductive layer 810 is formed on the thermistor layer 210, and an image sensor 820 is disposed on the thermal conductive layer 810. In the present embodiment, the material and forming method of the thermal conductive layer 810 may be the same or similar to the material and forming method of the thermal conductive layer 730. In the present embodiment, the image sensor 820 is disposed by a wire-bonding process. After the image sensor 820 is disposed, bonding wires are formed above the image sensor 820, such that the image sensor 820 is electrically connected to the first external structure 610.

[0053] Please refer to FIG. 8 again. The circuit board 800 includes a main board MB and an extending board EB. The internal structure 100 of the main board MB includes a protruding portion 100p, and the protruding portion 100p is covered by the first cover layer 230 and the second cover layer 250. The protruding portion 100p protrudes from a sidewall ss1 of the first external structure 610 and a sidewall ss2 of the second external structure 620. The extending board EB electrically connects to the protruding portion 100p of the internal structure 100. It should be noted that the main board MB and the extending board EB are an integrally formed into one substrate, and the substrate is formed through the above-mentioned processes shown in FIG. 1 to FIG. 8. In the present example, the extending board EB includes a data processor and a driving circuit.

[0054] As shown in FIG. 8, the main board MB includes the thermistor layer 210, the image sensor 820, and a refrigeration structure. It is understood that the electrodes 111 and 112 are used as the electrodes of the thermistor layer 210. The refrigeration structure herein includes N-type semiconductor units 510a, 510b, and 510c, the P-type semiconductor units 520a, 520b, and 530c, the cold ends 121, 122, and 123, and hot ends 621 and 622.

[0055] The N-type semiconductor units 510a, 510b, and 510c, the P-type semiconductor units 520a, 520b, and 530c electrically connect to the cold ends 121 and 122 of the second internal circuit layer 120 and the hot ends 621 and 622 of the second external structure 620, such that the refrigeration structure are a series structure. Taking FIG. 8 as an example, the first N-type semiconductor unit 510a and the first P-type semiconductor unit 520a connect to the same cold end 121, and the first P-type semiconductor unit 520a and the second N-type semiconductor unit 510b connect to the same hot end 621. Therefore, the ith N-type semiconductor unit (such as the first N-type semiconductor unit 510a) and the ith P-type semiconductor unit (such as the first P-type semiconductor unit 520a) connects to the same cold end (such as the cold end 121), and the ith P-type semiconductor unit (such as the first P-type semiconductor unit 520a) and the (i+1)th N-type semiconductor unit (such as the second N-type semiconductor unit 510b) connect to the same hot end (such as the hot end 621), where i is a positive integer.

[0056] The disclosed extending board EB may be used as a central controller, which may determine the current magnitude flowing through the refrigeration structure according to the temperature information (for example, the temperature of the image sensor 820 measured by the thermistor layer 210).

[0057] The disclosed thermistor layer 210 is embedded in the first bonding layer 410, and the refrigeration structure is embedded in the second bonding layer 420, in which the thermistor layer 210 connects to the cold ends 121 and 122. The thermistor layer 210 is used to monitor the temperature of the upper image sensor 820 and transmits the monitored temperature to the extending board EB, and then the extending board EB uses a data processor to determine the current magnitude flowing through the refrigeration structure.

[0058] Referring to arrows of the refrigeration structure shown in FIG. 8, which represent current flow directions of the refrigeration structure. When the current flows from the N-type semiconductor units 510a, 510b, and 510c to the P-type semiconductor units 520a, 520b, and 530c, the joints above are cold ends 121, 122, and 123. When the current flows from the P-type semiconductor units 520a, 520b, and 530c to the N-type semiconductor units 510a, 510b, and 510c, the joints below are hot ends 621 and 622. The cold ends 121, 122, and 123 exchange the heat energy of the image sensor 820 by means of conduction through the insulating layer 130, the thermistor layer 210, and the thermal conductive layer 810. The thermal conductive layer 730 and the dissipation reinforcing layer 740 dissipate the heat energy of the hot ends 621 and 622 by means of conduction.

[0059] Based on the above, the provided circuit board of the present invention has the refrigeration structure. The refrigeration structure can adjust the cooling effect according to the demand, and the cold ends of the refrigeration structure can remove the heat energy of the image sensor. Therefore, the heat energy of the circuit board can be effectively dissipated.

[0060] The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.