METHOD FOR DEFINING MULTIPLE RESIST PATTERNS

Abstract

The present disclosure provides a method for defining multiple resist patterns. In the present disclosure, by using a double-exposing process in combination with a dual-developing process (i.e., a PTD process followed by an NTD process), different resist patterns (e.g., a groove pattern and a through hole pattern) can be formed on a same resist layer. Problems encountered in the prior art, such as insufficient DOF, formation of abnormal patterns, self-alignment issue, overlying problem, and so on, can be successfully addressed.

Claims

1. A method for defining multiple resist patterns, comprising: providing a substrate including a peripheral region and an array region adjacent to the peripheral region; coating a dual-tone photoresist on the substrate to form a resist layer; sequentially exposing the resist layer to ultraviolet radiation via a first photomask and a second photomask to define groove patterns in the array region and the peripheral region; developing the resist layer using a positive-tone developer to form groove patterns in the array region and the peripheral region; exposing the resist layer to ultraviolet radiation via a third, a fourth, or a fifth photomask to define a through hole pattern in the groove pattern in either the array region, the peripheral region, or both; and developing the resist layer using a negative-tone developer to form a through hole pattern in the groove pattern in either the array region, the peripheral region, or both.

2. The method according to claim 1, further comprising pre-treating the substrate by dehydration and soft-baking for reducing or eliminating moisture on a surface of the substrate before the step of coating a dual-tone photoresist on the substrate to form a resist layer.

3. The method according to claim 1, further comprising adding a compound selected from the group consisting of hexa-methyl-disilazane (HMDS), tri-methyl-silyl-diethyl-amine (TMSDEA), and combinations thereof to a surface of the substrate before the step of coating a dual-tone photoresist on the substrate to form a resist layer.

4. The method according to claim 1, further comprising soft-baking the resist layer after the step of coating a dual-tone photoresist on the substrate to form a resist layer.

5. The method according to claim 1, wherein the step of coating a dual-tone photoresist on the substrate to form a resist layer is performed by spin-coating, sputtering, atomic layer deposition (ALD), atomic layer epitaxy (ALE), atomic layer chemical vapor deposition (ALCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or combination thereof.

6. The method according to claim 5, wherein the step of coating a dual-tone photoresist on the substrate to form a resist layer is carried out by spin coating.

7. The method according to claim 5, wherein the step of coating a dual-tone photoresist on the substrate to form a resist layer is carried out by ALD.

8. The method according to claim 1, wherein the dual-tone photoresist is a photoresist SAIL-Z187©.

9. The method according to claim 1, further comprising soft-baking the resist layer after the step of sequentially exposing the resist layer to ultraviolet radiation via a first photomask and a second photomask to define groove patterns in the array region and the peripheral region.

10. The method according to claim 1, wherein the positive-tone developer is an aqueous solution of tetra-methyl ammonium hydroxide.

11. The method according to claim 1, further comprising soft-baking the resist layer after the step of exposing the resist layer to ultraviolet radiation via a third, a fourth, or a fifth photomask to define a through hole pattern in the groove pattern in either the array region, the peripheral region, or both.

12. The method according to claim 1, wherein the negative-tone developer is an organic solution of n-butyl acetate (n-BA).

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0027] FIG. 1 is a representative flow diagram of a method 10 for defining multiple resist patterns according to an embodiment of the present disclosure.

[0028] FIG. 2 is an illustrative perspective view showing a substrate 201 according to an embodiment of the present disclosure after performing of step S101 in FIG. 1.

[0029] FIG. 3 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after performing of step S103 in FIG. 1.

[0030] FIG. 4A is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after performing of step S105 in FIG. 1 using a first photomask.

[0031] FIG. 4B is an illustrative top view showing the substrate 201 in FIG. 4A.

[0032] FIG. 4C is a schematic cross-sectional view, taken along line A-A in FIG. 4B, of the substrate 201 according to an embodiment of the present disclosure after the performing of step S105 in FIG. 1 using a first photomask.

[0033] FIG. 5A is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S105 in FIG. 1 using a second photomask.

[0034] FIG. 5B is an illustrative top view showing the substrate 201 in FIG. 5A.

[0035] FIG. 5C is a schematic cross-sectional view, taken along line B-B in FIG. 5B, of the substrate 201 according to an embodiment of the present disclosure after the performing of step S105 in FIG. 1 using a second photomask.

[0036] FIG. 6A is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after performing of step S107 in FIG. 1.

[0037] FIG. 6B is an illustrative top view showing the substrate 201 in FIG. 6A.

[0038] FIG. 6C is a schematic cross-sectional view, taken along line C-C in FIG. 6B, of the substrate 201 according to an embodiment of the present disclosure after the performing of step S107 in FIG. 1.

[0039] FIG. 7 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after performing of step S109 in FIG. 1 using a third photomask 701 with a through hole pattern in the groove pattern in the array region.

[0040] FIG. 8 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S109 in FIG. 1 using a fourth photomask 801 with a through hole pattern in the groove pattern in the peripheral region.

[0041] FIG. 9 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S109 in FIG. 1 using a fifth photomask 901 with a through hole pattern in the groove pattern in both the array region and the peripheral region.

[0042] FIG. 10 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S109 using the third photomask 701 as shown in FIG. 7 and step S111 in FIG. 1.

[0043] FIG. 11 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S109 using the third photomask 801 as shown in FIG. 8 and step S111 in FIG. 1.

[0044] FIG. 12 is an illustrative perspective view showing the substrate 201 according to an embodiment of the present disclosure after the performing of step S109 using the third photomask 901 as shown in FIG. 9 and step S111 in FIG. 1.

DETAILED DESCRIPTION

[0045] For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.

[0046] Embodiments (or examples) of the disclosure illustrated in the drawings are now described using specific language. It shall be understood that no limitation to the scope of the disclosure is hereby intended. Any alteration or modification of the described embodiments, and any further applications of principles described in this document, are to be considered as normally occurring to one of ordinary skill in the art to which the disclosure relates. Reference numerals may be repeated throughout the embodiments, but this does not necessarily mean that feature(s) of one embodiment apply to another embodiment, even if they share the same reference numeral.

[0047] The terminology used herein is for the purpose of describing particular example embodiments only and is not intended to be limited to the present inventive concept. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It shall be further understood that the terms “comprises” and “comprising,” when used in this specification, point out the presence of stated features, integers, steps, operations, elements, or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

[0048] As used herein, the terms “patterning” and “patterned” are used in the present disclosure to describe an operation of forming a predetermined pattern on a surface. The patterning operation includes various steps and processes, and varies in accordance with different embodiments. In some embodiments, a patterning process is adopted to pattern an existing film or layer. The patterning process includes forming a mask on the existing film or layer and removing an unmasked portion of the film or layer with an etching or other removal process. The mask can be a photoresist or a hard mask. In some embodiments, a patterning process is adopted to form a patterned layer directly on a surface. The patterning process includes forming a photosensitive film on the surface, conducting a photolithography process, and performing a developing process. After the developing process, a remaining portion of the photosensitive film is retained and integrated into the semiconductor device.

[0049] It shall be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers or sections, these elements, components, regions, layers or sections are not limited by these terms. Rather, these terms are merely used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present inventive concept.

[0050] The present disclosure will be described in detail with reference to the accompanying drawings with numbered elements. It should be noted that the drawings are in greatly simplified form and are not drawn to scale. Moreover, dimensions have been exaggerated in order to provide a clear illustration and understanding of the present invention.

[0051] The method for defining multiple resist patterns of the present disclosure will be explained in detail below along with drawings.

[0052] FIG. 1 is a representative flow diagram of a method 10 for defining multiple resist patterns according to an embodiment of the present disclosure. FIGS. 2, 3, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C, 7, 8, 9, 10, 11, and 12 are illustrative perspective views, top views or schematic cross-sectional views showing a semiconductor device after steps of the method are performed in accordance with some embodiments of the present disclosure.

[0053] Referring to FIGS. 1 and 2, a substrate 201 including a peripheral region and an array region adjacent to the peripheral region is provided. The substrate 201 can optionally be pre-treated by dehydration and baking so as to reduce or eliminate moisture on a surface of the substrate 201 before performing a next step. In addition, in order to improve adhesion of a resist layer 203 (as shown in FIG. 3) on the surface of the substrate 201, compounds such as hexa-methyl-disilazane (HMDS) and tri-methyl-silyl-diethyl-amine (TMSDEA) can be applied to the surface of the substrate 201.

[0054] In the present disclosure, the term “substrate” means and includes a base material or construction upon which materials are formed. It will be appreciated that the substrate may include a single material, a plurality of layers of different materials, a layer or layers having regions of different materials or different structures in them, or another similar arrangement. These materials may include semiconductors, insulators, conductors, or combinations thereof. For example, the substrate 201 may be a semiconductor substrate, a base semiconductor layer on a supporting structure, a metal electrode, or a semiconductor substrate having one or more layers, structures or regions formed thereon. The substrate 201 may be a conventional silicon substrate or other bulk substrate including a layer of semiconductive material. In some embodiments, the substrate 201 may be a silicon (Si) substrate, a germanium (Ge) substrate, a silicon germanium (SiGe) substrate, a silicon-on-sapphire (SOS) substrate, a silicon-on-quartz substrate, a silicon-on-insulator (SOI) substrate, an III-V compound semiconductor, a combination thereof, or the like.

[0055] Referring to FIGS. 1 and 3, in step S103, a resist layer 203 is formed on the substrate 201 by coating a dual-tone photoresist on the substrate 201. A process such as spin-coating, sputtering, atomic layer deposition (ALD), atomic layer epitaxy (ALE), atomic layer chemical vapor deposition (ALCVD), chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like can be used for the performing of step S103. In one exemplary process, the dual-tone photoresist is applied to the substrate 201, and the substrate 201 is then spun on a turntable at a high speed to produce a resist layer 203 having a desired thickness. This process is known as spin coating. Without intending to be bound by theory, the thickness of the dual-tone photoresist is inversely proportional to a square root of the spin speed and is directly proportional to a viscosity of the dual-tone photoresist. Thus, greater spin speeds lead to a thinner resist layer while a more viscous photoresist material leads to a thicker resist layer. In another exemplary process, the dual-tone photoresist is applied to the substrate 201 by ALD.

[0056] The term “dual-tone photoresist” refers to a photoresist which can be used to produce either positive-tone or negative-tone relief patterns depending on a choice of development solvent used. Typically, a single development step is used to produce a negative-tone or positive-tone film from a dual-tone resist; this single-step process is a standard lithographic procedure used in semiconductor manufacturing. A dual-tone resist can also be used in alternative “dual-tone development” processes in a sidewall-based double-patterning procedure. In this type of dual-tone development, a first development step uses PTD to remove high exposure dose areas and a subsequent development step uses NTD to remove unexposed or least-exposed dose areas. Dual-tone development of the resist film leaves the intermediate dose areas defining the two features edges intact. Within the context of the present invention, dual-tone development is carried out with two different organic solvents, a PTD organic solvent and an NTD organic solvent. A PTD resist is a type of photoresist in which a portion of the photoresist that is exposed to light becomes soluble to a photoresist developer, while an unexposed portion of the photoresist remains insoluble to the photoresist developer. An NTD resist is a type of photoresist in which a portion of the photoresist that is exposed to light becomes insoluble to the photoresist developer, while an unexposed portion of the photoresist is dissolved by the photoresist developer.

[0057] The terms “positive-tone development” and “PTD,” which are used interchangeably throughout the present disclosure, refer to a method by which exposure of a photoresist to a light source, typically followed by post-exposure bake, changes a composition of the photoresist such that exposed portions of the photoresist become more soluble in a positive-tone developing solvent. When the photoresist is developed with this solvent, exposed portions of the photoresist are washed away, leaving a positive-tone relief pattern in the resist film. Within a context of the present invention, the PTD solvent is an organic solvent. The terms “negative-tone development” and “NTD,” which are used interchangeably throughout the present disclosure, refer to a lithography method by which exposure of the photoresist to a light source, typically followed by post-exposure bake, changes the composition of the photoresist, making it more difficult to dissolve in an NTD solvent. When the photoresist is developed, only unexposed portions of the photoresist wash away, leaving a negative-tone relief pattern etched in the resist. Within the context of the present invention, the NTD solvent is an organic solvent. The NTD organic solvent is selected from a group consisting of methyl amyl ketone (MAK), n-butyl acetate (nBA), n-pentylacetate (nPA), ethyl amyl ketone (EAK), and combinations thereof.

[0058] Any commercially-available dual-tone photoresists can be used in step S103 of the present disclosure. Preferably, the dual-tone photoresist is a photoresist of the SAIL series sold by ShinEtsu Company of Japan. Most preferably, the dual-tone photoresist comprises a photoresist SAIL-Z187© sold by ShinEtsu Company of Japan.

[0059] In some embodiments, the dual-tone photoresist according to the present disclosure includes a polymer resin along with one or more photoactive compounds (PACs) in a solvent. Optionally, additives such as a cross-linking agent, a coupling agent, a solvent, a quencher, a stabilizer, a dissolution inhibitor, a plasticizer, a coloring agent, an adhesion additive, a surface leveling agent, and so on can be added to the photoresist.

[0060] A resulting resist layer usually contains a certain amount of solvent, for example, between 20 wt. % and 40 wt. %. A so-called soft-baking or pre-baking process can be used to remove excess solvent. A main reason for reducing the solvent content is to stabilize a resulting resist layer. At room temperature, an unbaked resist layer will lose solvent by evaporation, thus changing properties of the resist layer over time. By baking the resist layer, a majority of the solvent is removed and the resist layer becomes stable at room temperature. There are four major effects of removing solvent from the resist layer: (1) thickness is reduced, (2) post-exposure bake and development properties are changed, (3) adhesion is improved, and (4) the photoresist layer becomes less tacky and thus less susceptible to particulate contamination. Typical pre-bake processes leave between 3 wt. % and 8 wt. % residual solvent in the resulting resist layer, which is low enough to keep the resulting resist layer stable during subsequent lithographic processing.

[0061] Referring to FIGS. 1, 4A, 4B, 4C, 5A, 5B, and 5C, in step S105, the resist layer 203 is exposed to radiation such as deep ultraviolet (DUV) light through a first photomask 205 and a second photomask 209. The first photomask 205 is used to define a first groove pattern 207 in the array region. The second photomask 209 is used to define a second groove pattern 211 in the peripheral region. The first groove pattern 207 and the second groove pattern 211 are substantially light-transmittable under a subsequent photomask (i.e., the third photomask 701 in FIG. 7, the fourth photomask 801 in FIG. 8, and the fifth photomask 901 in FIG. 9) so that the first groove pattern 207 and the second groove pattern 211 will not be changed during a subsequent NTD process.

[0062] Optionally, after the performing of step S105, the substrate 201 is subjected to a soft baking step to improve the stability of the first groove pattern 207 and the second groove pattern 211 on the substrate 201.

[0063] Referring to FIGS. 1, 6A, 6B, and 6C, in step S107, the resist layer 203 is developed using a positive-tone developer so as to form a first groove pattern 207 in the array region and a second groove pattern 211 in the peripheral region. Positive-tone developers are typically aqueous base developers, such as tetraalkylammonium hydroxide (TMAH). In non-limiting examples, an aqueous solution of TMAH having a concertation of 2.38 wt. % may be used as the positive-tone developer.

[0064] Referring to FIGS. 1 and 7 to 9, in step S109, the first groove pattern 207 in the array region and the second groove pattern 211 in the peripheral region are exposed to radiation such as deep ultraviolet (DUV) light through a third photomask 701, a fourth photomask 801, or a fifth photomask 901 to define a through hole pattern in the groove pattern in either the array region, the peripheral region, or both. The third photomask 701 in FIG. 7 is used to define a through hole pattern 703 in the first groove pattern 207 in the array region. The fourth photomask 801 in FIG. 8 is used to define a through hole pattern 803 in the second groove pattern 211 in the peripheral region. The fifth photomask 901 in FIG. 9 is used to define a through hole pattern 903 in the first and second groove patterns 207 and 211 in the array region and the peripheral region simultaneously.

[0065] Optionally, after the performing of step S109, the substrate 201 is subjected to a soft baking step to improve the stability of the through hole pattern in the first groove pattern 207, the second groove pattern 211, or both.

[0066] Referring to FIGS. 1 and 10 to 12, in step S111, the resist layer 203 is developed using a negative-tone developer to form a through hole pattern 1001 in the array region (see FIG. 10), a through hole pattern 1101 in the peripheral region (see FIG. 11), or through hole patterns 1001 and 1101 in both the array region and the peripheral region (see FIG. 12). In certain embodiments of the present disclosure, the negative-tone developer may be an organic solvent that is selected to solvate the unexposed portion of the photoresist while not solvating the exposed portion of the photoresist. NTD developers are typically organic-based developers. In non-limiting examples, an organic solution of n-butyl acetate (n-BA) is used as the negative-tone developer.

[0067] Optionally, after the performing of step S111, the substrate 201 is subjected to a soft baking step to improve the stability of the through hole patterns 1001 and 1101.

[0068] In the present disclosure, by using a double-exposing process in combination with a dual-developing process (i.e., a PTD process followed by an NTD process), different resist patterns (e.g., a groove pattern and a through hole pattern) can be formed on a same resist layer. Problems encountered in the prior art, such as insufficient DOF, formation of abnormal patterns, self-alignment issue, overlying problem, and so on, can be successfully addressed.

[0069] It should be understood that the preceding examples are included to demonstrate specific embodiments of the present disclosure. It should be appreciated by those having skill in the art that the techniques disclosed in the examples which follow represent techniques discovered by the inventors to function well in the practice of the present disclosure, and thus can be considered to constitute preferred modes for its practice. However, it should be understood that the present disclosure is not intended to be limited to the particular forms disclosed. Rather, the different aspects of the disclosed process may be utilized in various combinations and/or independently. Thus, the present disclosure is not limited to only those combinations shown herein, but rather may include other combinations. Further, those having skill in the art should, in light of the present disclosure, appreciate that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the processes discussed above can be implemented in different methodologies and replaced by other processes, or a combination thereof.

[0070] Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein, may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, and steps.