Abstract
An integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the integrated circuit substrate comprises a support structure having at least one hole, and at least two functional inlays placed inside said at least one hole side by side, wherein a pitch at an integrated circuit component mounting side of the integrated circuit substrate is not more than 150 m.
Claims
1. An integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the integrated circuit substrate comprises: a support structure having at least one hole; and at least two functional inlays placed inside said at least one hole side by side; wherein a pitch at an integrated circuit component mounting side of the integrated circuit substrate is not more than 150 m.
2. The integrated circuit substrate according to claim 1, wherein the support structure has a plurality of holes, and wherein the at least two functional inlays are placed inside said plurality of holes.
3. The integrated circuit substrate according to claim 1, wherein the support structure is a frame structure.
4. The integrated circuit substrate according to claim 1, comprising a mounting board being connected to the support structure by an electromechanical interconnection layer.
5. The integrated circuit substrate according to claim 1, wherein upper main surfaces of the functional inlays form part of a top main surface of the integrated circuit substrate and/or lower main surfaces of the functional inlays form part of a bottom main surface of the integrated circuit substrate.
6. The integrated circuit substrate according to claim 1, wherein at least one of the functional inlays has at least one slanted sidewall.
7. The integrated circuit substrate according to claim 1, wherein at least one of the functional inlays has a non-rectangular cross-section.
8. The integrated circuit substrate according to claim 1, wherein at least one of the functional inlays is configured to provide a power conversion function, in particular a direct current-to-direct current (DC to DC) converter function.
9. The integrated circuit substrate according to claim 1, wherein the pitch at the integrated circuit component mounting side is different from a pitch at a mounting base mounting side.
10. The integrated circuit substrate according to claim 1, comprising at least one electrical and/or mechanical connection structure at least on one main surface of a respective one of the functional inlays.
11. An electronic device, which comprises an integrated circuit substrate according to claim 1.
12. The electronic device according to claim 11, comprising at least one integrated circuit component, in particular a semiconductor element, being surface mounted on the integrated circuit component mounting side.
13. The electronic device according to claim 11, comprising a mounting base, in particular a printed circuit board or an interposer, on which the integrated circuit substrate is mounted.
14. The electronic device according to claim 12, wherein: the integrated circuit substrate has an exposed substrate pad and has an exposed substrate dielectric; the integrated circuit component has an exposed component pad and has an exposed component dielectric; and the integrated circuit substrate is connected with the integrated circuit component so that there is a direct physical contact between the substrate pad and the component pad and so that there is a direct physical contact between the substrate dielectric and the component dielectric.
15. A method of manufacturing an integrated circuit substrate for surface mounting an integrated circuit component thereon, wherein the method comprises: providing a support structure with at least one hole; placing at least two functional inlays inside said at least one hole side by side; and forming a pitch at an integrated circuit component mounting side of the integrated circuit substrate being not more than 150 m.
16. The integrated circuit substrate according to claim 1, wherein at least one of the functional inlays is configured to provide a power distribution function, in particular a redistribution structure function.
17. The integrated circuit substrate according to claim 1, wherein at least one of the functional inlays is configured to provide a power delivery function.
18. The integrated circuit substrate according to claim 17, wherein the power delivery function is provided by a plurality of embedded capacitor components.
19. The integrated circuit substrate according to claim 1, further comprising at least one security component embedded in at least one of the functional inlays.
20. The integrated circuit substrate according to claim 1, wherein the pitch at the integrated circuit component mounting side is different in regions of different functional inlays.
Description
[0103] FIG. 1 illustrates a cross-sectional view of an electronic device according to an exemplary embodiment of the invention.
[0104] FIG. 2 illustrates a cross-sectional view of an IC substrate according to an exemplary embodiment of the invention.
[0105] FIG. 3 illustrates a cross-sectional view of an IC substrate according to another exemplary embodiment of the invention.
[0106] FIG. 4 illustrates a cross-sectional view of an IC substrate according to another exemplary embodiment of the invention.
[0107] FIG. 5 illustrates a cross-sectional view of an IC substrate according to another exemplary embodiment of the invention.
[0108] FIG. 6 illustrates a plan view of an IC substrate according to another exemplary embodiment of the invention.
[0109] FIG. 7 illustrates a cross-sectional view of an IC substrate according to another exemplary embodiment of the invention.
[0110] FIG. 8 to FIG. 10 illustrate cross-sectional views of functional inlays for an IC substrate according to exemplary embodiments of the invention.
[0111] FIG. 11 illustrates a cross-sectional view of an electronic device according to another exemplary embodiment of the invention.
[0112] The illustrations in the drawings are schematic. In different drawings, similar or identical elements are provided with the same reference signs.
[0113] Before, referring to the drawings, exemplary embodiments will be described in further detail, some basic considerations will be summarized based on which exemplary embodiments of the invention have been developed.
[0114] According to an exemplary embodiment of the invention, an IC substrate (having a characteristic pitch of not more than 150 m, preferably less) for surface mounting a bare semiconductor chip is provided. Advantageously, such an IC substrate comprises a (preferably core-type) support structure with embedded functional inlays arranged side by side. Such an architecture may make it possible to obtain an IC substrate with highly compact design in vertical direction which simultaneously provides a sophisticated electronic functionality being flexibly configurable by correspondingly selecting the embedded functional inlays. By embedding inlays in a support structure of the IC substrate, additional functionality may be integrated specifically in those regions where needed for a specific application. Preferably, such functional inlays may be pre-fabricated known-good components allowing to manufacture IC substrate with high yield.
[0115] The described approach has advantages: By splitting an IC substrate into separate blocks with specific functions, a functional optimization of the IC substrate volume may be achieved. Such an architecture may be versatile and may allow an efficient material usage and design for individual functional inlays or blocks. By an appropriate frame material choice, warpage may be efficiently suppressed. Application-adapted electrically insulating layer structures may be implemented in the IC substrate, for instance for influencing Young modulus, shrinkage behavior, thermal expansion, etc.
[0116] Furthermore, pre-tested and therefore known-good functional inlays may be implemented for achieving a high yield.
[0117] According to exemplary embodiments of the invention, any of the functions and sub-functions, alone or in any combination, mentioned in the following may be integrated in any functional inlay of an integrated circuit substrate: [0118] Security function: [0119] Embedding of memory with engines for encryption or for storing sensitive data (such as VPD/keywords/identifier) [0120] Construction of anti-tamper structure to avoid fraudulent handling of the hardware [0121] Integration to obtain a Hardware Security Module (HSM) [0122] Embedding of oscillator and/or crystal to avoid tamper of clock functions [0123] Protect all the above with the creation of a sensing network between devices and external accessible layers [0124] Thermal management function: [0125] Integration of heat-dissipative structures (for example copper slugs, thermal inlay) [0126] Multiple laser vias construction to increase thermal transfer [0127] Integration of heat-pipe(s) within one of the multi-functional sub-cores (i.e. functional inlays) [0128] Electrical function: [0129] Embedding of capacitances in areas close to a point of load of a microprocessor or an accelerator [0130] Embedding of other passive components to create filters [0131] Highly effective partitioning of the metal features supporting power domains [0132] Fully plated mechanical holes filled with copper for lower resistivity and higher ampacity [0133] Power networking distribution of power through thick planes [0134] Different copper thicknesses in different sub-cores [0135] Different drill diameters in the sub-cores for power feeding structures [0136] Flexibility in the wiring of structures (laser vias stacking) not influenced by the positioning of plated through holes [0137] Structural function: [0138] Sub-cores can have cavities (for instance for creating resonators, waveguides) [0139] Physical separation of analog circuits from digital circuits [0140] Sub-cores can be made of different dielectric materials (including glass) [0141] Every sub-core can be tested prior of its use in the stacking of the multi-functional core [0142] Sub-cores can be constructed so that embedded components are enclosed into a Faraday cage (for instance by cavity plating (for instance in the hole's wall or in the inlay itself), formation of a via fence) [0143] Different copper thicknesses in different sub-cores [0144] Different drill diameters in the sub-cores for power feeding structures [0145] Electrooptical integration function: [0146] Sub-core(s) can be designed to host optical waveguides, mirrors, coupling schemes like adiabatic coupling [0147] Sub-core can be designed to host an optical connector to receive or to inject optical signal to and/or from external
[0148] FIG. 1 illustrates a cross-sectional view of an electronic device 120 according to an exemplary embodiment of the invention.
[0149] The illustrated electronic device 120 comprises a central integrated circuit substrate 100, also denoted as IC substrate. Furthermore, the electronic device 120 comprises integrated circuit components 102 which are here configured as bare dies (i.e. non-encapsulated semiconductor chips) and which are surface mounted on a top main surface of the IC substrate 100, i.e. at an integrated circuit component mounting side 140 thereof. In the shown embodiment, two IC components 102 are surface mounted on the IC substrate 100. The IC components 102 may be configured as semiconductor chips, for instance active semiconductor chips. Examples of the IC components 102 are processors, memories, sensors, logic chips, microelectromechanical systems (MEMS), etc.
[0150] On a bottom side of the electronic device 120, a mounting base 136 is provided on which the IC substrate 100 is mounted. For example, the mounting base 136 may be a printed circuit board (PCB) or an interposer. Although not shown in FIG. 1, further components (such as further IC substrates, further (in particular over-molded) semiconductor chips, etc.) may be assembled on the mounting base 136.
[0151] As shown in FIG. 1 as well, electric connection structures 144 may be formed on both opposing main surfaces of the IC substrate 100. For instance, said electric connection structures 144 may be solder balls or solder bumps, or may be configured as sinter structures (for instance may be formed based on sinter paste). The electric connection structures 144 on the bottom main surface of the integrated circuit substrate 100 are connected electrically and mechanically with bottom-sided pads 150 of the IC substrate 100. As shown, a pitch, d, between adjacent bottom-sided pads 150 may be larger than a pitch, D, between adjacent top-sided pads 152 of the IC substrate 100.
[0152] Correspondingly, a mutual distance between adjacent electric connection structures 144 is smaller on a top side of the IC substrate 100 than on a bottom side. To put it shortly, the pitch, d, of for example the 250 m matches with the requirements of PCB technology, whereas the pitch, D, of for example 100 m matches with the requirements of semiconductor technology. More generally, pitch, D, at the integrated circuit component mounting side 140 of the integrated circuit substrate 100 may be not more than 150 m, in particular not more than 100 m. Correspondingly, pitch, d, at mounting base mounting side 142 of the integrated circuit substrate 100 may be more than 200 m, in particular more than 300 m. As shown, the bottom-sided pads 150 are electrically coupled with mounting base pads 154 of mounting base 136 by the bottom-sided electric connection structures 144. Correspondingly, the top-sided pads 152 of the IC substrate 100 are electrically coupled with integrated circuit component pads (which may also be denoted as chip pads) 156 of the IC components 102 by the top-sided electric connection structures 144.
[0153] In the following, construction of the IC substrate 100 will be explained in further detail:
[0154] As shown in FIG. 1, the integrated circuit substrate 100 comprises a support structure 104 having a plurality of through holes. The support structure 104 serves as a mechanically stable frame structure for mechanically supporting the surface mounted integrated circuit components 102 and for accommodating functional inlays 108. For example, the support structure 104 may be a fully cured core made of FR4 material, optionally with embedded electrically conductive structures therein. Such embedded electrically conductive structures may be, for example, copper filled drill holes, patterned copper layers, etc. Holes for accommodating functional inlays 108 may be formed in the support structure 104 for example by mechanically cutting, by laser processing, by etching or by routing.
[0155] In the embodiment of FIG. 1, three pre-fabricated functional inlays 108 are placed inside said holes side by side, i.e. sideways or laterally with respect to each other. Each functional inlay 108 may provide a dedicated function, and functions provided by different functional inlays 108 may be different. It is also possible that only two inlays 108 or at least four inlays 108 are provided. In the shown embodiment, one functional inlay 108 per hole is provided. Alternatively, two or more functional inlays 108 may be inserted per hole. It is also possible that a larger or smaller number of holes is provided. It is also possible that blind holes or recesses or cavities are provided additionally or alternatively to through holes. FIG. 1 does not show the detailed construction of the functional inlays 108. However, examples for functional inlays 108 which may be pre-fabricated and may then be inserted into the frame-type support structure 108 are illustrated in FIG. 8 to FIG. 10.
[0156] Preferably, the functional inlays 108 may be configured so that the surface mounted integrated circuit components 102 functionally cooperate with the functional inlays 108. For instance, the functional inlays 108 may provide additional functionality in terms of power conversion, power distribution, power delivery, etc.
[0157] As shown in FIG. 1 as well, the IC substrate 100 comprises a laminated layer stack 110 on a bottom main surface of the support structure 104 and of the functional inlays 108. Furthermore, a further laminated layer stack 112 may be formed on an opposing other main surface of the support structure 104 and of the functional inlays 108. Hence, a further build-up may be formed on one or both opposing main surfaces of the support structure 104 with embedded functional inlays 108. Any of the laminated layer stacks 110, 112 may comprise one or more electrically conductive layer structures (such as patterned copper foils which may form horizontal pads and/or a horizontal wiring structure, and/or vertical through connections such as copper pillars and/or copper filled laser vias) and one or more electrically insulating layer structures (such as prepreg or resin sheets). For example, the laminated layer stack 110 and/or the further laminated layer stack 112 may have a larger integration density than the support structure 104 with the inserted functional inlays 108. Advantageously, it is also possible that the bottom-sided laminated layer stack 110 has a lower integration density than the top-sided further laminated layer stack 112. Hence, a locally higher integration density may be formed next to the surface mounted IC components 102 having a higher integration density as well. However, a lower integration density may be sufficient next to the mounting base 136 with its lower integration density characteristic for PCB-technology. This may allow to manufacture the support structure 104 with low effort and to provide one or more regions of higher integration density only when needed. For instance, any of the optional layer stacks 110, 112 may contribute to a mechanical strengthening and/or the formation of a redistribution layer in the framework of the electronic device 120.
[0158] Again referring to FIG. 1, instead of providing a monolithic substrate, the shown embodiment uses sublets or sub-segments in form of the functional inlays 108 which are inserted into the main body of the integrated circuit substrate 100 and each providing a different functionality. Preferably, the functional inlays 108 comprise organic laminate material (see for instance FIG. 8 to FIG. 10) rather than being a semiconductor chip only. However, a functional inlay 108 may nevertheless comprise one or more embedded components (such as semiconductor chips) in addition to organic laminate material (see for instance FIG. 9 or FIG. 10).
[0159] It should be mentioned that the solder balls connecting the IC substrate 100 and the IC components 102 may be smaller than the solder balls connecting the IC substrate 100 with the mounting base 136.
[0160] FIG. 2 illustrates a cross-sectional view of an IC substrate 100 according to an exemplary embodiment of the invention.
[0161] To put it shortly, FIG. 2 illustrates IC substrate 100 of FIG. 1 without IC components 102 and without mounting base 136.
[0162] Referring to FIG. 2, possible functions which may be implemented in any of the functional inlays 108 may be in particular the following: [0163] signal routing (in particular for high-speed applications) [0164] power delivery (in particular by multilayer structures, embedded passive components, etc.) [0165] thermal functionality (for instance by heat-removing copper slugs) [0166] an electro-optical transducing function (In such a transducer, there may be several components. As a signal may be digital but light may be actually analog, an analog/digital converter and a digital/analog converter may be implemented. Furthermore, a digital signal processor may be implemented to distribute the data into different signal lanes. All these functions can be integrated in one IC component or in different IC components. Furthermore, photodiodes may translate optical signals into electrical ones, but optical signals may be generated by a laser or an external light source. Modulation of such a light may also be possible, which may be done with driver IC components controlling the laser itself or modulators on a photonic IC.) [0167] formation of an organic or silicon bridge (for instance for fine line structures) [0168] antenna or other high-frequency functions
[0169] FIG. 3 illustrates a cross-sectional view of an IC substrate 100 according to another exemplary embodiment of the invention.
[0170] The embodiment of FIG. 3 differs from the embodiment of FIG. 2 in particular in that, in the embodiment of FIG. 3, the laminated layer stacks 110, 112 are omitted. Furthermore, IC substrate 100 according to FIG. 3 comprises a mounting board 114 connected to the support structure 104 by an electromechanical interconnection layer 116. For instance, the electromechanical interconnection layer 116 has adhesive properties (for instance initially comprises uncured sticky prepreg or resin sheet) for mechanically interconnecting the mounting board 114 with the functional inlays 108 and with the support structure 104. Although not shown in FIG. 3, the electromechanical interconnection layer 116 can be provided with drilled holes filled with electrically conductive material (such as an electrically conductive paste, nanowires, solder material, plated copper, etc.). For instance, mounting board 114 may be an organic board, such as a piece of PCB. Mounting board 114 can for instance provide a power and/or signal supply function.
[0171] Due to the omission of laminated layer stack 112 in FIG. 3, upper main surfaces 118 of the functional inlays 108 as well as upper main surfaces of support structure 104 form part of a top main surface 122 of the integrated circuit substrate 100.
[0172] While the functional inlays 108 are coplanar according to FIG. 3, they can also be arranged at different vertical levels, as shown for instance in FIG. 7.
[0173] FIG. 4 illustrates a cross-sectional view of an IC substrate 100 according to another exemplary embodiment of the invention.
[0174] The embodiment of FIG. 4 differs from the embodiment of FIG. 2 in particular in that, in the embodiment of FIG. 4, the laminated layer stacks 110, 112 are omitted. As a result, upper main surfaces 118 of the functional inlays 108 as well as upper main surfaces of support structure 104 form part of top main surface 122 of the integrated circuit substrate 100, and lower main surfaces 124 of the functional inlays 108 as well as lower main surfaces of the support structure 104 form part of a bottom main surface 126 of the integrated circuit substrate 100. Electrical and/or mechanical connection structures 144, which are here embodied as solder balls, are formed on the bottom main surface of both the functional inlays 108 and the support structure 104 for accomplishing a mechanical and electrical connection to a mounting base 136 (not shown in FIG. 4). According to FIG. 4, the frame-type support structure 104 just holds the functional inlays 108 together without the necessity of build-up layers. The solder balls on the frame help stabilizing the IC substrate 100.
[0175] In all embodiments, the functional inlays 108 may be connected to the support structure 104 by a connection medium, such as a glue or a resin from a laminate.
[0176] As shown as well in FIG. 4, one or more security components 134 may be embedded in one or more of the functional inlays 108. For instance, the illustrated security component 134 may be a crypto engine, an anti-tamper structure, or a clock generator protected against tampering, etc. By embedding security component 134 in an interior of the integrated circuit substrate 100, a security attack by an unauthorized entity may be made more difficult since it would require access to embedded security component 134, which is difficult without destroying IC substrate 100.
[0177] Furthermore, embedded capacitor components 132 in another functional inlay 108 may provide a power delivery function inside IC substrate 100.
[0178] FIG. 5 illustrates a cross-sectional view of an IC substrate 100 according to another exemplary embodiment of the invention.
[0179] The embodiment of FIG. 5 differs from the embodiment of FIG. 4 in particular in that, in the embodiment of FIG. 5, the functional inlays 108 have slanted (rather than vertical) sidewalls 128. In the illustrated cross-sectional view of FIG. 5, the functional inlays 108 with slanted sidewalls 128 are grouped so as to form together a rectangular structure 130. The design of FIG. 5 with functional inlays 108 having sloped sidewalls 128 may allow to use the volume within the integrated circuit body highly efficiently by allocating different functionalities only to regions where they are needed.
[0180] FIG. 6 illustrates a plan view of an IC substrate 100 according to another exemplary embodiment of the invention.
[0181] According to FIG. 6, some of the functional inlays 108 have a non-rectangular cross-section. Hence, the shape of the functional inlays 108 is not limited to regular geometric forms like squares and rectangles. In contrast to this, it is also possible to freely form the functional inlays 108 to match with their intended function.
[0182] FIG. 7 illustrates a cross-sectional view of an IC substrate 100 according to another exemplary embodiment of the invention.
[0183] The embodiment of FIG. 7 differs from the embodiment of FIG. 4 in particular in that, in the embodiment of FIG. 7, different ones of the functional inlays 108 which are placed side by side extend over different vertical spatial extensions or ranges.
[0184] The functional inlay 108 on the right-hand side of FIG. 7, for instance, extends over the entire thickness of the support structure 104 by being inserted in a through hole of the support structure 104 extending between both its opposing main surfaces. For example, said inlay 108 may provide a function which is needed over the entire vertical extension of the support structure 104.
[0185] The functional inlay 108 on the left-hand side of FIG. 7, for instance, is inserted in a blind hole formed in a bottom main surface of support structure 104 and extends over only part of the thickness of the support structure 104 from its bottom main surface into an interior of the support structure 104. For example, said inlay 108 may provide a function which is needed only in the lower portion of the support structure 104.
[0186] The functional inlay 108 in the middle of FIG. 7, for instance, is inserted in a blind hole formed in a top main surface of support structure 104 and extends over only part of the thickness of the support structure 104 from its top main surface into an interior of the support structure 104. For example, said inlay 108 may provide a function which is needed only in the upper portion of the support structure 104.
[0187] FIG. 8 to FIG. 10 illustrate cross-sectional views of functional inlays 108 for an IC substrate 100 according to exemplary embodiments of the invention.
[0188] Referring to FIG. 8, a functional inlay 108 is shown which may be embodied as laminated layer stack, for instance in form of a piece of a further IC substrate or a piece of a printed circuit board (PCB). More specifically, the functional inlay 108 may comprise a stack 160 comprising electrically conductive layer structures 162 and electrically insulating layer structures 164. The electrically conductive layer structures 162 may comprise patterned metal layers (such as patterned copper foils or patterned deposited copper layers) and vertical through connections, for example copper filled vias which may be created by drilling and plating. The electrically insulating layer structures 164 may comprise a respective resin (such as a respective epoxy resin), preferably comprising reinforcing particles therein (for instance glass spheres). For instance, the electrically insulating layer structures 164 may be made of FR4. The electrically insulating layer structures 164 may also comprise resin layers being free of glass particles.
[0189] Moreover, the functional inlay 108 according to FIG. 8 comprises embedded components, here embodied as an active component 166 and a passive component 168. For instance, active component 166 may be a DC-DC-converter chip, whereas passive component 168 may be an inductor component. Together, components 166, 168 embedded in the functional inlay 108 may provide a power conversion function, more specifically a direct current-direct current-converter function. To put it shortly, the shown configuration may provide a core-integrated DC-DC-converter.
[0190] Referring to FIG. 9, the illustrated functional inlay 108 is configured to provide a power delivery function provided by a plurality of capacitor components 132 embedded in laminated layer stack 160. Descriptively speaking, the embedded capacitor components 132 may provide a power delivery function at a highly appropriate position inside of stack 160 (in particular more appropriate than in a surface mounted manner, as in conventional approaches).
[0191] Moreover and still referring to FIG. 9, the functional inlays 108 comprise a metallic slug 166 or a pillar (preferably made of copper). The metallic slug 166 is made of highly thermally conductive material and may therefore contribute to an efficient removal of heat out of the IC substrate 100 during operation. In FIG. 9, the metallic slug 166 is totally embedded inside of the IC substrate 100. However, it is also possible that the metallic slug 166 is exposed at the top side and/or the bottom side of the IC substrate 100. This may further improve heat management. In one configuration, the metallic slug 166 may also be used for conducting electric current.
[0192] Referring to FIG. 10, a functional inlay 108 is shown which is configured to provide a power distribution function. The distributed arrangement of electrically conductive layer structures 162 may distribute electric power over an electronic device 120 in a predefined and efficient way. Moreover, also the embodiment of FIG. 10 comprises metallic slugs 166 for improving the thermal performance.
[0193] FIG. 11 illustrates a cross-sectional view of an electronic device 120 according to another exemplary embodiment of the invention.
[0194] The illustrated electronic device 120 comprises an integrated circuit substrate 100 and comprises two electronic components 102 mounted with full-surface direct physical contact on the integrated circuit substrate 100.
[0195] On a bottom side of the electronic device 120, a mounting base 136 is provided on which the IC substrate 100 is mounted.
[0196] The integrated circuit substrate 100, the at least one electronic component 102 and/or the mounting base 136 can be constructed according to any of the above described figures.
[0197] A detail 240 in FIG. 11 shows particularities of the connection surface between the integrated circuit substrate 100 and one of the electronic components 102. As shown in detail 240, the electronic device 120 is free of any material and is free of any gap between the integrated circuit substrate 100 and the electronic component 102 which are connected with each other over a continuous connection area. Thus, the integrated circuit substrate 100 may be connected with the electronic components 102 with continuous physical contact over an entire main surface of the electronic components 102.
[0198] Still referring to FIG. 11 and in particular to detail 240, the integrated circuit substrate 100 comprises in its upper portion a plurality of exposed integrated circuit substrate pads 152 being surrounded by an exposed substrate dielectric 206. For instance, each of the substrate pads 152 is made of copper material. The exposed substrate dielectric 206 may for instance be organic dielectric material, such as epoxy resin. In the connected state according to FIG. 11, exterior planar surface portions of the exposed substrate dielectric 206 and of the exposed substrate pads 152 may be coplanar and at the same vertical level. The avoidance of protrusions and depressions in the substantially flat connection surface between integrated circuit substrate 100 and electronic components 102 may ensure a reliable electric connection as well as an avoidance of cracks.
[0199] Still referring to detail 240, the illustrated electronic component 102 has exposed component pads 156 and has an exposed component dielectric 212. For instance, each of the component pads 156 is made of copper material. Advantageously, the material of the substrate pads 152 and of the component pads 156 may be the same which may promote a firm pad-pad connection and thus a good reliability of electronic device 120. The exposed component dielectric 212 may for instance be a passivation layer made of a polymer dielectric material.
[0200] In the connected state according to FIG. 11, exterior planar surface portions of the exposed component dielectric 212 and of the exposed component pads 156 may be coplanar, i.e. at the same vertical level. Furthermore, exterior planar surface portions of the exposed component pads 156 and of the exposed substrate pads 152 may be coplanar and at the same vertical level as dielectrics 206, 212. Hence, a connection area 214 between the substrate dielectric 206 and the component dielectric 212 is coplanar with a further connection area 216 between the substrate pad 152 and the component pad 156.
[0201] As shown in detail 240 as well, the integrated circuit substrate 100 is connected with the illustrated electronic component 102 so that there is a direct physical contact between the substrate pads 152 and the component pads 156. Furthermore, the connection is executed so that there is a direct physical contact between the substrate dielectric 206 and the component dielectric 212. Advantageously, no additional material (such as solder) or element (for instance an interposer) is arranged between the integrated circuit substrate 100 and the electronic components 102. This keeps the vertical dimension of electronic device 120 small so that a compact design may be achieved. Furthermore, this direct connection keeps the electric connection paths short, thereby ensuring high signal integrity and low losses as well as a strong suppression of excessive electronic device heating. Consequently, electronic device 120 may be provided with high thermal, mechanical and electrical reliability.
[0202] In the illustrated embodiment, the exposed substrate dielectric 206 can be formed by a thin dielectric film 218, which can be preferably a dielectric oxide film formed by oxidizing a dielectric surface portion of the integrated circuit substrate 100. The thin dielectric film 218 may be arranged on a thick dielectric bulk structure 222 of the integrated circuit substrate 100. By forming the exposed substrate dielectric 206 with a very smooth thin dielectric film 218, excellent adhesion properties between integrated circuit substrate 100 and the respective IC-type electronic component 102 may be achieved.
[0203] As shown, the bottom-sided pads 150 are electrically coupled with mounting base pads 154 of mounting base 136 by bottom-sided electric connections structures 144 (such as solder balls). In contrast to this, the top-sided substrate pads 152 are directly electrically coupled with the component pads 156 of the IC components 102, i.e. without top-sided electric connections structures (i.e. without solder balls or the like).
[0204] It should be noted that the term comprising does not exclude other elements or steps and the a or an does not exclude a plurality. Also, elements described in association with different embodiments may be combined.
[0205] It should also be noted that reference signs in the claims shall not be construed as limiting the scope of the claims.
[0206] Implementation of the invention is not limited to the preferred embodiments shown in the figures and described above. Instead, a multiplicity of variants is possible which use the solutions shown and the principle according to the invention even in the case of fundamentally different embodiments.
