Dynamic amplifier of large output swing

Abstract

A dynamic amplifier includes a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node; a current mirror configured to mirror the drain current into an output current to an output current; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage; a second switch configured to conditionally connect the gate node to a gate-resetting voltage; a third switch configured to conditionally connect the source node to a source-resetting voltage; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage.

Claims

1. A dynamic amplifier working in a two-phase manner including a reset phase and an amplification phase and comprising: a common-source amplifier configured to receive a gate voltage at a gate node and output a drain current to a drain node in accordance with a source voltage at a source node; a current mirror configured to mirror the drain current into an output current to an output node; a source capacitor connected to the source node; a load capacitor connected to the output node; a first switch configured to conditionally connect the gate node to an input voltage in accordance with a first logical signal; a second switch configured to conditionally connect the gate node to a gate-resetting voltage in accordance with a second logical signal; a third switch configured to conditionally connect the source node to a source-resetting voltage in accordance with a third logical signal; a fourth switch configured to conditionally connect the drain node to a drain-resetting voltage in accordance with a fourth logical signal; and a fifth switch configured to conditionally connect the output node to an output-resetting voltage in accordance with a fifth logical signal, wherein during the reset phase the first logical signal is de-asserted, while the second logical signal, the third logical signal, the fourth logical signal, and the fifth logical signal are asserted, and during the amplification phase the first logical signal is asserted, while the second logical signal, the third logical signal, the fourth logical signal, and the fifth logical signal are de-asserted.

2. The dynamic amplifier of claim 1, wherein the common-source amplifier comprises a MOS (metal-oxide semiconductor) transistor of a first type with a gate connected to the gate node, a source connected to the source node, and a drain connected to the drain node.

3. The dynamic amplifier of claim 2, wherein the current mirror comprises: a first MOS transistor of a second type with a drain and a gate connected to the drain node and a source connected to a DC (direct current) node; and a second MOS transistor of the second type with a gate connected to the drain node, a drain connected to the output node, and a source connected to the DC node.

4. The dynamic amplifier of claim 3, wherein the MOS transistor of the first type is a NMOS (n-channel metal oxide semiconductor) transistor, the first MOS transistor of the second type is a first PMOS (p-channel metal oxide semiconductor) transistor, and the second MOS transistor of the second type is a second PMOS transistor.

5. The dynamic amplifier of claim 4, wherein the DC node is a power supply node, the drain-resetting voltage is not higher than a voltage of the power supply node, and the output-resetting voltage is not higher than the voltage of the power supply node.

6. The dynamic amplifier of claim 5, wherein the gate-resetting voltage is not higher than the drain-resetting voltage by more than a threshold voltage of the NMOS transistor, and not higher than the source-resetting voltage by more than the threshold voltage of the NMOS transistor.

7. The dynamic amplifier of claim 3, wherein the MOS transistor of the first type is a PMOS (p-channel metal oxide semiconductor) transistor, the first MOS transistor of the second type is a first NMOS (n-channel metal oxide semiconductor) transistor, and the second MOS transistor of the second type is a second NMOS transistor.

8. The dynamic amplifier of claim 7, wherein the DC node is a ground node, the drain-resetting voltage is not lower than a voltage of the ground node, and the output-resetting voltage is not lower than the voltage of the ground node.

9. The dynamic amplifier of claim 8, wherein the gate-resetting voltage is not lower than the drain-resetting voltage by more than a threshold voltage of the PMOS transistor, and not lower than the source-resetting voltage by more than the threshold voltage of the PMOS transistor.

10. The dynamic amplifier of claim 1 further comprises a feedback capacitor inserted between the drain node and the output node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic diagram of a prior art dynamic amplifier.

(2) FIG. 2 shows a schematic diagram of a dynamic amplifier in accordance with an embodiment of the present disclosure.

DETAILED DESCRIPTION OF THIS DISCLOSURE

(3) The present disclosure is directed to dynamic amplifier. While the specification describes several example embodiments of the disclosure considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the disclosure.

(4) Persons of ordinary skill in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “amplifier,” “gain,” “bias,” “capacitor,” “common-source amplifier,” “current mirror,” “load,” “parallel connection,” “circuit node,” “ground,” “DC (direct current),” “power supply,” “MOS (metal oxide semiconductor) transistor,” “CMOS (complementary metal oxide semiconductor) process technology,” “NMOS (n-channel metal oxide semiconductor) transistor,” and “PMOS (p-channel metal oxide semiconductor) transistor.” Terms and basic concepts like these, when used in a context of microelectronics, are apparent to those of ordinary skill in the art and thus will not be explained in detail here.

(5) Those of ordinary skills in the art understand units such as fF (femto-Farad), nm (nanometer), and μm (micron) without a need of explanations.

(6) Those of ordinary skills in the art can read schematics of a circuit comprising electronic components such as inductors, capacitors, resistors, NMOS transistors, PMOS transistors, and so on, and do not need a verbose description about how one component connects with another in the schematics. Those of ordinary skill in the art can also recognize a ground symbol, a capacitor symbol, an inductor symbol, a resistor symbol, and symbols of PMOS transistor and NMOS transistor, and identify the “source terminal,” the “gate terminal,” and the “drain terminal” thereof. Pertaining to a MOS transistor, for brevity, hereafter, “source terminal” is simply referred to as “source,” “gate terminal” is simply referred to “gate,” and “drain terminal” is simply referred to “drain.”

(7) A circuit is a collection of a transistor, a capacitor, a resistor, and/or other electronic devices inter-connected in a certain manner to embody a certain function.

(8) A power supply node is a circuit node of a substantially stationary voltage, and so is a ground node. Power supply node and ground node are both DC (direct current) nodes but differ in voltage level; that is, a voltage level of a power supply node is higher than a voltage level of a ground node. Following a convention widely used in the literature, in this disclosure, in a circuit, “V.sub.DD” denotes a power supply node and “V.sub.SS” denotes a ground node. If there are more than one power supply node in a circuit, “V.sub.DD1” denotes a first power supply node and “V.sub.DD2” denotes a second power supply node. If there are more than one ground node in a circuit, “V.sub.SS1” denotes a first ground supply node and “V.sub.SS2” denotes a second ground node.

(9) A MOS transistor, PMOS or NMOS, has a threshold voltage. A NMOS transistor is turned on when its gate-to-source voltage is higher than its threshold voltage and turned off otherwise. In some literature, a PMOS transistor is turned on when its gate-to-source voltage is lower than its threshold voltage and turned off otherwise; this is based on a convention that a threshold voltage of a PMOS transistor is negative. In this present disclosure, we use a convention that a threshold voltage of a PMOS transistor is positive (i.e., we refer to the absolute value that is always positive), therefore we say, a PMOS transistor is turned on when its source-to-gate voltage is higher its threshold voltage and turned off otherwise.

(10) In this disclosure, a “circuit node” is frequently simply stated as a “node” for short, when what it means is clear from a context.

(11) A signal is a voltage of a variable level that carries a certain information and can vary with time. A level of the signal at a moment represents a state of the signal at that moment. In this present disclosure, “signal” and “voltage signal” refer to the same thing and thus are interchangeable.

(12) A logical signal is a voltage signal of two states: a low state and a high state; the logical signal is in the high state when its voltage level is above a trip point and in the low state otherwise. The low state is also referred to as a “0” state, while the high stage is also referred to as a “1” state. Regarding a logical signal Q, the expression, “Q is high” or “Q is low,” means that “Q is in the high state” or “Q is in the low state.” Likewise, the expression “Q is 1” or “Q is 0,” means that “Q is in the 1 state” or “Q is in the 0 state.”

(13) A first logical signal may not necessarily have the same trip point as a second logical signal.

(14) A first logical signal is said to be a logical inversion of a second logical signal, if the first logical signal and the second logical signal are always in opposite states. That is, when the first logical signal is low, the second logical signal is high; when the first logical signal is high, the second logical signal is low. When a first logical signal is said to be a logical inversion of a second logical signal, the first logical signal and the second logical signal are said to be complementary to each other.

(15) A logical signal is often used as a control signal to enable or disable a function of a circuit. When the logical signal is in a logical state that enables the function of the circuit, the logical signal is said to be “asserted”; otherwise, the logical signal is said to be “de-asserted.” When a logical signal is “asserted” when it is high, it is said to be “active high”; when a logical signal is “asserted” when it is low, it is said to be “active low.”

(16) Switches are extensively used in the present disclosure. A switch is a device configured to conditionally connect a first node to a second node in accordance with a control by a logical signal; said switch is turned on and behaves like a short circuit when said logical signal is asserted; and said switch is turned off and behaves like an open circuit when said logical control signal is de-asserted.

(17) A switch can be embodied by a NMOS transistor with a gate voltage controlled by an active high logical signal, while a first node and a second node connect to a source and a gate of the NMOS transistor, respectively; in this case, a trip point of the active high logical signal is equal to a source voltage at the first node plus a threshold voltage of the NMOS transistor.

(18) Alternatively, a switch can be embodied by a PMOS transistor with a gate voltage controlled by an active low logical signal, while a first node and a second node connect to a source and a gate of the PMOS transistor, respectively; in this case, a trip point of the active low logical signal is equal to a source voltage at the first node minus a threshold voltage (which is a positive voltage per the convention used in the present disclosure) of the PMOS transistor.

(19) Yet alternatively, a switch can be embodied by using a parallel connection of a NMOS transistor with a gate voltage controlled by an active high logical signal and a PMOS transistor with a gate voltage controlled by an active low logical signal, wherein the active high logical signal and active low logical signal are complementary. This is known as “transmission gate” and well understood by those of ordinary skill in the art and thus not described in detail here.

(20) As shown in FIG. 1, a dynamic amplifier 200 in accordance with an embodiment of the present disclosure comprise: a common-source amplifier 210 comprising a NMOS transistor MN1 configured to receive a gate voltage V.sub.g at a gate node NG and output a drain current I.sub.d to a drain node ND in accordance with a source voltage V.sub.s at a source node NS; a source capacitor C.sub.S connected to the source node NS and configured to hold the source voltage V.sub.s; a current mirror 220 comprising a first PMOS transistor MP1 and a second PMOS transistor MP2 configured to mirror the drain current I.sub.d into an output current I.sub.o to an output node NO; a load capacitor C.sub.L connected to the output node NO and configured to hold an output voltage V.sub.o; a first switch SW1 configured to conditionally connect the gate node NG to an input voltage V.sub.i in accordance with a first logical signal C1; a second switch SW2 configured to conditionally connect the gate node NG to a gate-resetting voltage V.sub.g0 in accordance with a second logical signal C2; a third switch SW3 configured to conditionally connect the source node NS to a source-resetting voltage V.sub.s0 in accordance with a third logical signal C3; a fourth switch SW4 configured to conditionally connect the drain node ND to a drain-resetting voltage V.sub.d0 in accordance with a fourth logical signal C4; and a fifth switch SW5 configured to conditionally connect the output node NO to an output resetting voltage V.sub.o0 in accordance with a fifth logical signal C5. Dynamic amplifier 200 works in a two-phase manner including a reset phase and an amplification phase. During the reset phase, C2, C3, C4, and C5 are asserted (and consequently SW2, SW3, SW4, and SW5 are turned on and behave like a short circuit), while C1 is de-asserted (and consequently SW1 is turned off and behaves like an open circuit); as a result, NMOS transistor MN1 is shut off, the gate voltage V.sub.g is equal to V.sub.g0 and the source voltage V.sub.s is equal to V.sub.s0, the drain voltage V.sub.d is equal to V.sub.d0, and the output voltage V.sub.o is equal to V.sub.o0.

(21) During the amplification phase, C2, C3, C4, and C5 are de-asserted (and consequently SW2, SW3, SW4, and SW5 are turned off and behave like an open circuit), while C1 is asserted (and consequently SW1 is turned on and behaves like a short circuit); the gate voltage V.sub.g is tied to the input voltage V.sub.i; a source current I.sub.s of NMOS transistor MN1 charges the source capacitor C.sub.S and pulls up the source voltage V.sub.s; the drain current I.sub.d is mirrored to the output current I.sub.o to charge the load capacitor C.sub.L and pulls up the output voltage V.sub.o. A higher input voltage V.sub.i will cause NMOS transistor MN1 to have a larger gate-to-source voltage and lead to a larger drain current I.sub.d and consequently a larger output current I.sub.o and a higher output voltage V.sub.o.

(22) In an embodiment, V.sub.g0, V.sub.s0, V.sub.d0, and V.sub.o0 are chosen to meet the following constraints:
V.sub.d0≤V.sub.DD  (4)
V.sub.g0≤V.sub.d0+V.sub.th1  (5)
V.sub.g0≤V.sub.s0+V.sub.th1  (6)
V.sub.o0≤V.sub.DD  (7)

(23) Here, V.sub.th1 is a threshold voltage of NMOS transistor MN1.

(24) The constraints of Equations (4), (5), and (6) ensure that NMOS transistor MN1 is shut off during the reset phase, while the constraints of Equation (7) ensures that the current mirror can fulfill the current-mirroring function during the amplification phase.

(25) At the end of the amplification phase, the gate-to-source voltage of NMOS transistor NM1 reaches its threshold voltage V.sub.th1, and can be expressed as:

(26) $\begin{array}{cc}{V}_s=V_i-V_{th1}& \left(8\right)\end{array}$$\begin{array}{cc}{V}_o=V_{\mathrm{o0}}+\left(V_s-V_{s0}\right).Math.\frac{c_s}{c_L}.Math.\beta =V_{\mathrm{o0}}-\left(V_{th1}+V_{s0}\right).Math.\frac{c_s}{c_L}.Math.\beta +V_i.Math.\frac{c_s}{c_L}.Math.\beta & \left(9\right)\end{array}$

(27) Here, β is a current-mirroring factor of the current mirror 220 and can be expressed by:

(28) $\begin{array}{cc}\beta =\frac{W_2}{L_2}.Math.\frac{L_1}{W_1}& \left(10\right)\end{array}$

(29) Here, W.sub.1 and L.sub.1 are a width and a length of PMOS transistor MP1, and W.sub.2 and L.sub.2 are a width and a length of PMOS transistor MP2.

(30) Equation (9) is based on charge conservation along with current mirroring, that is, an increase of charge on C.sub.L is equal to an increase of charge on C.sub.S times the current mirroring factor β of the current mirror 220.

(31) A gain, say G.sub.200, of dynamic amplifier 200 is defined as an incremental change of V.sub.o divided by an incremental change of v.sub.i and is expressed as:

(32) $\begin{array}{cc}{G}_{200}\equiv \frac{d{V}_o}{d{V}_i}=\beta .Math.\frac{c_s}{c_L}& \left(11\right)\end{array}$

(33) Dynamic amplifier 200 has a few advantages. First, it can have a large output swing thanks to using the current mirror 220, which effectively prevents the output voltage V.sub.o from being limited by the source voltage V.sub.s. The output swing is limited only be the PMOS transistor MP2, which can charge the output voltage V.sub.o to nearly V.sub.DD and thus allow V.sub.o to have a large swing. Second, a gain of dynamic amplifier is determined by a ratio between the source capacitor C.sub.S and the load capacitor C.sub.L times the current-mirroring factor β. So, a higher gain can be achieved, and a circuit designer can have a higher degree of freedom in optimizing a design.

(34) By way of example but not limitation, in an embodiment: dynamic amplifier 200 is fabricated on a silicon substrate using a 12 nm CMOS process technology; V.sub.DD is 0.8V; V.sub.SS1 is 0V; V.sub.SS2 is 0V; V.sub.g0 is 0V; V.sub.s0 is 0V; V.sub.d0 is 0.8V; C.sub.1 is 200 fF; C.sub.2 is 200 fF; W/L (which stands for width/length) of NMOS transistor MN1 is 2 μm/16 nm; W/L of PMOS transistor MP1 is 2 μm/16 nm; and W/L of PMOS transistor MP2 is 6 μm/16 nm.

(35) In a further embodiment, dynamic amplifier 200 further comprises a feedback capacitor C.sub.F inserted between the drain node ND and the output node NO. A purpose of the feedback capacitor C.sub.F is to reduce a nonlinearity of the dynamic amplifier 200 by means of negative feedback, as a nonlinear error of V.sub.o can be fed back to the drain node ND to cause the PMOS transistor MP2 to adjust the output current I.sub.o to correct the nonlinear error. By way of example but not limitation, in an embodiment, C.sub.F is 25 fF.

(36) It is known in the prior art that, for a given first circuit, if every NMOS transistor is replaced with a PMOS transition, every PMOS transistor is replaced with a NMOS transistor, every power supply node is replaced with a ground node, and every ground node is replaced with a power supply node, then the resultant second circuit will be functionally equivalent to the originally given first circuit. Having said that, in an alternative embodiment not shown in figure but clear to those of ordinary skill in the art, dynamic amplifier 200 can be modified by applying the following changes: NMOS transistor MN1 is replaced with a PMOS transistor MP1′ (with a threshold voltage V.sub.th1′ in absolute value); PMOS transistor MP1 is replaced with a first NMOS transistor MN1′; PMOS transistor MP2 is replaced with a second NMOS transistor MN2′; power supply node “V.sub.DD” is changed to a ground node “V.sub.SS”; the first ground node “V.sub.SS1” is changed to a first power supply node “V.sub.DD1”; the second ground node is changed to a second power supply node “V.sub.DD2”; and V.sub.g0, V.sub.s0, V.sub.d0, and V.sub.o0 are chosen to meet the following constraints:
V.sub.d0≥V.sub.SS  (12)
V.sub.g0≥V.sub.d0−V.sub.th1′  (13)
V.sub.g0≥V.sub.s0−V.sub.th1′  (14)
V.sub.o0≥V.sub.SS  (15)

(37) Equations (12), (13), and (14) ensures that PMOS transistor MP1′ is shut off during the reset phase, while Equation (15) ensures that the current mirror embodied by the first NMOS transistor MN1′ and the second NMOS transistor MN2′ can fulfill the current-mirroring function during the amplification phase.

(38) This alternative embodiment is a “flipped” version of dynamic amplifier 200 and is functionally equivalent. In the appended claims, one of NMOS transistor and PMOS transistor is referred to as MOS transistor of a first type, while the other is referred to as MOS transistor of a second type. In dynamic amplifier 200, MOS transistor of the first type and MOS transistor of the second type refer to NMOS transistor and PMOS transistor, respectively. In the alternative embodiment, MOS transistor of the first type and MOS transistor of the second type refer to PMOS transistor and NMOS transistor, respectively.

(39) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the disclosure. Accordingly, the above disclosure should not be construed as limited only by the metes and bounds of the appended claims.