Abstract
The present invention proposes a driving circuit and a shift register. The driving circuit includes shift register circuits disposed in cascade. Each of shift register circuits includes a clock control transmittance circuit and a latch circuit. The clock control transmittance circuit is triggered by a first clock pulse. A driving pulse of a Q node at previous two stages is transmitted to the latch circuit and latched by the latch circuit. Further, the latch circuit is triggered by a second clock pulse, and then a gate driving pulse and a driving pulse of the Q node is output. So the present invention can be used in the CMOS process owing to the features of low consumption and wide noise margin.
Claims
1. A driving circuit, comprising a plurality of shift register circuits disposed in cascade, each of the plurality of shift register circuits comprising a clock control transmittance circuit and a latch circuit, the clock control transmittance circuit being triggered by a first clock pulse, a driving pulse of a Q node at previous two stages being transmitted to the latch circuit and latched by the latch circuit, further, the latch circuit being triggered by a second clock pulse, and then a gate driving pulse and a driving pulse of the Q node being output, and the clock control transmittance circuit and the latch circuit being rising edge-triggered; wherein the latch circuit at least comprises a first transmission gate, a second transmission gate, a first inverter, a second inverter, and an NOR gate; a first controlling terminal of the first transmission gate and a second controlling terminal of the second transmission gate are connected to an output terminal of the clock control transmittance circuit; an input terminal of the first transmission gate is connected to a Q node at the previous two stages, a second controlling terminal of the first transmission gate and a first controlling terminal of the second transmission gate both are connected to the first clock pulse; an output terminal of the first transmission gate is connected to an input terminal of the second transmission gate and an input terminal of the first inverter; an output terminal of the first inverter is connected to an input terminal of the second inverter; an output terminal of the second inverter and an output terminal of the second transmission gate both are connected to a first input terminal of the NOR gate; and a second input terminal of the NOR gate is connected to the second clock pulse.
2. The driving circuit of claim 1, wherein the clock control transmittance circuit inverts the first clock pulse when the clock control transmittance circuit transmits the first clock pulse.
3. The driving circuit of claim 1, wherein the output terminal of the second inverter outputs a driving pulse of the Q node.
4. The driving circuit of claim 1, wherein the latch circuit further comprises a multi-stage inverting circuit which an output terminal of the NOR gate is connected to.
5. The driving circuit of claim 4, wherein the multi-stage inverting circuit comprises three inverters.
6. The driving circuit of claim 1, wherein the input terminal of the first transmission gate is connected to a short-term variability (STV) pulse in the shift register circuit at the first stage and the shift register circuit at the second stage.
7. A driving circuit, comprising a plurality of shift register circuits disposed in cascade, each of the plurality of shift register circuits comprising a clock control transmittance circuit and a latch circuit, the clock control transmittance circuit being triggered by a first clock pulse, a driving pulse of a Q node at previous two stages being transmitted to the latch circuit and latched by the latch circuit, further, the latch circuit being triggered by a second clock pulse, and then a gate driving pulse and a driving pulse of the Q node being output, wherein the latch circuit at least comprises a first transmission gate, a second transmission gate, a first inverter, a second inverter, and an NOR gate; a first controlling terminal of the first transmission gate and a second controlling terminal of the second transmission gate are connected to an output terminal of the clock control transmittance circuit; an input terminal of the first transmission gate is connected to a Q node at the previous two stages, a second controlling terminal of the first transmission gate and a first controlling terminal of the second transmission gate both are connected to the first clock pulse; an output terminal of the first transmission gate is connected to an input terminal of the second transmission gate and an input terminal of the first inverter; an output terminal of the first inverter is connected to an input terminal of the second inverter; an output terminal of the second inverter and an output terminal of the second transmission gate both are connected to a first input terminal of the NOR gate; and a second input terminal of the NOR gate is connected to the second clock pulse.
8. The driving circuit of claim 7, wherein the clock control transmittance circuit and the latch circuit are rising edge-triggered.
9. The driving circuit of claim 7, wherein the clock control transmittance circuit inverts the first clock pulse when the clock control transmittance circuit transmits the first clock pulse.
10. The driving circuit of claim 7, wherein the output terminal of the second inverter outputs a driving pulse of the Q node.
11. The driving circuit of claim 7, wherein the latch circuit further comprises a multi-stage inverting circuit which an output terminal of the NOR gate is connected to.
12. The driving circuit of claim 11, wherein the multi-stage inverting circuit comprises three inverters.
13. The driving circuit of claim 7, wherein the input terminal of the first transmission gate is connected to a short-term variability (STV) pulse in the shift register circuit at the first stage and the shift register circuit at the second stage.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
(1) For better understanding embodiments of the present invention, the following detailed description taken in conjunction with the accompanying drawings is provided. Apparently, the accompanying drawings are merely for some of the embodiments of the present invention. Any ordinarily skilled person in the technical field of the present invention could still obtain other accompanying drawings without use laborious invention based on the present accompanying drawings.
(2) FIG. 1 shows a block diagram of a driving circuit according to a preferred embodiment of the present invention.
(3) FIG. 2 shows a circuit diagram of a shift register circuit shown in FIG. 1.
(4) FIG. 3 shows a circuit diagram of a first stage shift register circuit shown in FIG. 1.
(5) FIG. 4 shows a circuit diagram of a second stage shift register circuit shown in FIG. 1.
(6) FIG. 5 shows a timing diagram of ideal waveforms applied in the first and second stage shift register circuits shown in FIG. 1.
(7) FIG. 6 shows a circuit diagram of an mth stage shift register circuit shown in FIG. 1.
(8) FIG. 7 shows a circuit diagram of an (m+1)th stage shift register circuit shown in FIG. 1.
(9) FIG. 8 shows a circuit diagram of an (m+2)th stage shift register circuit shown in FIG. 1.
(10) FIG. 9 shows a circuit diagram of an (m+3)th stage shift register circuit shown in FIG. 1.
(11) FIG. 10 shows a timing diagram of waveforms applied in the driving circuits according to a preferred embodiment of the present invention.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
(12) The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
(13) Please refer to FIG. 1. FIG. 1 is a schematic diagram of a driving circuit 1 according to one embodiment of the present invention. The driving circuit 1 comprises a plurality of shift register circuits 10 disposed in cascade. Each of the plurality of shift register circuits 10 comprises a clock control transmittance circuit 11 and an NOR gate latch circuit 12. The clock control transmittance circuit 11 is triggered by a first clock pulse. A driving pulse Q.sub.n2 of a Q node at previous two stages is transmitted to the NOR gate latch circuit 12 and is latched by the NOR gate latch circuit 12. Further, the NOR gate latch circuit 12 is triggered by a second clock pulse, and then a driving pulse is output. The clock control transmittance circuit 11 inverts the first clock pulse when transmitting the first clock pulse. Also, the clock control transmittance circuit 11 and the NOR gate latch circuit 12 are rising edge-triggered. In this invention, the clock control transmittance circuit 11 controls the transmittance of signals, and the NOR gate latch circuit 12 latches the signals, so the present invention applies to the CMOS process owing to the features of low consumption and wide noise margin.
(14) Preferably, the clock control transmittance circuit 11 is an inverter. As FIG. 2 shows, the NOR gate latch circuit 12 at least comprises a first transmission gate 121, a second transmission gate 122, a first inverter 123, a second inverter 124, an NOR gate 125, and a multi-stage inverting circuit 126. A first controlling terminal of the first transmission gate 121 and a second controlling terminal of the second transmission gate 122 are connected to an output terminal of the clock control transmittance circuit 11. An input terminal of the first transmission gate 121 is connected to a Q node Q.sub.n2 at previous two stages. A second controlling terminal of the first transmission gate 121 and a first controlling terminal of the second transmission gate 122 are connected to a first clock pulse CK1. An output terminal of the first transmission gate 121 is connected to an input terminal of the second transmission gate 122 and an input terminal of the first inverter 123. An output terminal of the first inverter 123 is connected to an input terminal of the second inverter 124. An output terminal of the second inverter 124 and an output terminal of the second transmission gate 122 both are connected to a first input terminal of the NOR gate 125. A second input terminal of the NOR gate 125 is connected to a second clock pulse CK3. The multi-stage inverting circuit 126 is connected to an output terminal of the NOR gate 125 for improving the driving capacity of the driving circuit 1. Preferably, the multi-stage inverting circuit 126 comprises three inverters connected in series. The output terminal of the second inverter 124 outputs a driving pulse Q.sub.n of the Q node. An output terminal of the multi-stage inverting circuit 126 outputs a driving pulse G.sub.n. The n in Q.sub.n and G.sub.n is defined as an integral equal to or larger than one.
(15) The driving circuit 1 comprises a shift register circuit 10 at an onset stage and a shift register circuit 10 at an ordinary stage. The shift register circuit 10 at an onset stage comprises a shift register circuit 10 at a first stage and a shift register circuit 10 at a second stage. As FIG. 3 shows, the first clock pulse is the clock pulse CK1, the second clock pulse is the clock pulse CK3, the input terminal of the first transmission gate 121 is connected to a short-term variability (STV) pulse, the output terminal of the second inverter 124 outputs a driving pulse Q.sub.1 of the Q node at the first stage, and the output terminal of the multi-stage inverting circuit 126 outputs a driving pulse G.sub.1 at the first stage in the shift register circuit 10 at the first stage. As FIG. 4 shows, the first clock pulse is the clock pulse CK2, the second clock pulse is the clock pulse CK4, the input terminal of the first transmission gate 121 is connected to the STV pulse, the output terminal of the second inverter 124 outputs a driving pulse Q.sub.2 of the Q node at the second stage, and the output terminal of the multi-stage inverting circuit 126 outputs a driving pulse G.sub.2 at the second stage in the shift register circuit 10 at the second stage. Preferably, the STV pulse is an onset controlling signal.
(16) FIG. 5 is a theoretical timing diagram of the STV pulse and the clock pulses CK1, CK2, CK3, and CK4. The vertical coordinate defines voltage, and the horizontal coordinate defines time. In the shift register circuit 10 at the first stage, the clock control transmittance circuit 11 triggers the first transmission gate 121 to conduct and the second transmission gate 122 to disconnect when the clock pulse CK1 is at rising edge. The first transmission gate 121 transmits the STV pulse to the first inverter 123 and then to the driving pulse Q.sub.1 of the Q node at the first stage through the second inverter 124. The STV pulse is at a high electric level. The driving pulse Q.sub.1 of the Q node is also at a high electric level. The clock pulse CK3 triggers the NOR gate 125 of the driving circuit 1 when the clock pulse CK3 is at rising edge. The driving pulse Q.sub.1 of the Q node is transmitted to the driving pulse G.sub.1 at the first stage through the NOR gate 125 and the multi-stage inverting circuit 126. The driving pulse G.sub.1 is also at a high electric level. In the shift register circuit 10 at the second stage, the clock control transmittance circuit 11 triggers the first transmission gate 121 to conduct and the second transmission gate 122 to disconnect when the clock pulse CK2 is at rising edge. The first transmission gate 121 transmits the STV pulse to the first inverter 123 and then to the driving pulse Q.sub.2 of the Q node at the second stage through the second inverter 124. The STV pulse is at a high electric level. The driving pulse Q.sub.2 of the Q node is also at a high electric level. The clock pulse CK4 triggers the NOR gate 125 of the driving circuit 1 when the clock pulse CK4 is at rising edge. The driving pulse Q.sub.2 of the Q node is transmitted to the driving pulse G.sub.2 at the second stage through the NOR gate 125 and the multi-stage inverting circuit 126. The driving pulse G.sub.2 is also at a high electric level.
(17) The shift register circuit 10 at the ordinary stage is the shift register circuit 10 at the third stage or the shift register circuit 10 at higher than the third stage. As FIG. 6 shows, the first clock pulse is the clock pulse CK1 in the shift register circuit 10 at the mth stage where m means n larger than or equal to three. Also, the second clock pulse is the clock pulse CK3. The input terminal of the first transmission gate 121 is connected to the Q node Q.sub.m2 at the previous two stages. The output terminal of the second inverter 124 outputs the driving pulse Q.sub.m of the Q node at the mth stage. The output terminal of the multi-stage inverting circuit 126 outputs the driving pulse G.sub.m at the mth stage.
(18) As FIG. 7 shows, the first clock pulse is the clock pulse CK2 in the shift register circuit 10 at the m+1 stage. Also, the second clock pulse is the clock pulse CK4. The input terminal of the first transmission gate 121 is connected to the Q node Q.sub.m1 at the previous two stages. The output terminal of the second inverter 124 outputs the driving pulse Q.sub.m+1 of the Q node at the m+1th stage. The output terminal of the multi-stage inverting circuit 126 outputs the driving pulse G.sub.m+1 at the m+1th stage.
(19) As FIG. 8 shows, the first clock pulse is the clock pulse CK3 in the shift register circuit 10 at the m+2 stage. Also, the second clock pulse is the clock pulse CK1. The input terminal of the first transmission gate 121 is connected to the Q node Q.sub.m at the previous two stages. The output terminal of the second inverter 124 outputs the driving pulse Q.sub.m+2 of the Q node at the m+2th stage. The output terminal of the multi-stage inverting circuit 126 outputs the driving pulse G.sub.m+2 at the m+2th stage.
(20) As FIG. 9 shows, the first clock pulse is the clock pulse CK4 in the shift register circuit 10 at the m+3 stage. Also, the second clock pulse is the clock pulse CK2. The input terminal of the first transmission gate 121 is connected to the Q node Q.sub.m+1 at the previous two stages. The output terminal of the second inverter 124 outputs the driving pulse Q.sub.m+3 of the Q node at the m+3th stage. The output terminal of the multi-stage inverting circuit 126 outputs the driving pulse G.sub.m+3 at the m+3th stage.
(21) FIG. 10 is a simulated timing diagram of the driving circuit according to this embodiment of the present invention. The vertical coordinate defines voltage, and the horizontal coordinate defines time. FIG. 10 shows that the simulation from the shift register circuit 10 at the first stage to the STV impulse of the shift register circuit 10 at the fifth stage, the simulation of the clock pulses CK1, CK2, CK3, and CK4, and the simulation of the driving pulses of the Q node Q.sub.1, Q.sub.2, Q.sub.3, Q.sub.4, and Q.sub.5, and the simulation of the driving pulses G.sub.1, G.sub.2, G.sub.3, G.sub.4, and G.sub.5. It can be inferred from FIG. 10 that the simulated timing of the driving circuit of the NOR gate latch is the same as the theoretical timing shown in FIG. 5.
(22) The present invention further proposes a shift register circuit with an NOR gate latch 10. The shift register circuit with an NOR gate latch 10 comprises a clock control transmittance circuit 11 and an NOR gate latch circuit 12. As FIG. 2 shows, the NOR gate latch circuit 12 at least comprises a first transmission gate 121, a second transmission gate 122, a first inverter 123, a second inverter 124, an NOR gate 125, and a multi-stage inverting circuit 126. A first controlling terminal of the first inverter 123 and a second controlling terminal of the second transmission gate 122 are connected to an output terminal of the clock control transmittance circuit 11. An input terminal of the first transmission gate 121 is connected to a Q node Q.sub.n2 at previous two stages. A second controlling terminal of the first transmission gate 121 and a first controlling terminal of the second transmission gate 122 both are connected to a first clock pulse. An output terminal of the first transmission gate 121 is connected to an input terminal of the second transmission gate 122 and an input terminal of the first inverter 123. An output terminal of the first inverter 123 is connected to an input terminal of the second inverter 124. An output terminal of the second inverter 124 and an output terminal of the second transmission gate 122 both are connected to a first input terminal of the NOR gate 125. A second input terminal of the NOR gate 125 is connected to a second clock pulse. The multi-stage inverting circuit 126 is connected to an output terminal of the NOR gate 125 for improving the driving capacity of the driving circuit 1. Preferably, the multi-stage inverting circuit 126 comprises three inverters connected in series. The output terminal of the second inverter 124 outputs a driving pulse Q.sub.n of the Q node. An output terminal of the multi-stage inverting circuit 126 outputs a driving pulse G.sub.n. The n in Q.sub.n and G.sub.n is defined as an integral equal to or larger than one.
(23) Preferably, the driving pulse introduced by the present invention is a gate driving pulse.
(24) The present disclosure is described in detail in accordance with the above contents with the specific preferred examples. However, this present disclosure is not limited to the specific examples. For the ordinary technical personnel of the technical field of the present disclosure, on the premise of keeping the conception of the present disclosure, the technical personnel can also make simple deductions or replacements, and all of which should be considered to belong to the protection scope of the present disclosure.
