Multistage noise shaping sigma-delta modulator

Abstract

A sigma-delta modulator including at least first and second sub-modulators, each including an analog integration circuit, the analog integration circuit of the first sub-modulator having an output node connected to an input node of the analog integration circuit of the second sub-modulator, the modulator further comprising a coupling capacitor having a first electrode connected to an output node of the analog integration circuit of the second sub-modulator, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch.

Claims

1. A sigma-delta modulator comprising at least first and second analog integration circuits each comprising at least one analog integrator, each analog integrator comprising an operational amplifier having its input coupled to its output by an integration capacitor, the first analog integration circuit having an output node connected to an input node of the second analog integration circuit, the modulator further comprising a coupling capacitor different from said integration capacitors, the coupling capacitor having a first electrode connected to an output node of the second analog integration circuit, and a comparator having its input coupled to the first electrode of the coupling capacitor by a first switch and to a second electrode of the coupling capacitor by a second switch, the modulator being capable of implementing a phase of conversion of an analog input signal into an output bit train, the conversion phase comprising a plurality of operating cycles, each divided into first and second successive phases, wherein, for each cycle of the conversion phase: during the first phase of the cycle: the first analog integration circuit integrates a signal representative of the difference between the analog input signal and a first feedback signal, and supplies an output signal S1 on its output node; the second analog integration circuit only integrates signal S1; the first and second switches are respectively turned off and on, so that only signal S1 is transmitted to the input of the comparator via the coupling capacitor; and a binary value Y1 corresponding to 1-bit quantized signal S1 is read from the output of the comparator, and, during the second phase of the cycle: the second analog integration circuit integrates a signal representative of the difference between a second feedback signal and binary value Y1; the first and second switches are respectively turned on and off, so that the output signal of the second analog integration circuit is applied to the input of the comparator; and a binary value Y2 corresponding to the 1-bit quantized output signal of the second analog integration circuit is read from the output of the comparator, values Y1 and Y2 being then combined into one output bit of the modulator.

2. The modulator of claim 1, wherein the second electrode of the coupling capacitor is further coupled to a node of application of a reference potential by a third switch, the third switch being off during the first phase of each cycle of the conversion phase and on during the second phase of each cycle of the conversion phase.

3. The modulator of claim 1, wherein the first analog integration circuit comprises at least two cascaded analog integrators, and at least one circuit achieving a weighted sum of the output values of said integrators, the output of the summing circuit forming the output of said analog integration circuit.

4. The modulator of claim 1, wherein the analog integration circuit of the second sub-modulator comprises a single analog integrator having its input and its output respectively connected to the input and to the output of said analog integration circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1, previously described, schematically shows an example of a sigma-delta modulator of order 1;

(2) FIG. 2 schematically shows an example of a sigma-delta modulator of order 4;

(3) FIG. 3 schematically shows in the form of functional blocks an example of a multistage noise shaping sigma-delta modulator;

(4) FIG. 4 is a detailed electric diagram of an example of implementation of the sigma-delta modulator of FIG. 3; and

(5) FIG. 5 is a detailed electric diagram illustrating an embodiment of a multistage noise shaping sigma-delta modulator.

DETAILED DESCRIPTION OF THE PRESENT EMBODIMENTS

(6) The same elements have been designated with the same reference numerals in the different drawings. For clarity, only those elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the details of the forming of the digital filters of the described sigma-delta converters have not been shown, the forming of such filters being within the abilities of those skilled in the art on reading of the present description. In the present description, term connected is used to designate a direct electric connection, with no intermediate electronic component, for example, by means of one or a plurality of conductive tracks or conductive wires, and term coupled or term linked is used to designate an electric connection which may be direct (then meaning connected) or indirect (that is, via one or a plurality of intermediate components).

(7) FIG. 2 schematically illustrates in the form of blocks an example of a sigma-delta modulator of order 4.

(8) The sigma-delta modulator of FIG. 2 differs from the sigma-delta modulator of FIG. 1 essentially by the architecture of its analog integration circuit 101. In the example of FIG. 2, analog integration circuit 101 comprises a subtractor 107, four cascaded analog integrators Ia.sub.1, Ia.sub.2, Ia.sub.3 and Ia.sub.4, and a summing circuit 109 (). Each analog integrator comprises an input and an output, and for example has a z.sup.1/(1z.sup.1) transfer function, that is, for each cycle, the integrated signal, or output signal of the integrator, is incremented by the value of the signal applied at the integrator input. In this example, subtractor 107 receives, on its positive input, input signal Vin(k) weighted by a coefficient b.sub.1 and, on its negative input, feedback signal BS(k1) weighted by a coefficient a.sub.1. Integrator Ia.sub.1 receives on its input the output signal of subtractor 107, that is, a signal equal to difference b1*Vin(k)a1*BS(k1). Integrator Ia.sub.2 receives on its input a signal equal to the output signal of integrator Ia.sub.1 weighted by a coefficient c.sub.1. Integrator Ia.sub.3 receives on its input a signal equal to the output signal of integrator Ia.sub.2 weighted by a coefficient c.sub.2. Integrator Ia.sub.4 receives on its input a signal equal to the output signal of integrator Ia.sub.3 weighted by a coefficient c.sub.3. Summing circuit 109 adds input signal Vin(k) weighted by a coefficient b.sub.5 and the output signals of integrators Ia.sub.1, Ia.sub.2, Ia.sub.3, and Ia.sub.4, respectively weighted by coefficients c.sub.7, c.sub.6, c.sub.4, and c.sub.4. The output of summing circuit 109 is connected to output terminal A3 of circuit 101.

(9) In this example, it is considered that input signal Vin and output signal BS of the modulator are normalized, that is, value 0 of binary signal BS corresponds to a voltage level equal to the smallest value that analog signal Vin can take, and value 1 of signal BS corresponds to a voltage level equal to the greater value that signal Vin can take. Thus, the feedback loop of the modulator is a simple conductive track coupling terminal A2 to terminal A4, and the feedback signal directly is signal BS. In the case where binary output signal BS is not at the same scale as input signal Vin, the feedback loop may comprise, as in the example of FIG. 1, a 1-bit digital-to-analog converter having its input coupled to terminal A2 and having its output coupled to terminal A4, the feedback signal then being the output signal of the 1-bit digital-to-analog converter.

(10) Many alternative architectures of analog integration circuit 101 can be envisaged. Generally, analog integration circuit 101 of a sigma-delta modulator of order p greater than or equal to 1 may comprise p analog integrators Ia.sub.j, j being an integer in the range from 1 to p, each analog integrator Ia.sub.j receiving on its input a signal equal to the difference between input signal Vin(k) weighted by a coefficient b.sub.j and feedback signal BS(k1) weighted by a coefficient a.sub.j, to which is added, if rank j of integrator Ia.sub.j is greater than 1, the output signal of the integrator Ia.sub.j1 of previous rank weighted by a coefficient c.sub.j1. Summing circuit adds input signal Vin(k) weighted by a coefficient b.sub.p+1, the output signal of integrator Ia.sub.p of rank p weighted by a coefficient c.sub.p and, if p is greater than 1, the output signal(s) of the integrators of rank p1, 1 being an integer in the range from 1 to p1, respectively weighted by coefficients c.sub.p+1. Some of the above-mentioned coefficients may be zero. For example, in the modulator of order 4 of FIG. 2, coefficients b.sub.2, b.sub.3, b.sub.4, a.sub.2, a.sub.3 and a.sub.4 are zero, and, in the modulator of order 1 of FIG. 1, coefficients b1, a1, and c1 are unit coefficients, and coefficient b2 is zero. Further, in the sub-modulator of order 2 MOD1 of FIG. 3 (which will be described hereafter), coefficients b1, a1, and c2 are unit coefficients, and coefficients a2, b2, and b3 are zero, and, in the sub-modulator of order 1 MOD1 of FIG. 3 (which will be described hereafter), coefficients b1, a1, and c1 are unit coefficients and coefficient b2 is zero.

(11) In certain architectures of order p greater than or equal to 1, summing circuit may further receive as an input feedback signal BS(k1) weighted by a specific weighting coefficient.

(12) Further, the analog integration circuit 101 of a sigma-delta modulator of order p greater than 1 may further comprise one or a plurality of analog feedbacks from the output of an analog integrator to the input of an upstream analog integrator, through a specific weighting coefficient.

(13) Further, in an architecture of order p greater than 1, the output of an integrator of rank i may be added, through a specific weighting coefficient, to the input of a downstream integrator having a rank greater than or equal to i+2.

(14) Further, delays may be introduced between the different stages of circuit 101, and/or between circuit 101 and converter 103.

(15) A limitation of the above-mentioned architectures with a single noise shaping stage, that is, comprising a single feedback loop from the output of quantization stage 103 to the input of analog integration circuit 101, is that the forming of a modulator of high order is in practice complex to implement. In particular, a problem which is posed is that the modulator may have an unstable behavior for certain levels of the input signal.

(16) To overcome this disadvantage, MASH-type (Multi Stage Noise Shaping) sigma-delta modulators, that is, modulators of order p greater than 1 formed by the series connection of a plurality of sigma-delta sub-modulators having an order smaller than p, have been provided, where each sub-modulator may have a conventional single-stage noise shaping architecture of the above-described type, that is, comprising an analog integration circuit, a 1-bit analog-to-digital converter, and a feedback loop capable of comprising a digital-to-analog converter. The operating principle of MASH-type sigma-delta modulators is for example described in article Sturdy MASH - modulator of Maghari et al. (ELECTRONICS LETTERS 26 Oct. 2006 Vol. 42 No. 22). As an example, a MASH-type sigma-delta modulator of order 2 comprises a first sub-modulator of order 1, or upstream sub-modulator, for example, of the type described in relation with FIG. 1, receiving the analog signal to be digitized on its analog input, and a second sub-modulator of order 1, or downstream sub-modulator, for example, of the type described in relation with FIG. 1, receiving on its analog input a signal representative of the quantization error of the upstream sub-modulator. During a phase of conversion of the analog input signal into a digital value, each of the sub-modulators of order 1 supplies a train of OSR bits at the output of its 1-bit analog-to-digital converter, the two bit trains being recombined in a single train of OSR bits by a logic recombination circuit. The recombined bit train is digitally integrated by a digital filtering circuit generating a digital output value of the sigma-delta converter. More generally, MASH topologies can be applied whatever the orders of the series-coupled sub-modulators, and whatever the number of series-coupled sub-modulators. The sub-modulators are then coupled so that each sub-modulator of the series association of sub-modulators, except for the first sub-modulator, receives an input signal representative of the quantization error of the previous sub-modulator. An advantage of MASH-type sigma-delta modulators is that they enable to obtain high modulation orders, while doing away with the problems usually encountered (particularly, instability problems) in the forming of conventional sigma-delta modulators (with a single noise shaping stage).

(17) FIG. 3 schematically shows in the form of functional blocks an example of a MASH-type sigma-delta modulator.

(18) In this example, the modulator is of MASH 2-1 type, that is, it comprises a first sigma-delta sub-modulator of order 2 MOD1, or upstream sub-modulator, followed by a second sigma-delta sub-modulator of order 1 MOD2, of downstream sub-modulator.

(19) Sub-modulator MOD1 has a conventional topology of order 2 with a single noise shaping stage. It comprises, as in the above-described examples, an analog integration circuit 101 having a first input A1 intended to receive an analog input signal U to be converted, a 1-bit analog-to-digital converter 103 having its input coupled to an output A3 of analog integration circuit 101, and a feedback loop coupling output A2 of analog-to-digital converter 103 to a second input A4 of analog integration circuit 101. In this example, analog integration circuit 101 comprises a subtractor 107, two analog integrators Ia.sub.1 and Ia.sub.2, and a summing circuit 109. The positive input of subtractor 107 is coupled to input A1 of circuit 101, and the negative input of subtractor 107 is coupled to input A4 of circuit 101. The output of subtractor 107 is coupled to the input of analog integrator Ia.sub.1, and the output of analog integrator Ia.sub.1 is coupled to the input of analog integrator Ia.sub.2 via a weighting coefficient c1. Summing circuit 109 adds output signal O1 of integrator Ia.sub.1 weighted by a coefficient c3 to output signal O2 of integrator Ia.sub.2, and subtracts from this sum feedback signal Y applied to input A4 of circuit 101, weighted by a coefficient d. The output of summing circuit 109 forms the output (terminal A3) of analog integration circuit 101 of sub-modulator MOD1, and is coupled to the input of analog-to-digital converter 103 of sub-modulator MOD1. In the example of FIG. 3, 1-bit analog-to-digital converter 103 of sub-modulator MOD1 is shown in the form of a summing circuit adding to output signal S1 (terminal A3) of analog integration circuit 101 of sub-modulator MOD1 a quantization noise E1 introduced by converter 103. In this example, each analog integrator Ia.sub.i comprises a summing circuit 301, and a delay operator 303 with a unit gain noted Z.sup.1. A first input of summing circuit 301 is coupled to the input of the analog integrator, the output of summing circuit 301 being coupled to the input of operator 303, and the output of operator 303 being coupled, on the one hand, to the output of the analog integrator and, on the other hand, to a second input of summing circuit 301 by a unit-gain positive feedback loop. At each operating cycle k of the sigma-delta converter, summing circuit 301 adds the signal received at cycle k at the input of integrator Ia.sub.i and a signal internal to integrator Ia.sub.i corresponding to the output signal of operator 301, that is, to the output value of integrator Ia.sub.i at the previous cycle.

(20) Sub-modulator MOD2 has a conventional topology of order 1 of the type described in relation with FIG. 1. It comprises an analog integration circuit 101 comprising a first input A1 receiving an analog signal equal to the difference between output signal Y1 of analog-to-digital converter 103 of sub-modulator MOD1 and output signal S1 of analog integration circuit 101 of sub-modulator MOD1, that is, equal to the quantization error E1 introduced by analog-to-digital converter 103 of sub-modulator MOD1. To achieve this, the sigma-delta modulator of FIG. 3 comprises, between sub-modulators MOD1 and MOD2, a subtractor 305 having its positive input coupled to output A2 of sub-modulator MOD1, having its negative input coupled to output A3 of analog integration circuit 101 of sub-modulator MOD1, and having its output coupled to input A1 of analog integration circuit 101 of sub-modulator MOD2. Sub-modulator MOD2 further comprises a 1-bit analog-to-digital converter 103 having its input connected to an output terminal A3 of its analog integration circuit 101, and a feedback loop coupling output A2 of its analog-to-digital converter 103 to a second input A4 of its analog integration circuit 101. In this example, analog integration circuit 101 of sub-modulator MOD2 comprises a subtractor 107 and an analog integrator Ia.sub.1. The positive input of subtractor 107 is coupled to input A1 of circuit 101, and the negative input of subtractor 107 is coupled to input A4 of circuit 101. The output of subtractor 107 is coupled to the input of analog integrator Ia.sub.1. The output of analog integrator Ia.sub.1 forms output A3 of analog integration circuit 101, and is coupled to the input of analog-to-digital converter 103. Analog integrator Ia.sub.1 of sub-modulator MOD2 is for example identical or similar to integrator Ia.sub.1 of sub-modulator MOD1. In the example of FIG. 3, 1-bit analog-to-digital converter 103 of sub-modulator MOD2 is shown in the form of a summing circuit adding to output signal (terminal A3) of analog integration circuit 101 of sub-modulator MOD2 a quantization noise E2.

(21) In the example of FIG. 3, the sigma-delta modulator further comprises a unit-gain delay operator 307, noted Z.sup.1, and a subtractor 309. The input of operator 307 is coupled to output A2 of sub-modulator MOD1. The positive input of subtractor 309 is coupled to the output of operator 307. The negative input of subtractor 309 is coupled to output A2 of sub-modulator MOD2. In this example, the output of subtractor 309 forms the output of the sigma-delta modulator. The circuit formed by delay operator 307 and subtractor 309 recombines output bit trains Y1 of sub-modulator MOD2 and Y2 of sub-modulator MOD2 into an output bit train Y of the sigma-delta modulator, applied to the input of the digital filter (not shown) of the sigma-delta converter.

(22) In the shown example, the feedback loop of sub-modulator MOD2 is a direct feedback loop, that is, directly coupling (or possibly via a 1-bit digital-to-analog converter) output A2 of sub-modulator MOD2 to input A4 of analog integration circuit 101 of sub-modulator MOD2. Conversely, the feedback loop of sub-modulator MOD1 is an indirect feedback loop, comprising the recombination circuit formed by elements 307 and 309. In other words, the feedback loop of sub-modulator MOD1 does not directly couple output A2 of sub-modulator MOD1 to input A4 of analog integration circuit 101 of sub-modulator MOD1, but it couples the output of the sigma-delta modulator (that is, the output of subtractor 309 supplying signal Y) to input A4 of analog integration circuit 101 of sub-modulator MOD1 (possibly via an analog-to-digital converter, not shown).

(23) The following equations describe the response of the sigma-delta modulator of FIG. 3:
Y2=z.sup.1E1+(1z.sup.1)E2

(24) $Y1=E1-\mathrm{dY}+c3\frac{z^{-1}}{1-z^{-1}}\left(U-Y\right)+c1\frac{z^{-1}}{{\left(1-z^{-1}\right)}^2}\left(U-Y\right)$
Y=z.sup.1Y1Y2

(25) FIG. 4 is a detailed electric diagram of an embodiment of the sigma-delta modulator of FIG. 3.

(26) In the example of FIG. 4, each of integrators Ia.sub.1, respectively Ia.sub.2, of sub-modulator MOD1 comprises an operational amplifier AO having its input coupled to the output by an integration capacitor Ci1, respectively Ci2. The input and the output of the operational amplifier respectively form the input and the output of the integrator. Similarly, integrator Ia.sub.1 of sub-modulator MOD2 comprises an operational amplifier AO having its input coupled to its output by an integration capacitor Ci3. Each integrator further comprises, in parallel with its integration capacitor, a reset switch controlled by a signal r. In the present description, for simplification, the switches of the modulator are designated with the same reference numerals as their respective control signals. Thus, although the switches switching the different capacitors of the modulator are different, same designations are used for simultaneously controlled switches.

(27) In this example, each of sub-modulators MOD1 and MOD2 comprises an analog integration circuit 101 and a 1-bit analog-to-digital converter 103 formed by a comparator having its input connected to an output terminal A3 of analog integration circuit 101 of the sub-modulator, and having its output connected to an output terminal A2 of the sub-modulator. In operation, an internal signal of each comparator switches from a high state to a low state according to whether the input signal of the comparator is higher or lower than a threshold, for example, equal to a reference potential applied to a reference node R of the circuit. The internal signal of the comparator is copied on its output terminal A2 at each rising or falling edge of a control signal comp.

(28) In sub-modulator MOD1, the analog integration circuit 101 is formed as follows. The output of integrator Ia.sub.1 is coupled to a first electrode of a capacitor C2 by a first switch 1d, and the output of integrator Ia.sub.2 is coupled to a first electrode of a capacitor C3 by a first switch 2d. The second electrode of capacitor C2 is coupled to the input of integrator Ia.sub.2 by a first switch 2, and the second electrode of capacitor C3 is coupled to output terminal A3 of circuit 101 by a second switch 2. The first and second electrodes of capacitor C2 are further coupled to a node R of application of a reference potential, respectively via a second switch 2d and via a first switch 1. Further, the first and second electrodes of capacitor C3 are coupled to node R respectively via a second switch 1d and via a second switch 1. Analog integration circuit 101 of sub-modulator MOD1 further comprises a capacitor C1 having a first electrode coupled to input terminal A1 of the sub-modulator by a third switch 1d and having its second electrode coupled to the input of integrator Ia.sub.1 by a third switch 2. The first and second electrodes of capacitor C1 are further respectively coupled to a node N1 receiving output signal Y of the modulator by a third switch 2d and to node R by a third switch 1. Analog integration circuit 101 of sub-modulator MOD1 further comprises a capacitor C4 having a first electrode coupled to the output of integrator Ia.sub.1 by a fourth switch 2d and having its second electrode coupled to output terminal A3 of circuit 101 by a fourth switch 2. The first and second electrodes of capacitor C4 are further coupled to node R respectively by a fourth switch 1d and by a fourth switch 1. Analog integration circuit 101 of sub-modulator MOD1 further comprises a capacitor C5 having a first electrode coupled to node N2 receiving output signal Y2 of sub-modulator MOD2 via a fifth switch 2d and having a second electrode coupled to output terminal A3 of circuit 101 by a fifth switch 2. The first and second electrodes of capacitor C5 are further respectively coupled to a node N3 receiving output signal Y1 of sub-modulator MOD1 via a fifth switch 1d and to node R via a fifth switch 1.

(29) The circuit formed by capacitors C4, C3, and C5 and by the switches 2d, 1d, 1, 2 associated with these capacitors is duplicated at the input of the analog integrator Ia.sub.1 of sub-modulator MOD2. In other words, in addition to its analog integrator Ia.sub.1, analog integration circuit 101 of sub-modulator MOD2 comprises: a capacitor C3 substantially identical to capacitor C3 (to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia.sub.2 of sub-modulator MOD1 by a sixth switch 2d and having its second electrode coupled to the input of integrator Ia.sub.1 of sub-modulator MOD2 by a sixth switch 2, the first and second electrodes of capacitor C3 being further coupled to node R respectively by a sixth switch 1d and by a sixth switch 1; a capacitor C4 substantially identical to capacitor C4 (to within manufacturing dispersions) having a first electrode coupled to the output of integrator Ia.sub.1 of sub-modulator MOD1 by a seventh switch 2d and having its second electrode coupled to the input of integrator Ia.sub.1 of sub-modulator MOD2 by a seventh switch 2, the first and second electrodes of capacitor C4 being further coupled to node R respectively by a seventh switch 1d and by a seventh switch 1; and a capacitor C5 substantially identical to capacitor C5 (to within manufacturing dispersions) having a first electrode coupled to node N2 by an eighth switch 2d and having its second electrode coupled to the input of integrator Ia.sub.1 of sub-modulator MOD2 by an eighth switch 2, the first and second electrodes of capacitor C5 being further respectively coupled to node N3 by an eighth switch 1d and to node R by an eighth switch 1.

(30) Analog integration circuit 101 of sub-modulator MOD2 further comprises a capacitor C6 having a first electrode coupled to a node N4 receiving a signal Y1 complementary to output signal Y1 of sub-modulator MOD1 via a ninth switch 1d (node N4 is for example coupled to node N3 by an inverter) and having its second electrode coupled to the input of integrator Ia.sub.1 of sub-modulator MOD2 by a ninth switch 1. The first and second electrodes of capacitor C6 are further respectively coupled to a node N5 receiving a signal Y2 complementary to output signal Y2 of sub-modulator MOD2 via a ninth switch 2d (node N5 is for example coupled to node N2 by an inverter) and to node R by a ninth switch 2.

(31) In this example, the output of integrator Ia.sub.1 of sub-modulator MOD2 is connected to output terminal A3 of analog integration circuit 101 of sub-modulator MOD2.

(32) The sigma-delta modulator of FIG. 4 further comprises a logic circuit 401 (LOGIC) comprising two binary inputs respectively coupled to output terminal A2 of 1-bit analog-to-digital converter 103 of sub-modulator MOD1 and to output terminal A2 of 1-bit analog-to-digital converter 103 of sub-modulator MOD2, and three binary outputs respectively coupled to nodes N1, N2, and N3 and supplying binary output signal Y1 of sub-modulator MOD1, binary output signal Y2 of sub-modulator MOD2, and the binary output signal Y of the modulator.

(33) A timing diagram is shown in FIG. 4 to show the chaining in a cycle of two successive switching phases P1 and P2 of the modulator switches. During phase P1, switches 2 and 2d are turned on (made conductive), switches 1 and 1d being kept off (non-conductive). At the end of phase P1, switches 2 and 2d are turned off. During phase P2, switches 1 and 1d are turned on (made conductive), switches 2 and 2d being kept off (non-conductive). At the end of phase P2, switches 1 and 1d are turned off. At the end of each of phases P1 and P2, the internal signal of comparators 103 of sub-modulators MOD1 and MOD2 is sampled (rising edges of signal comp) to generate signals Y1 and Y2.

(34) In the embodiment of FIG. 4, the function of summing circuit 109 of FIG. 3 is implemented on the one hand by capacitors C4, C3, and C5 and the switches connected to these capacitors, and on the other hand by capacitors C4, C3, and C5 and the switches connected to these capacitors.

(35) At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P1, a signal S1 resulting from the weighted sum of output signal O1 of integrator Ia.sub.1, of output signal O2 of integrator Ia.sub.2, and of output signal Y of the sigma-delta modulator, is generated on input node A3 of analog-to-digital converter 103 of sub-modulator MOD1, with S1=(O2+c3*O1d*Y), coefficients c3 and d being respectively set by the ratio of capacitances C3 and C4 and the ratio of capacitances C5 and C3. It should be noted that in this example, signal Y(k)=Y1(k1)Y2(k) is not directly applied to the input of the summing circuit, but is generated again by the latter in capacitor C5, based on signals Y1 and Y2. At the end of phase P1, signal S1 is quantized by comparator 103 of sub-modulator MOD1 to generate signal Y1. In parallel, during phase P1, signal S1 is further generated on the input node of integrator Ia.sub.1 of sub-modulator MOD2 by the duplicated summing circuit comprising capacitors C4, C3, and C5 and the switches connected to these capacitors. The value of signal S1 thus adds to the output value of integrator Ia.sub.1 of sub-modulator MOD2.

(36) During phase P2 following phase P1, signal Y1 is applied to the input of integrator Ia.sub.1 of sub-modulator MOD2. Thus, at the end of the cycle, the output value of integrator Ia.sub.1 of sub-modulator MOD2 has effectively been increased by a value corresponding to quantization noise E1 of analog-to-digital converter 103 of sub-modulator MOD1 (from which feedback signal Y2 of sub-modulator MOD2 due to the precharging of capacitor C6 to potential Y2 during phase P1 is subtracted).

(37) In the example of FIG. 4, the function of subtractor circuit 107 of sub-modulator MOD1 of FIG. 3 is implemented by capacitor C1 and the switches associated with this capacitor, and the function of subtractor circuit 107 of sub-modulator MOD2 of FIG. 3 is implemented by capacitor C6 and the switches associated with this capacitor.

(38) A disadvantage of the architecture of FIG. 4 is the hardware cost due to the duplicating, at the input of sub-modulator MOD2, of the capacitors of the summing circuit used in sub-modulator MOD1 to generate output signal S1 of analog integration circuit 101 of sub-modulator MOD1. Another disadvantage is due to the matching, which is inevitably imperfect, of the duplicated capacitors, which results in introducing an additional component of quantization noise E1 in the expression of output signal Y of the modulator.

(39) FIG. 5 is a detailed electric diagram illustrating an embodiment of a multistage noise shaping sigma-delta modulator.

(40) Functionally, the sigma-delta modulator of FIG. 5 is a MASH 2-I-type modulator identical or similar to the modulator of FIG. 3.

(41) Structurally, the sigma-delta modulator of FIG. 5 comprises elements common with the sigma-delta modulator of FIG. 4. Only the differences between the two embodiments will be detailed hereafter.

(42) Analog integration circuit 101 of sub-modulator MOD1 of the modulator of FIG. 5 is identical or similar to analog integration circuit 101 of sub-modulator MOD1 described in relation with FIG. 4.

(43) Analog integration circuit 101 of sub-modulator MOD2 of FIG. 5 differs from analog integration circuit 101 of sub-modulator MOD2 of FIG. 4 essentially in that it comprises no replication of the output summing circuit of analog integration circuit 101 of sub-modulator MOD1. In other words, analog integration circuit 101 of sub-modulator MOD2 of FIG. 5 differs from analog integration circuit 101 of sub-modulator MOD2 of FIG. 4 essentially in that it does not comprise capacitors C4, C3 and C5 and the switches associated with these capacitors.

(44) In the example of FIG. 5, the analog integration circuits 101 of sub-modulators MOD1 and MOD2 are directly series-coupled, that is, output terminal A3 of analog integration circuit 101 of sub-modulator MOD1 is connected to input terminal A1 of analog integration circuit 101 of sub-modulator MOD2 (corresponding to the input node of integrator Ia.sub.1 of sub-modulator MOD2).

(45) In the embodiment of FIG. 5, the sigma-delta modulator comprises a single 1-bit analog-to-digital converter 103, for example, a comparator identical or similar to comparators 103 of sub-modulators MOD1 and MOD2 of FIG. 4, shared by sub-modulators MOD1 and MOD2. The input of converter 103 is coupled to the output of analog integration circuit 101 of sub-modulator MOD2. More particularly, in the shown example, the sigma-delta modulator comprises a capacitor Cc having a first electrode connected to output node A3 of analog integration circuit 101 of sub-modulator MOD2 (corresponding to the output node of integrator Ia.sub.1 of sub-modulator MOD2), and having its second electrode coupled to the input of analog-to-digital converter 103 by a switch 2d. The first electrode of capacitor Cc is further coupled to the input of converter 103 by a switch 1d. Further, the second electrode of capacitor Cc is coupled to node R by a switch 1.

(46) The sigma-delta modulator of FIG. 5 further comprises a logic circuit 501 (LOGIC) comprising a binary input coupled to the output terminal of 1-bit analog-to-digital converter 103, and three binary outputs respectively coupled to nodes N1, N2, and N3 and supplying binary output signal Y1 of sub-modulator MOD1, binary output signal Y2 of sub-modulator MOD2, and binary output signal Y of the modulator.

(47) A timing diagram is shown in FIG. 5 to show the chaining in a cycle of two successive switching phases P1 and P2 of the modulator switches. As in the example of FIG. 4, during phase P1, switches 2 and 2d are turned on, switches 1 and 1d being kept off (non-conductive). At the end of phase P1, switches 2 and 2d are turned off. During phase P2, switches 1 and 1d are turned on (made conductive), switches 2 and 2d being kept off (non-conductive). At the end of phase P2, switches 1 and 1d are turned off. At the end of each of phases P1 and P2, the internal signal of comparator 103 is sampled (rising edges of signal comp) to generate signals Y1 and Y2.

(48) In the implementation of FIG. 5, the function of summing circuit 109 of FIG. 3 is implemented by capacitors C4, C3, and C5 and the switches connected to these capacitors. At each cycle k of a phase of conversion of analog input signal U into a digital value, during phase P1, a signal S1 resulting from the weighted sum of output signal O1 of integrator Ia.sub.1 of sub-modulator MOD1, of output signal O2 of integrator Ia.sub.2 of sub-modulator MOD1, and of output signal Y of the sigma-delta modulator is generated on output node A3 of analog integration circuit 101 of sub-modulator MOD1, with S1=(O2+c3*O1d*Y). Signal S1 is applied to input node A1 of analog integration circuit 101 of the downstream sub-modulator MOD2, that is, in the shown example, to the input of integrator Ia.sub.1 of sub-modulator MOD2. Signal S1 is thus integrated by integrator Ia.sub.1 of sub-modulator MOD2, that is, during phase P1, the value of integrator Ia.sub.1 is incremented by value S1. Prior thereto, during phase P2 of the previous cycle during which switches 1 are conductive, capacitor Cc is charged to the output value of integrator Ia.sub.1. Thus, during the next phase P1 (1 off), output coupling capacitor Cc introduces at the input of comparator 103 a voltage shift with respect to the current output value of integrator Ia.sub.1 equal to the output value of integrator Ia.sub.1 at the end of the previous cycle. In other words, during phase P1, the voltage variation observed at the input of comparator 103 due to coupling capacitor Cc corresponds to quantity S1. At the end of phase P1, the value S1 observed on the second electrode of capacitor Cc is quantized by comparator 103 to generate signal Y1.

(49) During phase P2 following phase P1, signal Y1 is applied to the input of integrator Ia.sub.1 of sub-modulator MOD2 (node N4). Thus, during phase P2, the output value of integrator Ia.sub.1 of sub-modulator MOD2 is incremented by a value corresponding to the quantization noise E1 introduced by analog-to-digital converter 103 during the quantization of signal S1, from which feedback Y2 is subtracted (node N5). At the end of phase P2, the output signal of integrator Ia.sub.1 of sub-modulator MOD2 is directly quantized by comparator 103 (without passing through coupling capacitor Cc) to obtain signal Y2.

(50) Thus, functionally, the circuit of FIG. 5 behaves substantially in the same way as the circuit of FIG. 3. However, in the implementation of FIG. 5, rather than duplicating the circuit for generating signal S1 at the input of sub-modulator MOD2 as in the implementation of FIG. 4, it is provided to reconstruct signal S1 by diverting the output signal of integrator Ia.sub.1 of downstream modulator MOD2 through coupling capacitor Cc.

(51) An advantage of the embodiment of FIG. 5 is that signal S1 is not duplicated, which, in addition to the advantage in terms of hardware cost due to the suppressing of capacitors C4, C3, C5 and of their switches, enables, during the generation of quantization error signal E1=Y1S1, to avoid risks of lack of integrity of signal S1 due to a mismatch of the duplicated capacitors.

(52) Another advantage of the implementation of FIG. 5 is that it enables to spare a 1-bit analog-to-digital converter with respect to the implementation of FIG. 4.

(53) Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. In particular, the described embodiments are not limited to the example of MASH 2-I-type sigma-delta modulator architecture described in relation with FIGS. 3 and 5. More generally, the provided solution, implementing an analog circuit for diverting the output signal of an analog integration circuit 101 of a downstream sub-modulator to reconstruct an output signal of an analog integration circuit 101 of an upstream sub-modulator may be used in any type of sigma-delta modulator, comprising at least two cascaded sub-modulators.

(54) Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.