METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE

Abstract

A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

Claims

1. A method comprising: forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an interlayer dielectric (ILD) over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of source/drain contacts (CAs) adjacent a first portion of each PC and gate contacts (CBs) over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a trench silicide (TS) contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

2. The method according to claim 1, further comprising: removing the mask prior to selectively growing the metal capping layer.

3. The method according to claim 1, comprising: selectively growing a tungsten (W) or cobalt (Co) metal capping layer over the TS contacts.

4. The method according to claim 3, comprising growing the metal capping layer to a thickness of 5 to 10 nanometers (nm).

5. The method according to claim 4, comprising: forming the metal capping layer to cover any exposed corner of the nitride capping layer of an adjacent PC.

6. The method according to claim 1, comprising: forming an organic planarization layer (OPL) mask over the oxide ILD.

7. The method according to claim 1, comprising: forming the oxide ILD comprising a high density plasma (HDP) oxide, plasma-enhanced chemical vapor deposition (PECVD) oxide, or tetraethyl orthosilicate (TEOS) oxide over the PCs.

8. The method according to claim 1, comprising: removing the nitride capping layer by etching selective to the oxide ILD and metal of the PCs.

9. The method according to claim 8, wherein the nitride capping layer comprises silicon nitride (SiN).

10. The method according to claim 1, wherein the PCs comprise high-k metal gate (HKMG).

11. The method according to claim 1, comprising forming the S/D regions by selective epitaxy.

12. A device comprising: metal gates (PC) formed over a substrate, each metal gate having a nitride capping layer over a first portion; source/drain (S/D) regions formed on sides of the first portion of the PCs; trench silicide (TS) contacts formed over the S/D regions; source/drain contacts (CAs) formed over the TS contacts; gate contacts (CBs) formed over a second portion of the PCs; an interlayer dielectric (ILD) formed over the PCs and between the CAs and CBs; and a metal capping layer formed between the TS contacts and the CAs, the metal capping layer covering a corner portion of the nitride capping layer of an adjacent PC.

13. The device according to claim 12, wherein the nitride capping layer comprises silicon nitride (SiN).

14. The device according to claim 12, wherein the PCs comprise high-k metal gates (HKMGs).

15. The device according to claim 12, wherein the S/D regions comprise selective epitaxy S/D regions.

16. The device according to claim 12, wherein the metal capping layer comprises tungsten (W) or cobalt (Co).

17. The method according to claim 16, wherein: the metal capping layer has a thickness of 5 to 10 nanometers (nm), and the ILD comprises a high density plasma (HDP) oxide, plasma-enhanced chemical vapor deposition (PECVD) oxide, or tetraethyl orthosilicate (TEOS) oxide.

18. A method comprising: forming metal gates (PC) and source/drain (S/D) regions over a substrate; forming an interlayer dielectric (ILD) over the PCs and S/D regions; forming an organic planarization layer (OPL) mask over the ILD; concurrently patterning the OPL mask for formation of source/drain contacts (CAs) adjacent a first portion of each PC and gate contacts (CBs) over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a silicon nitride (SiN) capping layer formed over each the PC and a trench silicide (TS) contact formed over each S/D region; removing the mask; selectively growing a metal capping layer to a thickness of 5 to 10 nanometers (nm) over the TS contacts formed over the S/D regions; removing the SiN capping layer from the second portion of each PC; and metal filling the trenches to form the CAs and CBs.

19. The method according to claim 18, wherein the metal capping layer comprises tungsten (W) or cobalt (Co).

20. The method according to claim 19, comprising: forming the metal capping layer to cover any exposed corner of the nitride capping layer of an adjacent PC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawing and in which like reference numerals refer to similar elements and in which:

[0016] FIG. 1 schematically illustrates a top view of a conventional semiconductor device; and

[0017] FIGS. 2A through 7A illustrate cross-sectional views along directional arrow X in FIG. 1, and FIGS. 2B through 7B illustrate cross-sectional views along directional arrow Y in FIG. 1, of a process for fabricating a semiconductor device, in accordance with an exemplary embodiment.

DETAILED DESCRIPTION

[0018] In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term about.

[0019] The present disclosure addresses and solves the current problems of CB to CA misalignment and higher costs associated with additional masks used to produce CAs and CBs. Methodology in accordance with embodiments of the present disclosure includes forming metal PCs and S/D regions over a substrate; forming an ILD over the PCs and S/D regions; forming a mask over the ILD; concurrently patterning the mask for formation of CAs adjacent a first portion of each PC and CBs over a second portion of the PCs; etching through the mask, forming trenches extending through the ILD down to a nitride capping layer formed over each PC and a TS contact formed over each S/D region; selectively growing a metal capping layer over the TS contacts formed over the S/D regions; removing the nitride capping layer from the second portion of each PC; and metal filling the trenches, forming the CAs and CBs.

[0020] Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.

[0021] Adverting to FIGS. 2A and 2B, cross sectional views of a semiconductor device along directional arrow X (FIG. 1) and directional arrow Y (FIG. 1) are respectively shown. Substrate 201 is provided over which a plurality of metal PCs 203 are formed. The PCs include high-k metal gates (HKMGs) including sidewall spacers composed of SiN, SiBCN, SiOC. PCs on the edges of FIGS. 2A and 2B may be dummy PCs at the edges of a cell, and the other PCs (only one is shown for illustrative convenience) are active PCs. STI regions 205 are formed under the metal PCs 203 outside of the active region (as in FIG. 2B) and under the dummy PCs in the active region (as in FIG. 2A). S/D regions 207 are formed at opposite sides of the active metal PCs 203. The S/D regions 207 include selective epitaxy S/D regions. A SiN capping layer 209 is formed on upper of the metal PCs 203. TS contacts 211 are formed over the S/D regions 207 and between the metal PCs 203. The TS contacts 211 are formed of silicide at a bottom (e.g. nickel (Ni), titanium (Ti) or a nickel platinum (NiPt) silicide) with a conducting metal at a top (e.g W or Co, with a thin nucleation/adhesion layer formed at sidewall). An ILD 213 is formed over and between the metal PCs 203. The ILD 213 includes an oxide (e.g. plasma-enhanced chemical vapor deposition (PECVD) oxide, HDP oxide, tetraethyl orthosilicate (TEOS) oxide, etc). A mask 215 is concurrently patterned for CAs and CBs over the ILD 213 using either conventional optical lithography if the dimension is relaxed or EUV lithography for advanced technology node. The final pattern is transferred to mask material 215, which could be an OPL. The patterning of the mask 215 corresponds to the CAs and CBs to be formed in the ILD 213.

[0022] Adverting to FIGS. 3A and 3B, an etching step is performed through the mask 215, forming trenches 301 and 303 extending through the ILD 213 down to the TS contacts 211 formed over each S/D region 207 and the SiN capping layer 209 formed over each active PC 203, respectively. The etching step includes an oxide etch which is selective to SiN. The trenches 301 and 303 are formed at an offset such that the CAs will contact the TS contacts in a first portion of the PCs 203, and the CBs will contact a second portion of the PCs 203. Following the etching step through mask 215, the mask 215 is removed, as shown in FIGS. 4A and 4B to expose an upper surface of the ILD 213.

[0023] Adverting to FIGS. 5A and 5B, a metal capping layer 501 is selectively grown over the TS contacts 211 formed over the S/D regions 207. The metal capping layer 501 is formed of W or Co. The TS contacts 211 can be the same metal or different from the metal capping layer 501. The metal capping layer 501 is grown to a thickness of 5 to 10 nm over the TS contacts 211. As shown by circled region 503, a corner of the SiN capping layer 209 is covered with the metal capping layer 501. The metal capping layer 501 is formed to cover any exposed corner of the nitride capping layer 209 of an adjacent PC 203.

[0024] Adverting to FIGS. 6A and 6B, the SiN capping layer 209 is removed from the second portion of each PC 203 by a SiN open etch that is selective to oxide and metal. Openings 601 are formed on the sides of the PCs 203, and an upper surface of the PCs is exposed. This SiN open etching step does not adversely affect the circled region 503 since this corner of the SiN capping layer 209 is covered and protected by the metal capping layer 501.

[0025] Adverting to FIGS. 7A and 7B, a metal filling of the trenches forms the CAs 701 and the CB 703. Although not shown, a metal liner can be formed in the trenches prior to the metal filling step. Suitable metals for the metal filling step include copper (Cu), titanium (Ti), W, Co, and aluminum (Al).

[0026] The embodiments of the present disclosure can achieve several technical effects, including concurrently forming CAs and CBs using a single EUV mask and eliminating misalignment between CAs and CBs, which in turn reduces the risk of CB to CA shorts. The present disclosure enjoys industrial applicability in any of various industrial applications, e.g., microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices, particularly for advanced technology nodes.

[0027] In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.