ELECTROSTATIC DISCHARGE PROTECTION DEVICE FOR HIGH VOLTAGE

Abstract

A circuit for protecting against electrostatic discharge events has a semiconductor substrate (200) of first conductivity embedding a first diode in a well (260) of opposite second conductivity, the diode's anode (111) tied to an I/O pin-to-be-protected (101) at a first voltage, and the first diode's cathode (112) connected to the first drain (123) of a first MOS transistor in the substrate. The first MOS transistor's first gate (122) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain (670) merged with the first source of the first MOS transistor, and its second source (131), together with its second gate (132), tied to ground potential (140).

Claims

1. A method for fabricating a circuit for protecting against electrostatic discharge events, comprising: forming a cascode including at least a first MOS transistor tied to a second MOS transistor in series in a semiconductor substrate of first conductivity; forming a first diode in a well of opposite second conductivity in the semiconductor substrate; connecting an first anode of the first diode to an I/O pin-to-be-protected at a first voltage, and a first cathode of the first diode to the first drain of the first MOS transistor; connecting a first gate of the first MOS transistor to a bias node; and connecting a second drain of the second MOS transistor to a first source of the first MOS transistor, and a second source of the second MOS transistor, together with a second gate of the second MOS transistor to a ground node.

2. The method of claim 1, wherein the semiconductor substrate further has a first resistivity so that the second source is coupled to the first drain by a substrate resistance, and the well further has a second resistivity so that the first anode is tied to the first cathode by a well resistance, and the first anode is coupled to the second source by the sum of the substrate and well resistances.

3. The method of claim 1, further comprising forming a second diode having a second cathode connected to the first drain of the first MOS transistor and a second anode connected to the ground node.

4. The method of claim 3, further including forming a third diode having a third cathode tied to the I/O pin and a third anode connected to the ground node.

5. The method of claim 1, further including forming a third diode having a third cathode tied to the I/O pin and a third anode connected to the ground node.

6. The method of claim 1, wherein the first drain of the first MOS transistor has a reverse breakdown voltage greater than the first voltage.

7. The method of claim 6, wherein a parasitic silicon-controlled-rectifier (SCR) formed between the second source and the first anode has a trigger voltage V.sub.trig, set by the reverse breakdown of the first drain, inversely proportional to the resistance sum, and a holding voltage V.sub.hold directly proportional to the resistance sum.

8. The method of claim 7 wherein, V.sub.hold is directly proportional to the SCR spacing between the second source and the first anode.

9. The method of claim 1, wherein the contact regions of the first source and the second drain are merged.

10. The method of claim 1, further including forming one or more additional biased MOS transistors connected in series.

11. A method for fabricating a circuit for protecting against electrostatic discharge events, comprising: forming an integrated circuit input/output (I/O) pin to be protected at a first voltage; forming a first MOS transistor having a first source, first gate, and first drain, in a semiconductor substrate of first conductivity; forming in the substrate a second MOS transistor having second source, second gate, and second drain, and connecting the second drain to the first source; connecting the source and the gate of the second transistor to a ground node; forming a first diode in a well of opposite second conductivity, the first diode having first anode and first cathode; and connecting the first anode to the I/O pin, the first drain to the first cathode, and the first gate to a second voltage node.

12. The method of claim 11, wherein the substrate further has a first resistivity so that the second source is coupled to the first drain by a substrate resistance, and the well further has a second resistivity so that the diode anode is tied to the diode cathode by a well resistance.

13. The method of claim 12, wherein a parasitic silicon-controlled rectifier has a trigger voltage V.sub.trig inversely proportional to the sum of the substrate resistance and the well resistance, and a holding voltage V.sub.hold directly proportional to the sum of the resistances.

14. The method of claim 11, further comprising forming a second diode having a second cathode connected to the first drain of the first MOS transistor and a second anode connected to the ground node.

15. The method of claim 14, further including forming a third diode having a third cathode tied to the I/O pin and a third anode connected to the ground node.

16. A method of fabricating an electrostatic discharge protection circuit, comprising: forming a well of an opposite second conductivity type in a semiconductor substrate of first conductivity type; forming a first diode in the well of opposite second conductivity, the first diode having an anode tied to an I/O pin; forming a first MOS transistor having a first drain, first source, and first gate, wherein the first gate is coupled to a bias node; forming a second MOS transistor having a second drain, second source, and second gate, wherein the second drain is coupled to the first source of the first MOS transistor, and the second source, together with the second gate, are coupled to a ground node; and connecting a cathode of the first diode to the first drain of the first MOS transistor, such that the first diode is connected between the I/O pin and the first MOS transistor.

17. The method of claim 16, further comprising forming a second diode having a second cathode connected to the first drain of the first MOS transistor and a second anode connected to the ground node.

18. The method of claim 17, further comprising forming a third diode having a third cathode connected to the I/O pin and a third anode connected to the ground node.

19. The method of claim 16, further comprising forming a third diode having a third cathode connected to the I/O pin and a third anode connected to the ground node.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1 shows a block diagram of an ESD protection circuit for high voltages, using a diode-isolated grounded gate MOS structure including a diode in series with a voltage divider based on MOS transistors tied in series.

[0017] FIG. 2 illustrates a top view of an embodiment of the protection circuit of FIG. 1 in a p-type silicon substrate.

[0018] FIG. 3 depicts a hybrid top view and circuit diagram of the protection circuit in FIG. 2, emphasizing the arrangement of circuit portions determining certain protection parameters.

[0019] FIG. 4 shows a schematic cross section of the circuit of FIG. 2, a diode in an n-well in p-type substrate semiconductor tied in series with a first and a second nMOS transistor to facilitate the balanced formation of protective parasitic lateral bipolar transistors and a parasitic SCR for high voltage according to the invention.

[0020] FIG. 5 displays the current-voltage characteristic of the parasitic SCR of FIG. 4.

[0021] FIG. 6 illustrates a top view of another embodiment of the protection circuit of FIG. 1 in a p-type silicon substrate.

[0022] FIG. 7 depicts a hybrid top view and circuit diagram of the protection circuit in FIG. 6, emphasizing the arrangement of circuit portions determining certain protection parameters.

[0023] FIG. 8 shows a schematic cross section of the circuit of FIG. 6, a diode in an n-well in p-type substrate semiconductor tied in series with a first and a second nMOS transistor to facilitate the balanced formation of protective parasitic bipolar transistors and a parasitic SCR for high voltage according to the invention.

[0024] FIG. 9 displays the current-voltage characteristic of the parasitic SCR of FIG. 8.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0025] FIG. 1 shows the block diagram of an embodiment of the invention. The concept referred to as the diode isolated grounded-gate MOS structure for protecting pins of a semiconductor device against ESD events includes the input/output (I/O) pin 101 to be protected in series with a forward biased diode 110 and an MOS transistor 130 to ground potential 140. Serially inserted between diode 110 and transistor 130 is another forward biased MOS transistor 120, which has a gate 122 activated by a bias from an outside voltage potential. Pin 101 is connected with the anode 111 of diode 110; the cathode 112 of the diode is tied to the drain 123 of MOS transistor 120.

[0026] MOS transistor 120 is herein referred to as first transistor, and MOS transistor 130 is referred to as second transistor. Drain 133 of second transistor 130 is tied to source 121 of first transistor 120; gate 132 and source 131 of the second transistor are connected to ground potential 140.

[0027] The semiconductor device, usually an integrated circuit (I/C), with pin 101 is embedded in a semiconductor substrate of first conductivity and first resistivity. In the examples of the following Figures, the substrate is p-type, or at least a p-type well; in other embodiments, the substrate may be n-type. The maximum voltage applied to pin 101 is referred to herein as first voltage.

[0028] The term substrate refers herein to the starting semiconductor wafer, which, in present manufacturing generally and also in the examples of the following Figures, typically has p-type doping. With this selection, the semiconductor substrate is a p-type substrate, the MOS transistor an nMOS transistor, the diode a pn-, and the silicon-controlled rectifier a pnpn-SCR. It should be stressed, however, that the invention and all description also cover the case where the substrate has n-type doping. Frequently, but not necessarily, an epitaxial layer of the same conductivity type as the substrate has been deposited over the substrate; in this case the term substrate refers to epitaxial layer plus starting semiconductor. For preferred p-type substrates, the sheet resistance range is from about 200 to 500 /square; the selection of the substrate resistivity and sheet resistance determines the size of the substrate resistance.

[0029] FIG. 1 further shows a second diode 150 with its second cathode 151 tied to the first cathode 112 of first diode 110 and to first drain 123 of first MOS transistor 120. The second anode 152 is connected to ground. While the electrical potential at pin 101 keeps rising in a positive discharge event, diode 150 reaches reverse avalanche breakdown. Then the vertical parasitic pnp transistor 411 (see FIG. 4) turns on and elevates the potential of the local substrate 200. With the local substrate potential rising further, the parasitic npn transistor 412 turns on, which initiates the parasitic SCR (see FIG. 4).

[0030] FIG. 1 shows a third diode 155, which provides protection against negative discharge events, while the circuitry with first diode 110 provides protection against positive discharge events.

[0031] The protection circuitry of the block diagram of FIG. 1 is displayed in FIG. 2 as a schematic top view of electrical components in a semiconductor substrate. The selection of the electrical conductivities is exemplary. The p-type semiconductor substrate is designated 200 and the n-well is designated 260; I/O pad 101 with its first voltage and ground potential 140 are considered external to semiconductor substrate 200. With the substrate p-type, diode 110 is fabricated in an n-well 260, and first MOS transistors 120 and second MOS transistor 130 are nMOS transistors, preferably multi-finger transistors. The n.sup.+ drain region 123 (referred to as first drain) of first transistor 120 is connected to diode cathode 112 (doped n.sup.+) and the n.sup.+ source region 121 (referred to as first source) of first transistor 120 is connected to the n.sup.+ drain region 133 (referred to as second drain) of second transistor 130. First gate 122 can be biased to a potential (referred to as second voltage) smaller than the first voltage and is applied to reduce the first voltage of the I/O pin by the amount of the second voltage.

[0032] The n.sup.+ drain region 133 (referred to as second drain) of second transistor 130 is connected to n.sup.+ source region 121 (referred to as first source) and the n.sup.+ source region 131 (referred to as second source) of second transistor 130 is connected to ground potential (V.sub.SS) 140, indicated by the p.sup.+ well in the p-type substrate. The metallization of second gate 132 is also tied to ground potential. FIGS. 3 and 4 display the actions of the diode isolated grounded gate MOS structure during an ESD event.

[0033] In an ESD event, the parasitic lateral npn bipolar transistor, marked in FIG. 4 by dashed outlines, from first drain 123 to second source 131 will trigger, after diode 150 has reached reverse avalanche breakdown and parasitic pnp transistor 411 has turned on and elevated the local substrate potential. One portion of the protection relies on the mode of the parasitic bipolar transistor 412 formed by the second MOS transistor 130 to provide a low impedance current to ground; source 131 acts as an emitter, drain 123 as a collector, and the resistive substrate 200 as the base. The protection level or failure threshold (trigger current I.sub.t2) can be set by varying the nMOS transistor width; the protection level thus depends on the layout style. Under stress conditions, the dominant current conduction path between the protected pin and ground involves the parasitic bipolar transistor 412 of that nMOS transistor. This parasitic bipolar transistor operates in the snapback region under pin positive with respect to ground stress events. The concept also works for drain-extended nMOS transistors. The concept has been applied to low-capacitance ESD protection where the substrate pump from the vertical pnp transistor 411 (inherent in the diode) provides uniform trigger for the MOS transistor. A transient pulse on pin 101 connected to p.sup.+ node 111 activates vertical pnp transistor 411 to pump the substrate locally with holes. The pumping supports an increase of the substrate potential so that the parasitic bipolar transistor 412, formed from first drain 123 to second source 131, is turned on. In these applications, the layout of the diode in relation to the MOS transistor is arbitrary, and the diode is generally placed at some distance next to a side of the MOS layout.

[0034] Under the assumption that the complete ESD current is to be discharged through the parasitic bipolar transistor as described above, the layout of the nMOS transistor 130 can be calculated on the basis that the discharge of the 4 kV of the HBM requires an active transistor width of 400 m based on the empirical HBM performance of 10 V/m for a substrate-pumped transistor. Source and drain regions are designed to typically have individual widths of 40 m; consequently, 10 gates are needed. If transistor 130 were to handle the ESD event as a substrate-pumped MOS clamp, the transistor area would result in a capacitance of about 500 fF.

[0035] In addition to the action of the parasitic bipolar transistor of the nMOS transistor for discharging an ESD current to ground, FIG. 4 illustrates a parasitic silicon controlled rectifier (SCR) action. In order for the SCR to accept a significant portion of the ESD discharge current, the n-well 260 is to be laid out so that it is positioned in proximity to the regions of the MOS transistor, preferably at the minimum distance allowed by the design rules. In FIG. 4, the close proximity is indicated by distance 460. For many protection devices, distance 460 is preferably between 1 and 5 m. For a selected diode resistivity, the diode area is determined so that the diode on-resistance is low enough to allow sufficient current to flow through the diode to provide reliable substrate pumping for turning on the MOS transistor. Consequently, for many protection devices, the diode area is approximately a third of the MOS transistor area.

[0036] In the well 260 is at least one diode, its anode region 111 of the first conductivity type connected to I/O pad 101 and its cathode region 112 of the opposite conductivity type, connected to transistor drain 123. The layout is executed so that the diode-anode 111 is positioned in proximity to, and aligned with, the source region 122 of the MOS transistor, and the diode-cathode 112 is positioned in proximity to, and aligned with, the drain region 131.

[0037] The layout aspects are summarized in FIG. 3 by the geometrical consideration 301 referred to as SCR Spacing. The expression SCR Spacing concerns not only a geometrical distance 301, but also includes the sum of the substrate resistance R.sub.sub and the well resistance. The trigger voltage V.sub.trig of the SCR is inversely proportional to the sum of the resistances. Since a small V.sub.trig is desirable, as long as V.sub.trig remains larger than the I/O voltage at pin 101, it is preferred to keep the resistance sum, and especially R.sub.sub, at large values.

[0038] Based on the proximity layout of the transistor and diode regions and the electrical connections, a localized parasitic silicon-controlled rectifier (SCR) pnpn is created. In the schematic FIG. 8, the parasitic pnpn SCR is indicated by its pnp transistor portion 411 and its npn transistor portion 812. It comprises an SCR-anode formed by the diode-anode 111; a first base region formed by the n-well 260; a second base region formed by the p-substrate 200; and an SCR-cathode formed by the transistor source 131. The I/O pad 101 becomes the SCR-anode, and ground potential 131 (V.sub.SS) becomes the SCR-cathode. The parasitic SCR offers efficient ESD protection because it is operable to distribute an ESD current at low voltages. A further layout advantage of the embodiment of FIG. 2 is the fact that the gate 122 of MOS transistor 120 does not need a resistor to ground potential 130, since the successful ESD protection of FIG. 2 does not fully depend on an efficient npn device with additional circuit connections.

[0039] FIG. 5 illustrates the current-voltage characteristic 500 of the parasitic SCR as created by the embodiment of FIG. 4. As mentioned, the trigger voltage V.sub.trig1 (501) has to be greater than the first voltage applied to the I/O pin, and is inversely proportional to the sum of the substrate resistance R.sub.sub and n-well resistance. Since it is desirable to have a low V.sub.trig, the resistance sum should be reasonably large, as is indeed the case in FIG. 3 based on the extended SCR spacing. On the other hand, a large sum of resistances causes a relatively high value of the SCR holding voltage V.sub.hold1 (502), since the holding voltage is directly proportional to the SCR spacing.

[0040] It is preferred, however, to have a relatively low value of the SCR holding voltage for robust ESD protection and low power dissipation. Consequently, there is an effort to minimize the SCR spacing, or equivalently, to keep the sum of the substrate resistance R.sub.sub and n-well resistance small. The effort is described in the embodiment illustrated by FIGS. 6 to 9; the impact of this endeavor is shown in FIG. 9, which plots the current-voltage characteristic of the parasitic SCR on the same coordinates scale as in FIG. 5.

[0041] The preferred embodiment is shown in FIG. 6 as a schematic top view of the electrical components in a semiconductor substrate. Analogous to FIG. 2, the selection of the electrical conductivities in FIG. 6 is exemplary. The p-type semiconductor substrate is designated 600 and the n-well is designated 660; I/O pad 101 with its first voltage and ground potential 140 are considered external to semiconductor substrate 600. With the substrate p-type, diode 610 is fabricated in an n-well 660, and first MOS transistors 620 and second MOS transistor 630 are nMOS transistors, preferably multi-finger transistors. The n.sup.+ drain region 623 (referred to as first drain) of first transistor 620 is connected to diode cathode 612 (doped n.sup.+). The n.sup.+ source region 621 (referred to as first source) of first transistor 620 is merged with the n.sup.+ drain region 633 (referred to as second drain) of second transistor 630. The merged n.sup.+ region is designated 670. First gate 622 can be biased to a potential (referred to as second voltage) smaller than the first voltage and is applied to reduce the first voltage of the I/O pin by the amount of the second voltage.

[0042] While the n.sup.+ drain region 633 (referred to as second drain) of second transistor 630 is merged with n.sup.+ source region 621 (referred to as first source) to form n.sup.+ region 670, the n.sup.+ source region 631 (referred to as second source) of second transistor 630 is connected to ground potential (V.sub.SS) 140, indicated by the p.sup.+ well in the p-type substrate. The metallization of second gate 632 is also tied to ground potential; the second transistor is thus not activated and does not carry current. FIGS. 7 and 8 display the actions of the diode isolated grounded gate MOS structure during an ESD event.

[0043] FIG. 8 illustrates the n.sup.+ region 670 formed by merging the second drain region with the first source region. A consequence of the merging is a reduction of the geometrical distance between diode anode 111 and second source 131. This layout aspect is referred to as SCR Spacing in FIG. 7. The expression SCR Spacing concerns not only a geometrical distance 701, but also includes the sum of the substrate resistance R.sub.sub and the well resistance. As mentioned, the SCR holding voltage V.sub.hold is directly proportional the SCR spacing, the desirable low V.sub.hold2 (902) of FIG. 9 can be achieved by the reduced SCR spacing 701. On the other hand, since the trigger voltage V.sub.trig of the SCR is inversely proportional to the sum of the resistances, the reduction SCR spacing may be compensated by increasing the R.sub.sub resistivity.

[0044] In order for the SCR to accept a significant portion of the ESD discharge current, the n-well 260 is to be laid out so that it is positioned in proximity to the regions of the first MOS transistor, preferably at the minimum distance 460 allowed by the design rules. For many protection devices, distance 460 is preferably between 1 and 5 m. As mentioned above, for a selected diode resistivity, the diode area is determined so that the diode on-resistance is low enough to allow sufficient current to flow through the diode to provide reliable substrate pumping for turning on the MOS transistor. Consequently, for many protection devices, the diode area is approximately a third of the MOS transistor area.

[0045] Based on the proximity layout of the transistor and diode regions and the electrical connections, a localized parasitic silicon-controlled rectifier (SCR) pnpn is created. In the schematic FIG. 8, the parasitic pnpn SCR is indicated by its pnp transistor portion 411 and its npn transistor portion 812. It comprises an SCR-anode formed by the diode-anode 111; a first base region formed by the n-well 260; a second base region formed by the p-substrate 200; and an SCR-cathode formed by the transistor source 131. The I/O pin 101 becomes the SCR-anode, and ground potential 131 (V.sub.SS) becomes the SCR-cathode. The parasitic SCR offers efficient ESD protection because it is operable to distribute an ESD current at low voltages.

[0046] FIG. 9 illustrates the current-voltage characteristic 900 of the parasitic SCR as created by the embodiment of FIG. 8. As mentioned, the trigger voltage V.sub.trig2 (901) has to be greater than the first voltage applied to the I/O pin, and is inversely proportional to the sum of the substrate resistance R.sub.sub and n-well resistance. The desirable small holding voltage V.sub.hold2 (902), which is directly proportional to the SCR spacing, is achieved by the small SCR Spacing 701 illustrated in FIG. 7; small SCR spacing is equivalent to a small sum of substrate resistance R.sub.sub and n-well resistance. On the other hand, since it is desirable to have a low V.sub.trig, the resistance sum should be reasonably large, which can be achieved by high resistivity values.

[0047] While this invention has been described in reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. As an example, the embodiments are effective in pMOS transistors as well as in nMOS transistors to create ESD protection. As another example, the substrate material may include silicon, silicon germanium, gallium arsenide, gallium nitride, and other semiconductor materials employed in manufacturing.

[0048] As yet another example, while the MOS transistor is preferably a multi-finger transistor, the concept of the invention can be applied to a methodology wherein the number of poly-fingers is reduced to control the trigger point. A MOS transistor with diode area portions positioned in proximity to its four sides may operate with fewer poly fingers while contacts, vias and metals still remain the same, resulting in higher trigger and holding voltages.

[0049] As yet another example, for system level ESD protection, where SCR action is to be avoided, the proximity spacing of the diode portions relative to the MOS transistor may be adjusted until only uniform npn conduction is achieved and the protection device functions only as a large efficient npn for substrate trigger with a relatively large holding voltage.

[0050] It is therefore intended that the appended claims encompass any such modifications or embodiments.